drm/amd/display: Fix underflow for fused display pipes case

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[Why]
Depend on res_pool->res_cap->num_timing_generator to query timing
gernerator information, it would case underflow at the fused display
pipes case.
Due to the res_pool->res_cap->num_timing_generator records default
timing generator resource built in driver, not the current chip.

[How]
Some ASICs would be fused display pipes less than the default setting.
In dcnxx_resource_construct function, driver would obatin real timing
generator count and store it into res_pool->timing_generator_count.

Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Reviewed-by: Anthony Koo <Anthony.Koo@amd.com>
Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Signed-off-by: Yi-Ling Chen <Yi-Ling.Chen2@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

...

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Yi-Ling Chen 2021-12-13 16:13:26 +08:00 • committed by Alex Deucher

parent eac4c54bf7

commit 771ced73fc

1 changed files with 6 additions and 1 deletions

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7

drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

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