clk: bcm2835: Fix setting of PLL divider clock rates

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Our dividers weren't being set successfully because CM_PASSWORD wasn't
included in the register write.  It looks easier to just compute the
divider to write ourselves than to update clk-divider for the ability
to OR in some arbitrary bits on write.

Fixes about half of the video modes on my HDMI monitor (everything
except 720x400).

Cc: stable@vger.kernel.org
Signed-off-by: Eric Anholt <eric@anholt.net>
Signed-off-by: Michael Turquette <mturquette@baylibre.com>

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Eric Anholt 2016-02-15 19:03:57 -08:00 • committed by Michael Turquette

parent 92e963f50f

commit 773b3966dd

1 changed files with 7 additions and 5 deletions

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drivers/clk/bcm/clk-bcm2835.c

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