diff --git a/drivers/gpu/drm/amd/include/asic_reg/mmhub/mmhub_5_0_1_offset.h b/drivers/gpu/drm/amd/include/asic_reg/mmhub/mmhub_5_0_1_offset.h index a65e78e130f6..32338867fc60 100644 --- a/drivers/gpu/drm/amd/include/asic_reg/mmhub/mmhub_5_0_1_offset.h +++ b/drivers/gpu/drm/amd/include/asic_reg/mmhub/mmhub_5_0_1_offset.h @@ -1,17 +1,1501 @@ /* - * SPDX-License-Identifier: MIT + * Copyright 2026 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. * - * Copyright (c) 2026 Advanced Micro Devices, Inc. All rights reserved. */ - - #ifndef _mmhub_5_0_1_OFFSET_HEADER #define _mmhub_5_0_1_OFFSET_HEADER -// addressBlock: mmhub_mmhubdec + +// addressBlock: mmhub_dagb_dagbdec +// base address: 0x68000 +#define regDAGB0_RDCLI0 0x0000 +#define regDAGB0_RDCLI0_BASE_IDX 1 +#define regDAGB0_RDCLI1 0x0001 +#define regDAGB0_RDCLI1_BASE_IDX 1 +#define regDAGB0_RDCLI2 0x0002 +#define regDAGB0_RDCLI2_BASE_IDX 1 +#define regDAGB0_RDCLI3 0x0003 +#define regDAGB0_RDCLI3_BASE_IDX 1 +#define regDAGB0_RDCLI4 0x0004 +#define regDAGB0_RDCLI4_BASE_IDX 1 +#define regDAGB0_RDCLI5 0x0005 +#define regDAGB0_RDCLI5_BASE_IDX 1 +#define regDAGB0_RDCLI6 0x0006 +#define regDAGB0_RDCLI6_BASE_IDX 1 +#define regDAGB0_RDCLI7 0x0007 +#define regDAGB0_RDCLI7_BASE_IDX 1 +#define regDAGB0_RDCLI8 0x0008 +#define regDAGB0_RDCLI8_BASE_IDX 1 +#define regDAGB0_RDCLI9 0x0009 +#define regDAGB0_RDCLI9_BASE_IDX 1 +#define regDAGB0_RDCLI10 0x000a +#define regDAGB0_RDCLI10_BASE_IDX 1 +#define regDAGB0_RDCLI11 0x000b +#define regDAGB0_RDCLI11_BASE_IDX 1 +#define regDAGB0_RDCLI12 0x000c +#define regDAGB0_RDCLI12_BASE_IDX 1 +#define regDAGB0_RDCLI13 0x000d +#define regDAGB0_RDCLI13_BASE_IDX 1 +#define regDAGB0_RDCLI14 0x000e +#define regDAGB0_RDCLI14_BASE_IDX 1 +#define regDAGB0_RDCLI15 0x000f +#define regDAGB0_RDCLI15_BASE_IDX 1 +#define regDAGB0_RDCLI16 0x0010 +#define regDAGB0_RDCLI16_BASE_IDX 1 +#define regDAGB0_RDCLI17 0x0011 +#define regDAGB0_RDCLI17_BASE_IDX 1 +#define regDAGB0_RDCLI18 0x0012 +#define regDAGB0_RDCLI18_BASE_IDX 1 +#define regDAGB0_RDCLI19 0x0013 +#define regDAGB0_RDCLI19_BASE_IDX 1 +#define regDAGB0_RDCLI20 0x0014 +#define regDAGB0_RDCLI20_BASE_IDX 1 +#define regDAGB0_RDCLI21 0x0015 +#define regDAGB0_RDCLI21_BASE_IDX 1 +#define regDAGB0_RDCLI22 0x0016 +#define regDAGB0_RDCLI22_BASE_IDX 1 +#define regDAGB0_RDCLI23 0x0017 +#define regDAGB0_RDCLI23_BASE_IDX 1 +#define regDAGB0_RD_CNTL 0x001a +#define regDAGB0_RD_CNTL_BASE_IDX 1 +#define regDAGB0_RD_ADDR_DAGB 0x001b +#define regDAGB0_RD_ADDR_DAGB_BASE_IDX 1 +#define regDAGB0_RD_CGTT_CLK_CTRL 0x001c +#define regDAGB0_RD_CGTT_CLK_CTRL_BASE_IDX 1 +#define regDAGB0_L1TLB_RD_CGTT_CLK_CTRL 0x001d +#define regDAGB0_L1TLB_RD_CGTT_CLK_CTRL_BASE_IDX 1 +#define regDAGB0_RD_ADDR_DAGB_MAX_BURST0 0x001e +#define regDAGB0_RD_ADDR_DAGB_MAX_BURST0_BASE_IDX 1 +#define regDAGB0_RD_ADDR_DAGB_LAZY_TIMER0 0x001f +#define regDAGB0_RD_ADDR_DAGB_LAZY_TIMER0_BASE_IDX 1 +#define regDAGB0_RD_ADDR_DAGB_MAX_BURST1 0x0020 +#define regDAGB0_RD_ADDR_DAGB_MAX_BURST1_BASE_IDX 1 +#define regDAGB0_RD_ADDR_DAGB_LAZY_TIMER1 0x0021 +#define regDAGB0_RD_ADDR_DAGB_LAZY_TIMER1_BASE_IDX 1 +#define regDAGB0_RD_ADDR_DAGB_MAX_BURST2 0x0022 +#define regDAGB0_RD_ADDR_DAGB_MAX_BURST2_BASE_IDX 1 +#define regDAGB0_RD_ADDR_DAGB_LAZY_TIMER2 0x0023 +#define regDAGB0_RD_ADDR_DAGB_LAZY_TIMER2_BASE_IDX 1 +#define regDAGB0_RD_CNTL_MISC 0x0024 +#define regDAGB0_RD_CNTL_MISC_BASE_IDX 1 +#define regDAGB0_RD_TLB_CREDIT 0x0026 +#define regDAGB0_RD_TLB_CREDIT_BASE_IDX 1 +#define regDAGB0_RDCLI_ASK_PENDING 0x0027 +#define regDAGB0_RDCLI_ASK_PENDING_BASE_IDX 1 +#define regDAGB0_RDCLI_GO_PENDING 0x0028 +#define regDAGB0_RDCLI_GO_PENDING_BASE_IDX 1 +#define regDAGB0_RDCLI_GBLSEND_PENDING 0x0029 +#define regDAGB0_RDCLI_GBLSEND_PENDING_BASE_IDX 1 +#define regDAGB0_RDCLI_TLB_PENDING 0x002a +#define regDAGB0_RDCLI_TLB_PENDING_BASE_IDX 1 +#define regDAGB0_RDCLI_OARB_PENDING 0x002b +#define regDAGB0_RDCLI_OARB_PENDING_BASE_IDX 1 +#define regDAGB0_RDCLI_ASK2DF_PENDING 0x002c +#define regDAGB0_RDCLI_ASK2DF_PENDING_BASE_IDX 1 +#define regDAGB0_RDCLI_OSD_PENDING 0x002d +#define regDAGB0_RDCLI_OSD_PENDING_BASE_IDX 1 +#define regDAGB0_RDCLI_ASK_OSD_PENDING 0x002e +#define regDAGB0_RDCLI_ASK_OSD_PENDING_BASE_IDX 1 +#define regDAGB0_WRCLI0 0x002f +#define regDAGB0_WRCLI0_BASE_IDX 1 +#define regDAGB0_WRCLI1 0x0030 +#define regDAGB0_WRCLI1_BASE_IDX 1 +#define regDAGB0_WRCLI2 0x0031 +#define regDAGB0_WRCLI2_BASE_IDX 1 +#define regDAGB0_WRCLI3 0x0032 +#define regDAGB0_WRCLI3_BASE_IDX 1 +#define regDAGB0_WRCLI4 0x0033 +#define regDAGB0_WRCLI4_BASE_IDX 1 +#define regDAGB0_WRCLI5 0x0034 +#define regDAGB0_WRCLI5_BASE_IDX 1 +#define regDAGB0_WRCLI6 0x0035 +#define regDAGB0_WRCLI6_BASE_IDX 1 +#define regDAGB0_WRCLI7 0x0036 +#define regDAGB0_WRCLI7_BASE_IDX 1 +#define regDAGB0_WRCLI8 0x0037 +#define regDAGB0_WRCLI8_BASE_IDX 1 +#define regDAGB0_WRCLI9 0x0038 +#define regDAGB0_WRCLI9_BASE_IDX 1 +#define regDAGB0_WRCLI10 0x0039 +#define regDAGB0_WRCLI10_BASE_IDX 1 +#define regDAGB0_WRCLI11 0x003a +#define regDAGB0_WRCLI11_BASE_IDX 1 +#define regDAGB0_WRCLI12 0x003b +#define regDAGB0_WRCLI12_BASE_IDX 1 +#define regDAGB0_WRCLI13 0x003c +#define regDAGB0_WRCLI13_BASE_IDX 1 +#define regDAGB0_WRCLI14 0x003d +#define regDAGB0_WRCLI14_BASE_IDX 1 +#define regDAGB0_WRCLI15 0x003e +#define regDAGB0_WRCLI15_BASE_IDX 1 +#define regDAGB0_WRCLI16 0x003f +#define regDAGB0_WRCLI16_BASE_IDX 1 +#define regDAGB0_WRCLI17 0x0040 +#define regDAGB0_WRCLI17_BASE_IDX 1 +#define regDAGB0_WRCLI18 0x0041 +#define regDAGB0_WRCLI18_BASE_IDX 1 +#define regDAGB0_WRCLI19 0x0042 +#define regDAGB0_WRCLI19_BASE_IDX 1 +#define regDAGB0_WRCLI20 0x0043 +#define regDAGB0_WRCLI20_BASE_IDX 1 +#define regDAGB0_WRCLI21 0x0044 +#define regDAGB0_WRCLI21_BASE_IDX 1 +#define regDAGB0_WRCLI22 0x0045 +#define regDAGB0_WRCLI22_BASE_IDX 1 +#define regDAGB0_WRCLI23 0x0046 +#define regDAGB0_WRCLI23_BASE_IDX 1 +#define regDAGB0_WR_CNTL 0x0067 +#define regDAGB0_WR_CNTL_BASE_IDX 1 +#define regDAGB0_WR_ADDR_DAGB 0x0068 +#define regDAGB0_WR_ADDR_DAGB_BASE_IDX 1 +#define regDAGB0_WR_CGTT_CLK_CTRL 0x0069 +#define regDAGB0_WR_CGTT_CLK_CTRL_BASE_IDX 1 +#define regDAGB0_L1TLB_WR_CGTT_CLK_CTRL 0x006a +#define regDAGB0_L1TLB_WR_CGTT_CLK_CTRL_BASE_IDX 1 +#define regDAGB0_WR_ADDR_DAGB_MAX_BURST0 0x006b +#define regDAGB0_WR_ADDR_DAGB_MAX_BURST0_BASE_IDX 1 +#define regDAGB0_WR_ADDR_DAGB_LAZY_TIMER0 0x006c +#define regDAGB0_WR_ADDR_DAGB_LAZY_TIMER0_BASE_IDX 1 +#define regDAGB0_WR_ADDR_DAGB_MAX_BURST1 0x006d +#define regDAGB0_WR_ADDR_DAGB_MAX_BURST1_BASE_IDX 1 +#define regDAGB0_WR_ADDR_DAGB_LAZY_TIMER1 0x006e +#define regDAGB0_WR_ADDR_DAGB_LAZY_TIMER1_BASE_IDX 1 +#define regDAGB0_WR_ADDR_DAGB_MAX_BURST2 0x006f +#define regDAGB0_WR_ADDR_DAGB_MAX_BURST2_BASE_IDX 1 +#define regDAGB0_WR_ADDR_DAGB_LAZY_TIMER2 0x0070 +#define regDAGB0_WR_ADDR_DAGB_LAZY_TIMER2_BASE_IDX 1 +#define regDAGB0_WR_DATA_DAGB 0x0071 +#define regDAGB0_WR_DATA_DAGB_BASE_IDX 1 +#define regDAGB0_WR_DATA_DAGB_MAX_BURST0 0x0072 +#define regDAGB0_WR_DATA_DAGB_MAX_BURST0_BASE_IDX 1 +#define regDAGB0_WR_DATA_DAGB_LAZY_TIMER0 0x0073 +#define regDAGB0_WR_DATA_DAGB_LAZY_TIMER0_BASE_IDX 1 +#define regDAGB0_WR_DATA_DAGB_MAX_BURST1 0x0074 +#define regDAGB0_WR_DATA_DAGB_MAX_BURST1_BASE_IDX 1 +#define regDAGB0_WR_DATA_DAGB_LAZY_TIMER1 0x0075 +#define regDAGB0_WR_DATA_DAGB_LAZY_TIMER1_BASE_IDX 1 +#define regDAGB0_WR_DATA_DAGB_MAX_BURST2 0x0076 +#define regDAGB0_WR_DATA_DAGB_MAX_BURST2_BASE_IDX 1 +#define regDAGB0_WR_DATA_DAGB_LAZY_TIMER2 0x0077 +#define regDAGB0_WR_DATA_DAGB_LAZY_TIMER2_BASE_IDX 1 +#define regDAGB0_WR_CNTL_MISC 0x0078 +#define regDAGB0_WR_CNTL_MISC_BASE_IDX 1 +#define regDAGB0_WR_TLB_CREDIT 0x007a +#define regDAGB0_WR_TLB_CREDIT_BASE_IDX 1 +#define regDAGB0_WR_DATA_FIFO_CREDIT_CNTL1 0x007b +#define regDAGB0_WR_DATA_FIFO_CREDIT_CNTL1_BASE_IDX 1 +#define regDAGB0_WR_ATOMIC_FIFO_CREDIT_CNTL1 0x007c +#define regDAGB0_WR_ATOMIC_FIFO_CREDIT_CNTL1_BASE_IDX 1 +#define regDAGB0_WRCLI_ASK_PENDING 0x007d +#define regDAGB0_WRCLI_ASK_PENDING_BASE_IDX 1 +#define regDAGB0_WRCLI_GO_PENDING 0x007e +#define regDAGB0_WRCLI_GO_PENDING_BASE_IDX 1 +#define regDAGB0_WRCLI_GBLSEND_PENDING 0x007f +#define regDAGB0_WRCLI_GBLSEND_PENDING_BASE_IDX 1 +#define regDAGB0_WRCLI_TLB_PENDING 0x0080 +#define regDAGB0_WRCLI_TLB_PENDING_BASE_IDX 1 +#define regDAGB0_WRCLI_OARB_PENDING 0x0081 +#define regDAGB0_WRCLI_OARB_PENDING_BASE_IDX 1 +#define regDAGB0_WRCLI_ASK2DF_PENDING 0x0082 +#define regDAGB0_WRCLI_ASK2DF_PENDING_BASE_IDX 1 +#define regDAGB0_WRCLI_OSD_PENDING 0x0083 +#define regDAGB0_WRCLI_OSD_PENDING_BASE_IDX 1 +#define regDAGB0_WRCLI_ASK_OSD_PENDING 0x0084 +#define regDAGB0_WRCLI_ASK_OSD_PENDING_BASE_IDX 1 +#define regDAGB0_WRCLI_DBUS_ASK_PENDING 0x0085 +#define regDAGB0_WRCLI_DBUS_ASK_PENDING_BASE_IDX 1 +#define regDAGB0_WRCLI_DBUS_GO_PENDING 0x0086 +#define regDAGB0_WRCLI_DBUS_GO_PENDING_BASE_IDX 1 +#define regDAGB0_SDP_ERR_STATUS 0x0089 +#define regDAGB0_SDP_ERR_STATUS_BASE_IDX 1 +#define regDAGB0_DAGB_DLY 0x008b +#define regDAGB0_DAGB_DLY_BASE_IDX 1 +#define regDAGB0_CNTL_MISC 0x008c +#define regDAGB0_CNTL_MISC_BASE_IDX 1 +#define regDAGB0_CNTL_MISC2 0x008d +#define regDAGB0_CNTL_MISC2_BASE_IDX 1 +#define regDAGB0_FIFO_EMPTY 0x008e +#define regDAGB0_FIFO_EMPTY_BASE_IDX 1 +#define regDAGB0_FIFO_FULL 0x008f +#define regDAGB0_FIFO_FULL_BASE_IDX 1 +#define regDAGB0_RD_CREDITS_FULL 0x0090 +#define regDAGB0_RD_CREDITS_FULL_BASE_IDX 1 +#define regDAGB0_WR_CREDITS_FULL 0x0091 +#define regDAGB0_WR_CREDITS_FULL_BASE_IDX 1 +#define regDAGB0_PERFCOUNTER_LO 0x0092 +#define regDAGB0_PERFCOUNTER_LO_BASE_IDX 1 +#define regDAGB0_PERFCOUNTER_HI 0x0093 +#define regDAGB0_PERFCOUNTER_HI_BASE_IDX 1 +#define regDAGB0_PERFCOUNTER0_CFG 0x0094 +#define regDAGB0_PERFCOUNTER0_CFG_BASE_IDX 1 +#define regDAGB0_PERFCOUNTER1_CFG 0x0095 +#define regDAGB0_PERFCOUNTER1_CFG_BASE_IDX 1 +#define regDAGB0_PERFCOUNTER2_CFG 0x0096 +#define regDAGB0_PERFCOUNTER2_CFG_BASE_IDX 1 +#define regDAGB0_PERFCOUNTER_RSLT_CNTL 0x009b +#define regDAGB0_PERFCOUNTER_RSLT_CNTL_BASE_IDX 1 +#define regDAGB0_L1TLB_REG_RW 0x009c +#define regDAGB0_L1TLB_REG_RW_BASE_IDX 1 +#define regDAGB0_RESERVE0 0x009d +#define regDAGB0_RESERVE0_BASE_IDX 1 +#define regDAGB0_RESERVE1 0x009e +#define regDAGB0_RESERVE1_BASE_IDX 1 +#define regDAGB0_RESERVE2 0x009f +#define regDAGB0_RESERVE2_BASE_IDX 1 +#define regDAGB0_RESERVE3 0x00a0 +#define regDAGB0_RESERVE3_BASE_IDX 1 +#define regDAGB0_SDP_RD_BW_CNTL 0x00a1 +#define regDAGB0_SDP_RD_BW_CNTL_BASE_IDX 1 +#define regDAGB0_SDP_RD_PRIORITY 0x00a5 +#define regDAGB0_SDP_RD_PRIORITY_BASE_IDX 1 +#define regDAGB0_SDP_WR_PRIORITY 0x00a6 +#define regDAGB0_SDP_WR_PRIORITY_BASE_IDX 1 +#define regDAGB0_SDP_RD_CLI2SDP_VC_MAP 0x00a7 +#define regDAGB0_SDP_RD_CLI2SDP_VC_MAP_BASE_IDX 1 +#define regDAGB0_SDP_WR_CLI2SDP_VC_MAP 0x00a8 +#define regDAGB0_SDP_WR_CLI2SDP_VC_MAP_BASE_IDX 1 +#define regDAGB0_SDP_ENABLE 0x00a9 +#define regDAGB0_SDP_ENABLE_BASE_IDX 1 +#define regDAGB0_SDP_CREDITS 0x00aa +#define regDAGB0_SDP_CREDITS_BASE_IDX 1 +#define regDAGB0_SDP_TAG_RESERVE0 0x00ab +#define regDAGB0_SDP_TAG_RESERVE0_BASE_IDX 1 +#define regDAGB0_SDP_TAG_RESERVE1 0x00ac +#define regDAGB0_SDP_TAG_RESERVE1_BASE_IDX 1 +#define regDAGB0_SDP_VCC_RESERVE0 0x00c8 +#define regDAGB0_SDP_VCC_RESERVE0_BASE_IDX 1 +#define regDAGB0_SDP_VCC_RESERVE1 0x00c9 +#define regDAGB0_SDP_VCC_RESERVE1_BASE_IDX 1 +#define regDAGB0_SDP_REQ_CNTL 0x00ca +#define regDAGB0_SDP_REQ_CNTL_BASE_IDX 1 +#define regDAGB0_SDP_MISC_AON 0x00cb +#define regDAGB0_SDP_MISC_AON_BASE_IDX 1 +#define regDAGB0_SDP_MISC 0x00cc +#define regDAGB0_SDP_MISC_BASE_IDX 1 +#define regDAGB0_SDP_MISC2 0x00cd +#define regDAGB0_SDP_MISC2_BASE_IDX 1 +#define regDAGB0_SDP_VCD_RESERVE0 0x00ce +#define regDAGB0_SDP_VCD_RESERVE0_BASE_IDX 1 +#define regDAGB0_SDP_VCD_RESERVE1 0x00cf +#define regDAGB0_SDP_VCD_RESERVE1_BASE_IDX 1 +#define regDAGB0_SDP_ARB_CNTL0 0x00d0 +#define regDAGB0_SDP_ARB_CNTL0_BASE_IDX 1 +#define regDAGB0_SDP_ARB_CNTL1 0x00d1 +#define regDAGB0_SDP_ARB_CNTL1_BASE_IDX 1 +#define regDAGB0_FATAL_ERROR_CLEAR 0x00d2 +#define regDAGB0_FATAL_ERROR_CLEAR_BASE_IDX 1 +#define regDAGB0_FATAL_ERROR_STATUS0 0x00d3 +#define regDAGB0_FATAL_ERROR_STATUS0_BASE_IDX 1 +#define regDAGB0_FATAL_ERROR_STATUS1 0x00d4 +#define regDAGB0_FATAL_ERROR_STATUS1_BASE_IDX 1 +#define regDAGB0_FATAL_ERROR_STATUS2 0x00d5 +#define regDAGB0_FATAL_ERROR_STATUS2_BASE_IDX 1 +#define regDAGB0_FATAL_ERROR_STATUS3 0x00d6 +#define regDAGB0_FATAL_ERROR_STATUS3_BASE_IDX 1 +#define regDAGB0_FATAL_ERROR_STATUS4 0x00d7 +#define regDAGB0_FATAL_ERROR_STATUS4_BASE_IDX 1 +#define regDAGB0_SDP_CGTT_CLK_CTRL 0x00d8 +#define regDAGB0_SDP_CGTT_CLK_CTRL_BASE_IDX 1 +#define regDAGB0_SDP_LATENCY_SAMPLING 0x00d9 +#define regDAGB0_SDP_LATENCY_SAMPLING_BASE_IDX 1 +#define regDAGB0_WRCLI_GPU_SNOOP_OVERRIDE 0x00ee +#define regDAGB0_WRCLI_GPU_SNOOP_OVERRIDE_BASE_IDX 1 +#define regDAGB0_WRCLI_GPU_SNOOP_OVERRIDE_VALUE 0x00ef +#define regDAGB0_WRCLI_GPU_SNOOP_OVERRIDE_VALUE_BASE_IDX 1 +#define regDAGB1_RDCLI0 0x0200 +#define regDAGB1_RDCLI0_BASE_IDX 1 +#define regDAGB1_RDCLI1 0x0201 +#define regDAGB1_RDCLI1_BASE_IDX 1 +#define regDAGB1_RDCLI2 0x0202 +#define regDAGB1_RDCLI2_BASE_IDX 1 +#define regDAGB1_RDCLI3 0x0203 +#define regDAGB1_RDCLI3_BASE_IDX 1 +#define regDAGB1_RDCLI4 0x0204 +#define regDAGB1_RDCLI4_BASE_IDX 1 +#define regDAGB1_RDCLI5 0x0205 +#define regDAGB1_RDCLI5_BASE_IDX 1 +#define regDAGB1_RDCLI6 0x0206 +#define regDAGB1_RDCLI6_BASE_IDX 1 +#define regDAGB1_RDCLI7 0x0207 +#define regDAGB1_RDCLI7_BASE_IDX 1 +#define regDAGB1_RDCLI8 0x0208 +#define regDAGB1_RDCLI8_BASE_IDX 1 +#define regDAGB1_RDCLI9 0x0209 +#define regDAGB1_RDCLI9_BASE_IDX 1 +#define regDAGB1_RDCLI10 0x020a +#define regDAGB1_RDCLI10_BASE_IDX 1 +#define regDAGB1_RDCLI11 0x020b +#define regDAGB1_RDCLI11_BASE_IDX 1 +#define regDAGB1_RDCLI12 0x020c +#define regDAGB1_RDCLI12_BASE_IDX 1 +#define regDAGB1_RDCLI13 0x020d +#define regDAGB1_RDCLI13_BASE_IDX 1 +#define regDAGB1_RDCLI14 0x020e +#define regDAGB1_RDCLI14_BASE_IDX 1 +#define regDAGB1_RDCLI15 0x020f +#define regDAGB1_RDCLI15_BASE_IDX 1 +#define regDAGB1_RDCLI16 0x0210 +#define regDAGB1_RDCLI16_BASE_IDX 1 +#define regDAGB1_RDCLI17 0x0211 +#define regDAGB1_RDCLI17_BASE_IDX 1 +#define regDAGB1_RDCLI18 0x0212 +#define regDAGB1_RDCLI18_BASE_IDX 1 +#define regDAGB1_RDCLI19 0x0213 +#define regDAGB1_RDCLI19_BASE_IDX 1 +#define regDAGB1_RDCLI20 0x0214 +#define regDAGB1_RDCLI20_BASE_IDX 1 +#define regDAGB1_RDCLI21 0x0215 +#define regDAGB1_RDCLI21_BASE_IDX 1 +#define regDAGB1_RDCLI22 0x0216 +#define regDAGB1_RDCLI22_BASE_IDX 1 +#define regDAGB1_RDCLI23 0x0217 +#define regDAGB1_RDCLI23_BASE_IDX 1 +#define regDAGB1_RD_CNTL 0x021a +#define regDAGB1_RD_CNTL_BASE_IDX 1 +#define regDAGB1_RD_ADDR_DAGB 0x021b +#define regDAGB1_RD_ADDR_DAGB_BASE_IDX 1 +#define regDAGB1_RD_CGTT_CLK_CTRL 0x021c +#define regDAGB1_RD_CGTT_CLK_CTRL_BASE_IDX 1 +#define regDAGB1_L1TLB_RD_CGTT_CLK_CTRL 0x021d +#define regDAGB1_L1TLB_RD_CGTT_CLK_CTRL_BASE_IDX 1 +#define regDAGB1_RD_ADDR_DAGB_MAX_BURST0 0x021e +#define regDAGB1_RD_ADDR_DAGB_MAX_BURST0_BASE_IDX 1 +#define regDAGB1_RD_ADDR_DAGB_LAZY_TIMER0 0x021f +#define regDAGB1_RD_ADDR_DAGB_LAZY_TIMER0_BASE_IDX 1 +#define regDAGB1_RD_ADDR_DAGB_MAX_BURST1 0x0220 +#define regDAGB1_RD_ADDR_DAGB_MAX_BURST1_BASE_IDX 1 +#define regDAGB1_RD_ADDR_DAGB_LAZY_TIMER1 0x0221 +#define regDAGB1_RD_ADDR_DAGB_LAZY_TIMER1_BASE_IDX 1 +#define regDAGB1_RD_ADDR_DAGB_MAX_BURST2 0x0222 +#define regDAGB1_RD_ADDR_DAGB_MAX_BURST2_BASE_IDX 1 +#define regDAGB1_RD_ADDR_DAGB_LAZY_TIMER2 0x0223 +#define regDAGB1_RD_ADDR_DAGB_LAZY_TIMER2_BASE_IDX 1 +#define regDAGB1_RD_CNTL_MISC 0x0224 +#define regDAGB1_RD_CNTL_MISC_BASE_IDX 1 +#define regDAGB1_RD_TLB_CREDIT 0x0226 +#define regDAGB1_RD_TLB_CREDIT_BASE_IDX 1 +#define regDAGB1_RDCLI_ASK_PENDING 0x0227 +#define regDAGB1_RDCLI_ASK_PENDING_BASE_IDX 1 +#define regDAGB1_RDCLI_GO_PENDING 0x0228 +#define regDAGB1_RDCLI_GO_PENDING_BASE_IDX 1 +#define regDAGB1_RDCLI_GBLSEND_PENDING 0x0229 +#define regDAGB1_RDCLI_GBLSEND_PENDING_BASE_IDX 1 +#define regDAGB1_RDCLI_TLB_PENDING 0x022a +#define regDAGB1_RDCLI_TLB_PENDING_BASE_IDX 1 +#define regDAGB1_RDCLI_OARB_PENDING 0x022b +#define regDAGB1_RDCLI_OARB_PENDING_BASE_IDX 1 +#define regDAGB1_RDCLI_ASK2DF_PENDING 0x022c +#define regDAGB1_RDCLI_ASK2DF_PENDING_BASE_IDX 1 +#define regDAGB1_RDCLI_OSD_PENDING 0x022d +#define regDAGB1_RDCLI_OSD_PENDING_BASE_IDX 1 +#define regDAGB1_RDCLI_ASK_OSD_PENDING 0x022e +#define regDAGB1_RDCLI_ASK_OSD_PENDING_BASE_IDX 1 +#define regDAGB1_WRCLI0 0x022f +#define regDAGB1_WRCLI0_BASE_IDX 1 +#define regDAGB1_WRCLI1 0x0230 +#define regDAGB1_WRCLI1_BASE_IDX 1 +#define regDAGB1_WRCLI2 0x0231 +#define regDAGB1_WRCLI2_BASE_IDX 1 +#define regDAGB1_WRCLI3 0x0232 +#define regDAGB1_WRCLI3_BASE_IDX 1 +#define regDAGB1_WRCLI4 0x0233 +#define regDAGB1_WRCLI4_BASE_IDX 1 +#define regDAGB1_WRCLI5 0x0234 +#define regDAGB1_WRCLI5_BASE_IDX 1 +#define regDAGB1_WRCLI6 0x0235 +#define regDAGB1_WRCLI6_BASE_IDX 1 +#define regDAGB1_WRCLI7 0x0236 +#define regDAGB1_WRCLI7_BASE_IDX 1 +#define regDAGB1_WRCLI8 0x0237 +#define regDAGB1_WRCLI8_BASE_IDX 1 +#define regDAGB1_WRCLI9 0x0238 +#define regDAGB1_WRCLI9_BASE_IDX 1 +#define regDAGB1_WRCLI10 0x0239 +#define regDAGB1_WRCLI10_BASE_IDX 1 +#define regDAGB1_WRCLI11 0x023a +#define regDAGB1_WRCLI11_BASE_IDX 1 +#define regDAGB1_WRCLI12 0x023b +#define regDAGB1_WRCLI12_BASE_IDX 1 +#define regDAGB1_WRCLI13 0x023c +#define regDAGB1_WRCLI13_BASE_IDX 1 +#define regDAGB1_WRCLI14 0x023d +#define regDAGB1_WRCLI14_BASE_IDX 1 +#define regDAGB1_WRCLI15 0x023e +#define regDAGB1_WRCLI15_BASE_IDX 1 +#define regDAGB1_WR_CNTL 0x0267 +#define regDAGB1_WR_CNTL_BASE_IDX 1 +#define regDAGB1_WR_ADDR_DAGB 0x0268 +#define regDAGB1_WR_ADDR_DAGB_BASE_IDX 1 +#define regDAGB1_WR_CGTT_CLK_CTRL 0x0269 +#define regDAGB1_WR_CGTT_CLK_CTRL_BASE_IDX 1 +#define regDAGB1_L1TLB_WR_CGTT_CLK_CTRL 0x026a +#define regDAGB1_L1TLB_WR_CGTT_CLK_CTRL_BASE_IDX 1 +#define regDAGB1_WR_ADDR_DAGB_MAX_BURST0 0x026b +#define regDAGB1_WR_ADDR_DAGB_MAX_BURST0_BASE_IDX 1 +#define regDAGB1_WR_ADDR_DAGB_LAZY_TIMER0 0x026c +#define regDAGB1_WR_ADDR_DAGB_LAZY_TIMER0_BASE_IDX 1 +#define regDAGB1_WR_ADDR_DAGB_MAX_BURST1 0x026d +#define regDAGB1_WR_ADDR_DAGB_MAX_BURST1_BASE_IDX 1 +#define regDAGB1_WR_ADDR_DAGB_LAZY_TIMER1 0x026e +#define regDAGB1_WR_ADDR_DAGB_LAZY_TIMER1_BASE_IDX 1 +#define regDAGB1_WR_DATA_DAGB 0x0271 +#define regDAGB1_WR_DATA_DAGB_BASE_IDX 1 +#define regDAGB1_WR_DATA_DAGB_MAX_BURST0 0x0272 +#define regDAGB1_WR_DATA_DAGB_MAX_BURST0_BASE_IDX 1 +#define regDAGB1_WR_DATA_DAGB_LAZY_TIMER0 0x0273 +#define regDAGB1_WR_DATA_DAGB_LAZY_TIMER0_BASE_IDX 1 +#define regDAGB1_WR_DATA_DAGB_MAX_BURST1 0x0274 +#define regDAGB1_WR_DATA_DAGB_MAX_BURST1_BASE_IDX 1 +#define regDAGB1_WR_DATA_DAGB_LAZY_TIMER1 0x0275 +#define regDAGB1_WR_DATA_DAGB_LAZY_TIMER1_BASE_IDX 1 +#define regDAGB1_WR_CNTL_MISC 0x0278 +#define regDAGB1_WR_CNTL_MISC_BASE_IDX 1 +#define regDAGB1_WR_TLB_CREDIT 0x027a +#define regDAGB1_WR_TLB_CREDIT_BASE_IDX 1 +#define regDAGB1_WR_ATOMIC_FIFO_CREDIT_CNTL1 0x027c +#define regDAGB1_WR_ATOMIC_FIFO_CREDIT_CNTL1_BASE_IDX 1 +#define regDAGB1_WRCLI_ASK_PENDING 0x027d +#define regDAGB1_WRCLI_ASK_PENDING_BASE_IDX 1 +#define regDAGB1_WRCLI_GO_PENDING 0x027e +#define regDAGB1_WRCLI_GO_PENDING_BASE_IDX 1 +#define regDAGB1_WRCLI_GBLSEND_PENDING 0x027f +#define regDAGB1_WRCLI_GBLSEND_PENDING_BASE_IDX 1 +#define regDAGB1_WRCLI_TLB_PENDING 0x0280 +#define regDAGB1_WRCLI_TLB_PENDING_BASE_IDX 1 +#define regDAGB1_WRCLI_OARB_PENDING 0x0281 +#define regDAGB1_WRCLI_OARB_PENDING_BASE_IDX 1 +#define regDAGB1_WRCLI_OSD_PENDING 0x0283 +#define regDAGB1_WRCLI_OSD_PENDING_BASE_IDX 1 +#define regDAGB1_WRCLI_DBUS_ASK_PENDING 0x0285 +#define regDAGB1_WRCLI_DBUS_ASK_PENDING_BASE_IDX 1 +#define regDAGB1_WRCLI_DBUS_GO_PENDING 0x0286 +#define regDAGB1_WRCLI_DBUS_GO_PENDING_BASE_IDX 1 +#define regDAGB1_SDP_ERR_STATUS 0x0289 +#define regDAGB1_SDP_ERR_STATUS_BASE_IDX 1 +#define regDAGB1_DAGB_DLY 0x028b +#define regDAGB1_DAGB_DLY_BASE_IDX 1 +#define regDAGB1_CNTL_MISC 0x028c +#define regDAGB1_CNTL_MISC_BASE_IDX 1 +#define regDAGB1_CNTL_MISC2 0x028d +#define regDAGB1_CNTL_MISC2_BASE_IDX 1 +#define regDAGB1_FIFO_EMPTY 0x028e +#define regDAGB1_FIFO_EMPTY_BASE_IDX 1 +#define regDAGB1_FIFO_FULL 0x028f +#define regDAGB1_FIFO_FULL_BASE_IDX 1 +#define regDAGB1_RD_CREDITS_FULL 0x0290 +#define regDAGB1_RD_CREDITS_FULL_BASE_IDX 1 +#define regDAGB1_WR_CREDITS_FULL 0x0291 +#define regDAGB1_WR_CREDITS_FULL_BASE_IDX 1 +#define regDAGB1_PERFCOUNTER_LO 0x0292 +#define regDAGB1_PERFCOUNTER_LO_BASE_IDX 1 +#define regDAGB1_PERFCOUNTER_HI 0x0293 +#define regDAGB1_PERFCOUNTER_HI_BASE_IDX 1 +#define regDAGB1_PERFCOUNTER0_CFG 0x0294 +#define regDAGB1_PERFCOUNTER0_CFG_BASE_IDX 1 +#define regDAGB1_PERFCOUNTER1_CFG 0x0295 +#define regDAGB1_PERFCOUNTER1_CFG_BASE_IDX 1 +#define regDAGB1_PERFCOUNTER2_CFG 0x0296 +#define regDAGB1_PERFCOUNTER2_CFG_BASE_IDX 1 +#define regDAGB1_PERFCOUNTER_RSLT_CNTL 0x029b +#define regDAGB1_PERFCOUNTER_RSLT_CNTL_BASE_IDX 1 +#define regDAGB1_L1TLB_REG_RW 0x029c +#define regDAGB1_L1TLB_REG_RW_BASE_IDX 1 +#define regDAGB1_RESERVE0 0x029d +#define regDAGB1_RESERVE0_BASE_IDX 1 +#define regDAGB1_RESERVE1 0x029e +#define regDAGB1_RESERVE1_BASE_IDX 1 +#define regDAGB1_RESERVE2 0x029f +#define regDAGB1_RESERVE2_BASE_IDX 1 +#define regDAGB1_RESERVE3 0x02a0 +#define regDAGB1_RESERVE3_BASE_IDX 1 +#define regDAGB1_SDP_RD_BW_CNTL 0x02a1 +#define regDAGB1_SDP_RD_BW_CNTL_BASE_IDX 1 +#define regDAGB1_SDP_RD_PRIORITY 0x02a5 +#define regDAGB1_SDP_RD_PRIORITY_BASE_IDX 1 +#define regDAGB1_SDP_RD_CLI2SDP_VC_MAP 0x02a7 +#define regDAGB1_SDP_RD_CLI2SDP_VC_MAP_BASE_IDX 1 +#define regDAGB1_SDP_ENABLE 0x02a9 +#define regDAGB1_SDP_ENABLE_BASE_IDX 1 +#define regDAGB1_SDP_CREDITS 0x02aa +#define regDAGB1_SDP_CREDITS_BASE_IDX 1 +#define regDAGB1_SDP_TAG_RESERVE0 0x02ab +#define regDAGB1_SDP_TAG_RESERVE0_BASE_IDX 1 +#define regDAGB1_SDP_TAG_RESERVE1 0x02ac +#define regDAGB1_SDP_TAG_RESERVE1_BASE_IDX 1 +#define regDAGB1_SDP_VCC_RESERVE0 0x02c8 +#define regDAGB1_SDP_VCC_RESERVE0_BASE_IDX 1 +#define regDAGB1_SDP_VCC_RESERVE1 0x02c9 +#define regDAGB1_SDP_VCC_RESERVE1_BASE_IDX 1 +#define regDAGB1_SDP_REQ_CNTL 0x02ca +#define regDAGB1_SDP_REQ_CNTL_BASE_IDX 1 +#define regDAGB1_SDP_MISC_AON 0x02cb +#define regDAGB1_SDP_MISC_AON_BASE_IDX 1 +#define regDAGB1_SDP_MISC 0x02cc +#define regDAGB1_SDP_MISC_BASE_IDX 1 +#define regDAGB1_SDP_MISC2 0x02cd +#define regDAGB1_SDP_MISC2_BASE_IDX 1 +#define regDAGB1_SDP_ARB_CNTL0 0x02d0 +#define regDAGB1_SDP_ARB_CNTL0_BASE_IDX 1 +#define regDAGB1_SDP_ARB_CNTL1 0x02d1 +#define regDAGB1_SDP_ARB_CNTL1_BASE_IDX 1 +#define regDAGB1_FATAL_ERROR_CLEAR 0x02d2 +#define regDAGB1_FATAL_ERROR_CLEAR_BASE_IDX 1 +#define regDAGB1_FATAL_ERROR_STATUS0 0x02d3 +#define regDAGB1_FATAL_ERROR_STATUS0_BASE_IDX 1 +#define regDAGB1_FATAL_ERROR_STATUS1 0x02d4 +#define regDAGB1_FATAL_ERROR_STATUS1_BASE_IDX 1 +#define regDAGB1_FATAL_ERROR_STATUS2 0x02d5 +#define regDAGB1_FATAL_ERROR_STATUS2_BASE_IDX 1 +#define regDAGB1_FATAL_ERROR_STATUS3 0x02d6 +#define regDAGB1_FATAL_ERROR_STATUS3_BASE_IDX 1 +#define regDAGB1_SDP_CGTT_CLK_CTRL 0x02d8 +#define regDAGB1_SDP_CGTT_CLK_CTRL_BASE_IDX 1 +#define regDAGB1_SDP_LATENCY_SAMPLING 0x02d9 +#define regDAGB1_SDP_LATENCY_SAMPLING_BASE_IDX 1 +#define regDAGB1_WRCLI_GPU_SNOOP_OVERRIDE 0x02ee +#define regDAGB1_WRCLI_GPU_SNOOP_OVERRIDE_BASE_IDX 1 +#define regDAGB1_WRCLI_GPU_SNOOP_OVERRIDE_VALUE 0x02ef +#define regDAGB1_WRCLI_GPU_SNOOP_OVERRIDE_VALUE_BASE_IDX 1 + + +// addressBlock: mmhub_pctldec +// base address: 0x69000 +#define regPCTL_CTRL 0x0400 +#define regPCTL_CTRL_BASE_IDX 1 +#define regPCTL_MMHUB_DEEPSLEEP_IB 0x0401 +#define regPCTL_MMHUB_DEEPSLEEP_IB_BASE_IDX 1 +#define regPCTL_MMHUB_DEEPSLEEP_OVERRIDE 0x0402 +#define regPCTL_MMHUB_DEEPSLEEP_OVERRIDE_BASE_IDX 1 +#define regPCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB 0x0403 +#define regPCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB_BASE_IDX 1 +#define regPCTL_PG_IGNORE_DEEPSLEEP 0x0404 +#define regPCTL_PG_IGNORE_DEEPSLEEP_BASE_IDX 1 +#define regPCTL_PG_IGNORE_DEEPSLEEP_IB 0x0405 +#define regPCTL_PG_IGNORE_DEEPSLEEP_IB_BASE_IDX 1 +#define regPCTL_UTCL2_MISC 0x0406 +#define regPCTL_UTCL2_MISC_BASE_IDX 1 +#define regPCTL_SLICE0_CFG_DAGB_WRBUSY 0x0407 +#define regPCTL_SLICE0_CFG_DAGB_WRBUSY_BASE_IDX 1 +#define regPCTL_SLICE0_CFG_DAGB_RDBUSY 0x0408 +#define regPCTL_SLICE0_CFG_DAGB_RDBUSY_BASE_IDX 1 +#define regPCTL_SLICE0_CFG_DS_ALLOW 0x0409 +#define regPCTL_SLICE0_CFG_DS_ALLOW_BASE_IDX 1 +#define regPCTL_SLICE0_CFG_DS_ALLOW_IB 0x040a +#define regPCTL_SLICE0_CFG_DS_ALLOW_IB_BASE_IDX 1 +#define regPCTL_SLICE0_MISC 0x040b +#define regPCTL_SLICE0_MISC_BASE_IDX 1 +#define regPCTL_SLICE1_CFG_DAGB_WRBUSY 0x040c +#define regPCTL_SLICE1_CFG_DAGB_WRBUSY_BASE_IDX 1 +#define regPCTL_SLICE1_CFG_DAGB_RDBUSY 0x040d +#define regPCTL_SLICE1_CFG_DAGB_RDBUSY_BASE_IDX 1 +#define regPCTL_SLICE1_CFG_DS_ALLOW 0x040e +#define regPCTL_SLICE1_CFG_DS_ALLOW_BASE_IDX 1 +#define regPCTL_SLICE1_CFG_DS_ALLOW_IB 0x040f +#define regPCTL_SLICE1_CFG_DS_ALLOW_IB_BASE_IDX 1 +#define regPCTL_SLICE1_MISC 0x0410 +#define regPCTL_SLICE1_MISC_BASE_IDX 1 +#define regPCTL_RENG_CTRL 0x0411 +#define regPCTL_RENG_CTRL_BASE_IDX 1 +#define regPCTL_UTCL2_RENG_EXECUTE 0x0412 +#define regPCTL_UTCL2_RENG_EXECUTE_BASE_IDX 1 +#define regPCTL_UTCL2_RENG_RAM_INDEX 0x0413 +#define regPCTL_UTCL2_RENG_RAM_INDEX_BASE_IDX 1 +#define regPCTL_UTCL2_RENG_RAM_DATA 0x0414 +#define regPCTL_UTCL2_RENG_RAM_DATA_BASE_IDX 1 +#define regPCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE0 0x0415 +#define regPCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE0_BASE_IDX 1 +#define regPCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE1 0x0416 +#define regPCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE1_BASE_IDX 1 +#define regPCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE2 0x0417 +#define regPCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE2_BASE_IDX 1 +#define regPCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE3 0x0418 +#define regPCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE3_BASE_IDX 1 +#define regPCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE4 0x0419 +#define regPCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE4_BASE_IDX 1 +#define regPCTL_UTCL2_STCTRL_REGISTER_SAVE_EXCL_SET0 0x041a +#define regPCTL_UTCL2_STCTRL_REGISTER_SAVE_EXCL_SET0_BASE_IDX 1 +#define regPCTL_UTCL2_STCTRL_REGISTER_SAVE_EXCL_SET1 0x041b +#define regPCTL_UTCL2_STCTRL_REGISTER_SAVE_EXCL_SET1_BASE_IDX 1 +#define regPCTL_SLICE0_RENG_EXECUTE 0x041c +#define regPCTL_SLICE0_RENG_EXECUTE_BASE_IDX 1 +#define regPCTL_SLICE0_RENG_RAM_INDEX 0x041d +#define regPCTL_SLICE0_RENG_RAM_INDEX_BASE_IDX 1 +#define regPCTL_SLICE0_RENG_RAM_DATA 0x041e +#define regPCTL_SLICE0_RENG_RAM_DATA_BASE_IDX 1 +#define regPCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE0 0x041f +#define regPCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE0_BASE_IDX 1 +#define regPCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE1 0x0420 +#define regPCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE1_BASE_IDX 1 +#define regPCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE2 0x0421 +#define regPCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE2_BASE_IDX 1 +#define regPCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE3 0x0422 +#define regPCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE3_BASE_IDX 1 +#define regPCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE4 0x0423 +#define regPCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE4_BASE_IDX 1 +#define regPCTL_SLICE0_STCTRL_REGISTER_SAVE_EXCL_SET0 0x0424 +#define regPCTL_SLICE0_STCTRL_REGISTER_SAVE_EXCL_SET0_BASE_IDX 1 +#define regPCTL_SLICE0_STCTRL_REGISTER_SAVE_EXCL_SET1 0x0425 +#define regPCTL_SLICE0_STCTRL_REGISTER_SAVE_EXCL_SET1_BASE_IDX 1 +#define regPCTL_SLICE1_RENG_EXECUTE 0x0426 +#define regPCTL_SLICE1_RENG_EXECUTE_BASE_IDX 1 +#define regPCTL_SLICE1_RENG_RAM_INDEX 0x0427 +#define regPCTL_SLICE1_RENG_RAM_INDEX_BASE_IDX 1 +#define regPCTL_SLICE1_RENG_RAM_DATA 0x0428 +#define regPCTL_SLICE1_RENG_RAM_DATA_BASE_IDX 1 +#define regPCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE0 0x0429 +#define regPCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE0_BASE_IDX 1 +#define regPCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE1 0x042a +#define regPCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE1_BASE_IDX 1 +#define regPCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE2 0x042b +#define regPCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE2_BASE_IDX 1 +#define regPCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE3 0x042c +#define regPCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE3_BASE_IDX 1 +#define regPCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE4 0x042d +#define regPCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE4_BASE_IDX 1 +#define regPCTL_SLICE1_STCTRL_REGISTER_SAVE_EXCL_SET0 0x042e +#define regPCTL_SLICE1_STCTRL_REGISTER_SAVE_EXCL_SET0_BASE_IDX 1 +#define regPCTL_SLICE1_STCTRL_REGISTER_SAVE_EXCL_SET1 0x042f +#define regPCTL_SLICE1_STCTRL_REGISTER_SAVE_EXCL_SET1_BASE_IDX 1 +#define regPCTL_STATUS 0x0430 +#define regPCTL_STATUS_BASE_IDX 1 +#define regPCTL_PERFCOUNTER_LO 0x0432 +#define regPCTL_PERFCOUNTER_LO_BASE_IDX 1 +#define regPCTL_PERFCOUNTER_HI 0x0433 +#define regPCTL_PERFCOUNTER_HI_BASE_IDX 1 +#define regPCTL_PERFCOUNTER0_CFG 0x0434 +#define regPCTL_PERFCOUNTER0_CFG_BASE_IDX 1 +#define regPCTL_PERFCOUNTER1_CFG 0x0435 +#define regPCTL_PERFCOUNTER1_CFG_BASE_IDX 1 +#define regPCTL_PERFCOUNTER_RSLT_CNTL 0x0436 +#define regPCTL_PERFCOUNTER_RSLT_CNTL_BASE_IDX 1 +#define regPCTL_RESERVED_0 0x0437 +#define regPCTL_RESERVED_0_BASE_IDX 1 +#define regPCTL_RESERVED_1 0x0438 +#define regPCTL_RESERVED_1_BASE_IDX 1 +#define regPCTL_RESERVED_2 0x0439 +#define regPCTL_RESERVED_2_BASE_IDX 1 +#define regPCTL_RESERVED_3 0x043a +#define regPCTL_RESERVED_3_BASE_IDX 1 + + +// addressBlock: mmhub_mmutcl2_mmvmsharedpfdec +// base address: 0x69420 +#define regMMMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB 0x0508 +#define regMMMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB_BASE_IDX 1 +#define regMMMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB 0x0509 +#define regMMMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB_BASE_IDX 1 +#define regMMUTCL2_CGTT_CLK_CTRL 0x050a +#define regMMUTCL2_CGTT_CLK_CTRL_BASE_IDX 1 +#define regMMMC_SHARED_ACTIVE_FCN_ID 0x050b +#define regMMMC_SHARED_ACTIVE_FCN_ID_BASE_IDX 1 +#define regMMUTCL2_CGTT_BUSY_CTRL 0x050c +#define regMMUTCL2_CGTT_BUSY_CTRL_BASE_IDX 1 +#define regMMUTCL2_GROUP_RET_FAULT_STATUS 0x050d +#define regMMUTCL2_GROUP_RET_FAULT_STATUS_BASE_IDX 1 + + +// addressBlock: mmhub_mmutcl2_mmvml2pfdec +// base address: 0x694b0 +#define regMMVM_L2_CNTL 0x052c +#define regMMVM_L2_CNTL_BASE_IDX 1 +#define regMMVM_L2_CNTL2 0x052d +#define regMMVM_L2_CNTL2_BASE_IDX 1 +#define regMMVM_L2_CNTL3 0x052e +#define regMMVM_L2_CNTL3_BASE_IDX 1 +#define regMMVM_L2_STATUS 0x052f +#define regMMVM_L2_STATUS_BASE_IDX 1 +#define regMMVM_DUMMY_PAGE_FAULT_CNTL 0x0530 +#define regMMVM_DUMMY_PAGE_FAULT_CNTL_BASE_IDX 1 +#define regMMVM_DUMMY_PAGE_FAULT_ADDR_LO32 0x0531 +#define regMMVM_DUMMY_PAGE_FAULT_ADDR_LO32_BASE_IDX 1 +#define regMMVM_DUMMY_PAGE_FAULT_ADDR_HI32 0x0532 +#define regMMVM_DUMMY_PAGE_FAULT_ADDR_HI32_BASE_IDX 1 +#define regMMVM_INVALIDATE_CNTL 0x0533 +#define regMMVM_INVALIDATE_CNTL_BASE_IDX 1 +#define regMMVM_L2_PROTECTION_FAULT_CNTL_LO32 0x0534 +#define regMMVM_L2_PROTECTION_FAULT_CNTL_LO32_BASE_IDX 1 +#define regMMVM_L2_PROTECTION_FAULT_CNTL_HI32 0x0535 +#define regMMVM_L2_PROTECTION_FAULT_CNTL_HI32_BASE_IDX 1 +#define regMMVM_L2_PROTECTION_FAULT_CNTL2 0x0536 +#define regMMVM_L2_PROTECTION_FAULT_CNTL2_BASE_IDX 1 +#define regMMVM_L2_PROTECTION_FAULT_STATUS_LO32 0x0537 +#define regMMVM_L2_PROTECTION_FAULT_STATUS_LO32_BASE_IDX 1 +#define regMMVM_L2_PROTECTION_FAULT_STATUS_HI32 0x0538 +#define regMMVM_L2_PROTECTION_FAULT_STATUS_HI32_BASE_IDX 1 +#define regMMVM_L2_PROTECTION_FAULT_ADDR_LO32 0x0539 +#define regMMVM_L2_PROTECTION_FAULT_ADDR_LO32_BASE_IDX 1 +#define regMMVM_L2_PROTECTION_FAULT_ADDR_HI32 0x053a +#define regMMVM_L2_PROTECTION_FAULT_ADDR_HI32_BASE_IDX 1 +#define regMMVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32 0x053b +#define regMMVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32_BASE_IDX 1 +#define regMMVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32 0x053c +#define regMMVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32_BASE_IDX 1 +#define regMMVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32 0x053e +#define regMMVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32_BASE_IDX 1 +#define regMMVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32 0x053f +#define regMMVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32_BASE_IDX 1 +#define regMMVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32 0x0540 +#define regMMVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32_BASE_IDX 1 +#define regMMVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32 0x0541 +#define regMMVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32_BASE_IDX 1 +#define regMMVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32 0x0542 +#define regMMVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32_BASE_IDX 1 +#define regMMVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32 0x0543 +#define regMMVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32_BASE_IDX 1 +#define regMMVM_L2_CNTL4 0x0544 +#define regMMVM_L2_CNTL4_BASE_IDX 1 +#define regMMVM_L2_MM_GROUP_RT_CLASSES 0x0545 +#define regMMVM_L2_MM_GROUP_RT_CLASSES_BASE_IDX 1 +#define regMMVM_L2_BANK_SELECT_RESERVED_CID 0x0546 +#define regMMVM_L2_BANK_SELECT_RESERVED_CID_BASE_IDX 1 +#define regMMVM_L2_BANK_SELECT_RESERVED_CID2 0x0547 +#define regMMVM_L2_BANK_SELECT_RESERVED_CID2_BASE_IDX 1 +#define regMMVM_L2_CACHE_PARITY_CNTL 0x0548 +#define regMMVM_L2_CACHE_PARITY_CNTL_BASE_IDX 1 +#define regMMVM_L2_CGTT_CLK_CTRL 0x0549 +#define regMMVM_L2_CGTT_CLK_CTRL_BASE_IDX 1 +#define regMMVM_L2_CNTL5 0x054a +#define regMMVM_L2_CNTL5_BASE_IDX 1 +#define regMMVM_L2_GCR_CNTL 0x054b +#define regMMVM_L2_GCR_CNTL_BASE_IDX 1 +#define regMMVM_L2_CGTT_BUSY_CTRL 0x054c +#define regMMVM_L2_CGTT_BUSY_CTRL_BASE_IDX 1 +#define regMMVM_L2_PTE_CACHE_DUMP_CNTL 0x054d +#define regMMVM_L2_PTE_CACHE_DUMP_CNTL_BASE_IDX 1 +#define regMMVM_L2_PTE_CACHE_DUMP_READ 0x054e +#define regMMVM_L2_PTE_CACHE_DUMP_READ_BASE_IDX 1 +#define regMMVM_L2_BANK_SELECT_MASKS 0x0557 +#define regMMVM_L2_BANK_SELECT_MASKS_BASE_IDX 1 +#define regMMUTCL2_CREDIT_SAFETY_GROUP_RET_CDC 0x0558 +#define regMMUTCL2_CREDIT_SAFETY_GROUP_RET_CDC_BASE_IDX 1 +#define regMMUTCL2_CREDIT_SAFETY_GROUP_CLIENTS_INVREQ_CDC 0x0559 +#define regMMUTCL2_CREDIT_SAFETY_GROUP_CLIENTS_INVREQ_CDC_BASE_IDX 1 +#define regMMUTCL2_CREDIT_SAFETY_GROUP_CLIENTS_INVREQ_NOCDC 0x055a +#define regMMUTCL2_CREDIT_SAFETY_GROUP_CLIENTS_INVREQ_NOCDC_BASE_IDX 1 +#define regMMVML2_CREDIT_SAFETY_IH_FAULT_INTERRUPT 0x055b +#define regMMVML2_CREDIT_SAFETY_IH_FAULT_INTERRUPT_BASE_IDX 1 +#define regMMVML2_WALKER_CREDIT_SAFETY_FETCH_RDREQ 0x055c +#define regMMVML2_WALKER_CREDIT_SAFETY_FETCH_RDREQ_BASE_IDX 1 + + +// addressBlock: mmhub_mmutcl2_mmvml2prdec +// base address: 0x69630 +#define regMMMC_VM_L2_PERFCOUNTER_LO 0x058c +#define regMMMC_VM_L2_PERFCOUNTER_LO_BASE_IDX 1 +#define regMMMC_VM_L2_PERFCOUNTER_HI 0x058d +#define regMMMC_VM_L2_PERFCOUNTER_HI_BASE_IDX 1 +#define regMMUTCL2_PERFCOUNTER_LO 0x058e +#define regMMUTCL2_PERFCOUNTER_LO_BASE_IDX 1 +#define regMMUTCL2_PERFCOUNTER_HI 0x058f +#define regMMUTCL2_PERFCOUNTER_HI_BASE_IDX 1 + + +// addressBlock: mmhub_mmutcl2_mmatcl2prdec +// base address: 0x69670 +#define regMM_ATC_L2_PERFCOUNTER_LO 0x059c +#define regMM_ATC_L2_PERFCOUNTER_LO_BASE_IDX 1 +#define regMM_ATC_L2_PERFCOUNTER_HI 0x059d +#define regMM_ATC_L2_PERFCOUNTER_HI_BASE_IDX 1 + + +// addressBlock: mmhub_mmutcl2_mmvml2pldec +// base address: 0x696a0 +#define regMMMC_VM_L2_PERFCOUNTER0_CFG 0x05a8 +#define regMMMC_VM_L2_PERFCOUNTER0_CFG_BASE_IDX 1 +#define regMMMC_VM_L2_PERFCOUNTER1_CFG 0x05a9 +#define regMMMC_VM_L2_PERFCOUNTER1_CFG_BASE_IDX 1 +#define regMMMC_VM_L2_PERFCOUNTER2_CFG 0x05aa +#define regMMMC_VM_L2_PERFCOUNTER2_CFG_BASE_IDX 1 +#define regMMMC_VM_L2_PERFCOUNTER3_CFG 0x05ab +#define regMMMC_VM_L2_PERFCOUNTER3_CFG_BASE_IDX 1 +#define regMMMC_VM_L2_PERFCOUNTER4_CFG 0x05ac +#define regMMMC_VM_L2_PERFCOUNTER4_CFG_BASE_IDX 1 +#define regMMMC_VM_L2_PERFCOUNTER5_CFG 0x05ad +#define regMMMC_VM_L2_PERFCOUNTER5_CFG_BASE_IDX 1 +#define regMMMC_VM_L2_PERFCOUNTER6_CFG 0x05ae +#define regMMMC_VM_L2_PERFCOUNTER6_CFG_BASE_IDX 1 +#define regMMMC_VM_L2_PERFCOUNTER7_CFG 0x05af +#define regMMMC_VM_L2_PERFCOUNTER7_CFG_BASE_IDX 1 +#define regMMMC_VM_L2_PERFCOUNTER_RSLT_CNTL 0x05b0 +#define regMMMC_VM_L2_PERFCOUNTER_RSLT_CNTL_BASE_IDX 1 +#define regMMUTCL2_PERFCOUNTER0_CFG 0x05b1 +#define regMMUTCL2_PERFCOUNTER0_CFG_BASE_IDX 1 +#define regMMUTCL2_PERFCOUNTER1_CFG 0x05b2 +#define regMMUTCL2_PERFCOUNTER1_CFG_BASE_IDX 1 +#define regMMUTCL2_PERFCOUNTER2_CFG 0x05b3 +#define regMMUTCL2_PERFCOUNTER2_CFG_BASE_IDX 1 +#define regMMUTCL2_PERFCOUNTER3_CFG 0x05b4 +#define regMMUTCL2_PERFCOUNTER3_CFG_BASE_IDX 1 +#define regMMUTCL2_PERFCOUNTER_RSLT_CNTL 0x05b5 +#define regMMUTCL2_PERFCOUNTER_RSLT_CNTL_BASE_IDX 1 + + +// addressBlock: mmhub_mmutcl2_mmatcl2pldec +// base address: 0x696e0 +#define regMM_ATC_L2_PERFCOUNTER0_CFG 0x05b8 +#define regMM_ATC_L2_PERFCOUNTER0_CFG_BASE_IDX 1 +#define regMM_ATC_L2_PERFCOUNTER1_CFG 0x05b9 +#define regMM_ATC_L2_PERFCOUNTER1_CFG_BASE_IDX 1 +#define regMM_ATC_L2_PERFCOUNTER_RSLT_CNTL 0x05ba +#define regMM_ATC_L2_PERFCOUNTER_RSLT_CNTL_BASE_IDX 1 + + +// addressBlock: mmhub_mmutcl2_mmvmsharedvcdec +// base address: 0x69740 #define regMMMC_VM_FB_LOCATION_BASE 0x05d0 #define regMMMC_VM_FB_LOCATION_BASE_BASE_IDX 1 +#define regMMMC_VM_FB_LOCATION_TOP 0x05d1 +#define regMMMC_VM_FB_LOCATION_TOP_BASE_IDX 1 +#define regMMMC_VM_AGP_TOP 0x05d2 +#define regMMMC_VM_AGP_TOP_BASE_IDX 1 +#define regMMMC_VM_AGP_BOT 0x05d3 +#define regMMMC_VM_AGP_BOT_BASE_IDX 1 +#define regMMMC_VM_AGP_BASE 0x05d4 +#define regMMMC_VM_AGP_BASE_BASE_IDX 1 +#define regMMMC_VM_SYSTEM_APERTURE_LOW_ADDR 0x05d5 +#define regMMMC_VM_SYSTEM_APERTURE_LOW_ADDR_BASE_IDX 1 +#define regMMMC_VM_SYSTEM_APERTURE_HIGH_ADDR 0x05d6 +#define regMMMC_VM_SYSTEM_APERTURE_HIGH_ADDR_BASE_IDX 1 +#define regMMMC_VM_MX_L1_TLB_CNTL 0x05d7 +#define regMMMC_VM_MX_L1_TLB_CNTL_BASE_IDX 1 + + +// addressBlock: mmhub_mmutcl2_mmvml2vcdec +// base address: 0x69780 +#define regMMVM_CONTEXT0_CNTL 0x05e0 +#define regMMVM_CONTEXT0_CNTL_BASE_IDX 1 +#define regMMVM_CONTEXT1_CNTL 0x05e1 +#define regMMVM_CONTEXT1_CNTL_BASE_IDX 1 +#define regMMVM_CONTEXT2_CNTL 0x05e2 +#define regMMVM_CONTEXT2_CNTL_BASE_IDX 1 +#define regMMVM_CONTEXT3_CNTL 0x05e3 +#define regMMVM_CONTEXT3_CNTL_BASE_IDX 1 +#define regMMVM_CONTEXT4_CNTL 0x05e4 +#define regMMVM_CONTEXT4_CNTL_BASE_IDX 1 +#define regMMVM_CONTEXT5_CNTL 0x05e5 +#define regMMVM_CONTEXT5_CNTL_BASE_IDX 1 +#define regMMVM_CONTEXT6_CNTL 0x05e6 +#define regMMVM_CONTEXT6_CNTL_BASE_IDX 1 +#define regMMVM_CONTEXT7_CNTL 0x05e7 +#define regMMVM_CONTEXT7_CNTL_BASE_IDX 1 +#define regMMVM_CONTEXT8_CNTL 0x05e8 +#define regMMVM_CONTEXT8_CNTL_BASE_IDX 1 +#define regMMVM_CONTEXT9_CNTL 0x05e9 +#define regMMVM_CONTEXT9_CNTL_BASE_IDX 1 +#define regMMVM_CONTEXT10_CNTL 0x05ea +#define regMMVM_CONTEXT10_CNTL_BASE_IDX 1 +#define regMMVM_CONTEXT11_CNTL 0x05eb +#define regMMVM_CONTEXT11_CNTL_BASE_IDX 1 +#define regMMVM_CONTEXT12_CNTL 0x05ec +#define regMMVM_CONTEXT12_CNTL_BASE_IDX 1 +#define regMMVM_CONTEXT13_CNTL 0x05ed +#define regMMVM_CONTEXT13_CNTL_BASE_IDX 1 +#define regMMVM_CONTEXT14_CNTL 0x05ee +#define regMMVM_CONTEXT14_CNTL_BASE_IDX 1 +#define regMMVM_CONTEXT15_CNTL 0x05ef +#define regMMVM_CONTEXT15_CNTL_BASE_IDX 1 +#define regMMVM_CONTEXTS_DISABLE 0x05f0 +#define regMMVM_CONTEXTS_DISABLE_BASE_IDX 1 +#define regMMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32 0x05f1 +#define regMMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 1 +#define regMMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32 0x05f2 +#define regMMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 1 +#define regMMVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32 0x05f3 +#define regMMVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 1 +#define regMMVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32 0x05f4 +#define regMMVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 1 +#define regMMVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32 0x05f5 +#define regMMVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 1 +#define regMMVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32 0x05f6 +#define regMMVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 1 +#define regMMVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32 0x05f7 +#define regMMVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 1 +#define regMMVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32 0x05f8 +#define regMMVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 1 +#define regMMVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32 0x05f9 +#define regMMVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 1 +#define regMMVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32 0x05fa +#define regMMVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 1 +#define regMMVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32 0x05fb +#define regMMVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 1 +#define regMMVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32 0x05fc +#define regMMVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 1 +#define regMMVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32 0x05fd +#define regMMVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 1 +#define regMMVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32 0x05fe +#define regMMVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 1 +#define regMMVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32 0x05ff +#define regMMVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 1 +#define regMMVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32 0x0600 +#define regMMVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 1 +#define regMMVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32 0x0601 +#define regMMVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 1 +#define regMMVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32 0x0602 +#define regMMVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 1 +#define regMMVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32 0x0603 +#define regMMVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 1 +#define regMMVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32 0x0604 +#define regMMVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 1 +#define regMMVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32 0x0605 +#define regMMVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 1 +#define regMMVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32 0x0606 +#define regMMVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 1 +#define regMMVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32 0x0607 +#define regMMVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 1 +#define regMMVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32 0x0608 +#define regMMVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 1 +#define regMMVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32 0x0609 +#define regMMVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 1 +#define regMMVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32 0x060a +#define regMMVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 1 +#define regMMVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32 0x060b +#define regMMVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 1 +#define regMMVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32 0x060c +#define regMMVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 1 +#define regMMVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32 0x060d +#define regMMVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 1 +#define regMMVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32 0x060e +#define regMMVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 1 +#define regMMVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32 0x060f +#define regMMVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 1 +#define regMMVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32 0x0610 +#define regMMVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 1 +#define regMMVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32 0x0611 +#define regMMVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 1 +#define regMMVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32 0x0612 +#define regMMVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 1 +#define regMMVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32 0x0613 +#define regMMVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 1 +#define regMMVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32 0x0614 +#define regMMVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 1 +#define regMMVM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32 0x0615 +#define regMMVM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 1 +#define regMMVM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32 0x0616 +#define regMMVM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 1 +#define regMMVM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32 0x0617 +#define regMMVM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 1 +#define regMMVM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32 0x0618 +#define regMMVM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 1 +#define regMMVM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32 0x0619 +#define regMMVM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 1 +#define regMMVM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32 0x061a +#define regMMVM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 1 +#define regMMVM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32 0x061b +#define regMMVM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 1 +#define regMMVM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32 0x061c +#define regMMVM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 1 +#define regMMVM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32 0x061d +#define regMMVM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 1 +#define regMMVM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32 0x061e +#define regMMVM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 1 +#define regMMVM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32 0x061f +#define regMMVM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 1 +#define regMMVM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32 0x0620 +#define regMMVM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 1 +#define regMMVM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32 0x0621 +#define regMMVM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 1 +#define regMMVM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32 0x0622 +#define regMMVM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 1 +#define regMMVM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32 0x0623 +#define regMMVM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 1 +#define regMMVM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32 0x0624 +#define regMMVM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 1 +#define regMMVM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32 0x0625 +#define regMMVM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 1 +#define regMMVM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32 0x0626 +#define regMMVM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 1 +#define regMMVM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32 0x0627 +#define regMMVM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 1 +#define regMMVM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32 0x0628 +#define regMMVM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 1 +#define regMMVM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32 0x0629 +#define regMMVM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 1 +#define regMMVM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32 0x062a +#define regMMVM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 1 +#define regMMVM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32 0x062b +#define regMMVM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 1 +#define regMMVM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32 0x062c +#define regMMVM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 1 +#define regMMVM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32 0x062d +#define regMMVM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 1 +#define regMMVM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32 0x062e +#define regMMVM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 1 +#define regMMVM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32 0x062f +#define regMMVM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 1 +#define regMMVM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32 0x0630 +#define regMMVM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 1 +#define regMMVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32 0x0631 +#define regMMVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 1 +#define regMMVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32 0x0632 +#define regMMVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 1 +#define regMMVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32 0x0633 +#define regMMVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 1 +#define regMMVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32 0x0634 +#define regMMVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 1 +#define regMMVM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32 0x0635 +#define regMMVM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 1 +#define regMMVM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32 0x0636 +#define regMMVM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 1 +#define regMMVM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32 0x0637 +#define regMMVM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 1 +#define regMMVM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32 0x0638 +#define regMMVM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 1 +#define regMMVM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32 0x0639 +#define regMMVM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 1 +#define regMMVM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32 0x063a +#define regMMVM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 1 +#define regMMVM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32 0x063b +#define regMMVM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 1 +#define regMMVM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32 0x063c +#define regMMVM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 1 +#define regMMVM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32 0x063d +#define regMMVM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 1 +#define regMMVM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32 0x063e +#define regMMVM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 1 +#define regMMVM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32 0x063f +#define regMMVM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 1 +#define regMMVM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32 0x0640 +#define regMMVM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 1 +#define regMMVM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32 0x0641 +#define regMMVM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 1 +#define regMMVM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32 0x0642 +#define regMMVM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 1 +#define regMMVM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32 0x0643 +#define regMMVM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 1 +#define regMMVM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32 0x0644 +#define regMMVM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 1 +#define regMMVM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32 0x0645 +#define regMMVM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 1 +#define regMMVM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32 0x0646 +#define regMMVM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 1 +#define regMMVM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32 0x0647 +#define regMMVM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 1 +#define regMMVM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32 0x0648 +#define regMMVM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 1 +#define regMMVM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32 0x0649 +#define regMMVM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 1 +#define regMMVM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32 0x064a +#define regMMVM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 1 +#define regMMVM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32 0x064b +#define regMMVM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 1 +#define regMMVM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32 0x064c +#define regMMVM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 1 +#define regMMVM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32 0x064d +#define regMMVM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 1 +#define regMMVM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32 0x064e +#define regMMVM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 1 +#define regMMVM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32 0x064f +#define regMMVM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 1 +#define regMMVM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32 0x0650 +#define regMMVM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 1 +#define regMMVM_L2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES 0x0651 +#define regMMVM_L2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX 1 +#define regMMVM_L2_CONTEXT0_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES 0x0652 +#define regMMVM_L2_CONTEXT0_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX 1 +#define regMMVM_L2_CONTEXT1_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES 0x0653 +#define regMMVM_L2_CONTEXT1_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX 1 +#define regMMVM_L2_CONTEXT2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES 0x0654 +#define regMMVM_L2_CONTEXT2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX 1 +#define regMMVM_L2_CONTEXT3_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES 0x0655 +#define regMMVM_L2_CONTEXT3_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX 1 +#define regMMVM_L2_CONTEXT4_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES 0x0656 +#define regMMVM_L2_CONTEXT4_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX 1 +#define regMMVM_L2_CONTEXT5_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES 0x0657 +#define regMMVM_L2_CONTEXT5_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX 1 +#define regMMVM_L2_CONTEXT6_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES 0x0658 +#define regMMVM_L2_CONTEXT6_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX 1 +#define regMMVM_L2_CONTEXT7_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES 0x0659 +#define regMMVM_L2_CONTEXT7_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX 1 +#define regMMVM_L2_CONTEXT8_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES 0x065a +#define regMMVM_L2_CONTEXT8_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX 1 +#define regMMVM_L2_CONTEXT9_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES 0x065b +#define regMMVM_L2_CONTEXT9_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX 1 +#define regMMVM_L2_CONTEXT10_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES 0x065c +#define regMMVM_L2_CONTEXT10_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX 1 +#define regMMVM_L2_CONTEXT11_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES 0x065d +#define regMMVM_L2_CONTEXT11_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX 1 +#define regMMVM_L2_CONTEXT12_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES 0x065e +#define regMMVM_L2_CONTEXT12_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX 1 +#define regMMVM_L2_CONTEXT13_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES 0x065f +#define regMMVM_L2_CONTEXT13_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX 1 +#define regMMVM_L2_CONTEXT14_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES 0x0660 +#define regMMVM_L2_CONTEXT14_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX 1 +#define regMMVM_L2_CONTEXT15_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES 0x0661 +#define regMMVM_L2_CONTEXT15_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX 1 + + +// addressBlock: mmhub_mmutcl2_mmvml2indec +// base address: 0x699a0 +#define regMMVM_INVALIDATE_ENG0_SEM 0x0668 +#define regMMVM_INVALIDATE_ENG0_SEM_BASE_IDX 1 +#define regMMVM_INVALIDATE_ENG0_REQ 0x0669 +#define regMMVM_INVALIDATE_ENG0_REQ_BASE_IDX 1 +#define regMMVM_INVALIDATE_ENG0_ACK 0x066a +#define regMMVM_INVALIDATE_ENG0_ACK_BASE_IDX 1 +#define regMMVM_INVALIDATE_ENG0_ADDR_RANGE_LO32 0x066b +#define regMMVM_INVALIDATE_ENG0_ADDR_RANGE_LO32_BASE_IDX 1 +#define regMMVM_INVALIDATE_ENG0_ADDR_RANGE_HI32 0x066c +#define regMMVM_INVALIDATE_ENG0_ADDR_RANGE_HI32_BASE_IDX 1 +#define regMMVM_INVALIDATE_ENG1_SEM 0x0670 +#define regMMVM_INVALIDATE_ENG1_SEM_BASE_IDX 1 +#define regMMVM_INVALIDATE_ENG1_REQ 0x0671 +#define regMMVM_INVALIDATE_ENG1_REQ_BASE_IDX 1 +#define regMMVM_INVALIDATE_ENG1_ACK 0x0672 +#define regMMVM_INVALIDATE_ENG1_ACK_BASE_IDX 1 +#define regMMVM_INVALIDATE_ENG1_ADDR_RANGE_LO32 0x0673 +#define regMMVM_INVALIDATE_ENG1_ADDR_RANGE_LO32_BASE_IDX 1 +#define regMMVM_INVALIDATE_ENG1_ADDR_RANGE_HI32 0x0674 +#define regMMVM_INVALIDATE_ENG1_ADDR_RANGE_HI32_BASE_IDX 1 +#define regMMVM_INVALIDATE_ENG2_SEM 0x0678 +#define regMMVM_INVALIDATE_ENG2_SEM_BASE_IDX 1 +#define regMMVM_INVALIDATE_ENG2_REQ 0x0679 +#define regMMVM_INVALIDATE_ENG2_REQ_BASE_IDX 1 +#define regMMVM_INVALIDATE_ENG2_ACK 0x067a +#define regMMVM_INVALIDATE_ENG2_ACK_BASE_IDX 1 +#define regMMVM_INVALIDATE_ENG2_ADDR_RANGE_LO32 0x067b +#define regMMVM_INVALIDATE_ENG2_ADDR_RANGE_LO32_BASE_IDX 1 +#define regMMVM_INVALIDATE_ENG2_ADDR_RANGE_HI32 0x067c +#define regMMVM_INVALIDATE_ENG2_ADDR_RANGE_HI32_BASE_IDX 1 +#define regMMVM_INVALIDATE_ENG3_SEM 0x0680 +#define regMMVM_INVALIDATE_ENG3_SEM_BASE_IDX 1 +#define regMMVM_INVALIDATE_ENG3_REQ 0x0681 +#define regMMVM_INVALIDATE_ENG3_REQ_BASE_IDX 1 +#define regMMVM_INVALIDATE_ENG3_ACK 0x0682 +#define regMMVM_INVALIDATE_ENG3_ACK_BASE_IDX 1 +#define regMMVM_INVALIDATE_ENG3_ADDR_RANGE_LO32 0x0683 +#define regMMVM_INVALIDATE_ENG3_ADDR_RANGE_LO32_BASE_IDX 1 +#define regMMVM_INVALIDATE_ENG3_ADDR_RANGE_HI32 0x0684 +#define regMMVM_INVALIDATE_ENG3_ADDR_RANGE_HI32_BASE_IDX 1 +#define regMMVM_INVALIDATE_ENG4_SEM 0x0688 +#define regMMVM_INVALIDATE_ENG4_SEM_BASE_IDX 1 +#define regMMVM_INVALIDATE_ENG4_REQ 0x0689 +#define regMMVM_INVALIDATE_ENG4_REQ_BASE_IDX 1 +#define regMMVM_INVALIDATE_ENG4_ACK 0x068a +#define regMMVM_INVALIDATE_ENG4_ACK_BASE_IDX 1 +#define regMMVM_INVALIDATE_ENG4_ADDR_RANGE_LO32 0x068b +#define regMMVM_INVALIDATE_ENG4_ADDR_RANGE_LO32_BASE_IDX 1 +#define regMMVM_INVALIDATE_ENG4_ADDR_RANGE_HI32 0x068c +#define regMMVM_INVALIDATE_ENG4_ADDR_RANGE_HI32_BASE_IDX 1 +#define regMMVM_INVALIDATE_ENG5_SEM 0x0690 +#define regMMVM_INVALIDATE_ENG5_SEM_BASE_IDX 1 +#define regMMVM_INVALIDATE_ENG5_REQ 0x0691 +#define regMMVM_INVALIDATE_ENG5_REQ_BASE_IDX 1 +#define regMMVM_INVALIDATE_ENG5_ACK 0x0692 +#define regMMVM_INVALIDATE_ENG5_ACK_BASE_IDX 1 +#define regMMVM_INVALIDATE_ENG5_ADDR_RANGE_LO32 0x0693 +#define regMMVM_INVALIDATE_ENG5_ADDR_RANGE_LO32_BASE_IDX 1 +#define regMMVM_INVALIDATE_ENG5_ADDR_RANGE_HI32 0x0694 +#define regMMVM_INVALIDATE_ENG5_ADDR_RANGE_HI32_BASE_IDX 1 +#define regMMVM_INVALIDATE_ENG6_SEM 0x0698 +#define regMMVM_INVALIDATE_ENG6_SEM_BASE_IDX 1 +#define regMMVM_INVALIDATE_ENG6_REQ 0x0699 +#define regMMVM_INVALIDATE_ENG6_REQ_BASE_IDX 1 +#define regMMVM_INVALIDATE_ENG6_ACK 0x069a +#define regMMVM_INVALIDATE_ENG6_ACK_BASE_IDX 1 +#define regMMVM_INVALIDATE_ENG6_ADDR_RANGE_LO32 0x069b +#define regMMVM_INVALIDATE_ENG6_ADDR_RANGE_LO32_BASE_IDX 1 +#define regMMVM_INVALIDATE_ENG6_ADDR_RANGE_HI32 0x069c +#define regMMVM_INVALIDATE_ENG6_ADDR_RANGE_HI32_BASE_IDX 1 +#define regMMVM_INVALIDATE_ENG7_SEM 0x06a0 +#define regMMVM_INVALIDATE_ENG7_SEM_BASE_IDX 1 +#define regMMVM_INVALIDATE_ENG7_REQ 0x06a1 +#define regMMVM_INVALIDATE_ENG7_REQ_BASE_IDX 1 +#define regMMVM_INVALIDATE_ENG7_ACK 0x06a2 +#define regMMVM_INVALIDATE_ENG7_ACK_BASE_IDX 1 +#define regMMVM_INVALIDATE_ENG7_ADDR_RANGE_LO32 0x06a3 +#define regMMVM_INVALIDATE_ENG7_ADDR_RANGE_LO32_BASE_IDX 1 +#define regMMVM_INVALIDATE_ENG7_ADDR_RANGE_HI32 0x06a4 +#define regMMVM_INVALIDATE_ENG7_ADDR_RANGE_HI32_BASE_IDX 1 +#define regMMVM_INVALIDATE_ENG8_SEM 0x06a8 +#define regMMVM_INVALIDATE_ENG8_SEM_BASE_IDX 1 +#define regMMVM_INVALIDATE_ENG8_REQ 0x06a9 +#define regMMVM_INVALIDATE_ENG8_REQ_BASE_IDX 1 +#define regMMVM_INVALIDATE_ENG8_ACK 0x06aa +#define regMMVM_INVALIDATE_ENG8_ACK_BASE_IDX 1 +#define regMMVM_INVALIDATE_ENG8_ADDR_RANGE_LO32 0x06ab +#define regMMVM_INVALIDATE_ENG8_ADDR_RANGE_LO32_BASE_IDX 1 +#define regMMVM_INVALIDATE_ENG8_ADDR_RANGE_HI32 0x06ac +#define regMMVM_INVALIDATE_ENG8_ADDR_RANGE_HI32_BASE_IDX 1 +#define regMMVM_INVALIDATE_ENG9_SEM 0x06b0 +#define regMMVM_INVALIDATE_ENG9_SEM_BASE_IDX 1 +#define regMMVM_INVALIDATE_ENG9_REQ 0x06b1 +#define regMMVM_INVALIDATE_ENG9_REQ_BASE_IDX 1 +#define regMMVM_INVALIDATE_ENG9_ACK 0x06b2 +#define regMMVM_INVALIDATE_ENG9_ACK_BASE_IDX 1 +#define regMMVM_INVALIDATE_ENG9_ADDR_RANGE_LO32 0x06b3 +#define regMMVM_INVALIDATE_ENG9_ADDR_RANGE_LO32_BASE_IDX 1 +#define regMMVM_INVALIDATE_ENG9_ADDR_RANGE_HI32 0x06b4 +#define regMMVM_INVALIDATE_ENG9_ADDR_RANGE_HI32_BASE_IDX 1 +#define regMMVM_INVALIDATE_ENG10_SEM 0x06b8 +#define regMMVM_INVALIDATE_ENG10_SEM_BASE_IDX 1 +#define regMMVM_INVALIDATE_ENG10_REQ 0x06b9 +#define regMMVM_INVALIDATE_ENG10_REQ_BASE_IDX 1 +#define regMMVM_INVALIDATE_ENG10_ACK 0x06ba +#define regMMVM_INVALIDATE_ENG10_ACK_BASE_IDX 1 +#define regMMVM_INVALIDATE_ENG10_ADDR_RANGE_LO32 0x06bb +#define regMMVM_INVALIDATE_ENG10_ADDR_RANGE_LO32_BASE_IDX 1 +#define regMMVM_INVALIDATE_ENG10_ADDR_RANGE_HI32 0x06bc +#define regMMVM_INVALIDATE_ENG10_ADDR_RANGE_HI32_BASE_IDX 1 +#define regMMVM_INVALIDATE_ENG11_SEM 0x06c0 +#define regMMVM_INVALIDATE_ENG11_SEM_BASE_IDX 1 +#define regMMVM_INVALIDATE_ENG11_REQ 0x06c1 +#define regMMVM_INVALIDATE_ENG11_REQ_BASE_IDX 1 +#define regMMVM_INVALIDATE_ENG11_ACK 0x06c2 +#define regMMVM_INVALIDATE_ENG11_ACK_BASE_IDX 1 +#define regMMVM_INVALIDATE_ENG11_ADDR_RANGE_LO32 0x06c3 +#define regMMVM_INVALIDATE_ENG11_ADDR_RANGE_LO32_BASE_IDX 1 +#define regMMVM_INVALIDATE_ENG11_ADDR_RANGE_HI32 0x06c4 +#define regMMVM_INVALIDATE_ENG11_ADDR_RANGE_HI32_BASE_IDX 1 +#define regMMVM_INVALIDATE_ENG12_SEM 0x06c8 +#define regMMVM_INVALIDATE_ENG12_SEM_BASE_IDX 1 +#define regMMVM_INVALIDATE_ENG12_REQ 0x06c9 +#define regMMVM_INVALIDATE_ENG12_REQ_BASE_IDX 1 +#define regMMVM_INVALIDATE_ENG12_ACK 0x06ca +#define regMMVM_INVALIDATE_ENG12_ACK_BASE_IDX 1 +#define regMMVM_INVALIDATE_ENG12_ADDR_RANGE_LO32 0x06cb +#define regMMVM_INVALIDATE_ENG12_ADDR_RANGE_LO32_BASE_IDX 1 +#define regMMVM_INVALIDATE_ENG12_ADDR_RANGE_HI32 0x06cc +#define regMMVM_INVALIDATE_ENG12_ADDR_RANGE_HI32_BASE_IDX 1 +#define regMMVM_INVALIDATE_ENG13_SEM 0x06d0 +#define regMMVM_INVALIDATE_ENG13_SEM_BASE_IDX 1 +#define regMMVM_INVALIDATE_ENG13_REQ 0x06d1 +#define regMMVM_INVALIDATE_ENG13_REQ_BASE_IDX 1 +#define regMMVM_INVALIDATE_ENG13_ACK 0x06d2 +#define regMMVM_INVALIDATE_ENG13_ACK_BASE_IDX 1 +#define regMMVM_INVALIDATE_ENG13_ADDR_RANGE_LO32 0x06d3 +#define regMMVM_INVALIDATE_ENG13_ADDR_RANGE_LO32_BASE_IDX 1 +#define regMMVM_INVALIDATE_ENG13_ADDR_RANGE_HI32 0x06d4 +#define regMMVM_INVALIDATE_ENG13_ADDR_RANGE_HI32_BASE_IDX 1 +#define regMMVM_INVALIDATE_ENG14_SEM 0x06d8 +#define regMMVM_INVALIDATE_ENG14_SEM_BASE_IDX 1 +#define regMMVM_INVALIDATE_ENG14_REQ 0x06d9 +#define regMMVM_INVALIDATE_ENG14_REQ_BASE_IDX 1 +#define regMMVM_INVALIDATE_ENG14_ACK 0x06da +#define regMMVM_INVALIDATE_ENG14_ACK_BASE_IDX 1 +#define regMMVM_INVALIDATE_ENG14_ADDR_RANGE_LO32 0x06db +#define regMMVM_INVALIDATE_ENG14_ADDR_RANGE_LO32_BASE_IDX 1 +#define regMMVM_INVALIDATE_ENG14_ADDR_RANGE_HI32 0x06dc +#define regMMVM_INVALIDATE_ENG14_ADDR_RANGE_HI32_BASE_IDX 1 +#define regMMVM_INVALIDATE_ENG15_SEM 0x06e0 +#define regMMVM_INVALIDATE_ENG15_SEM_BASE_IDX 1 +#define regMMVM_INVALIDATE_ENG15_REQ 0x06e1 +#define regMMVM_INVALIDATE_ENG15_REQ_BASE_IDX 1 +#define regMMVM_INVALIDATE_ENG15_ACK 0x06e2 +#define regMMVM_INVALIDATE_ENG15_ACK_BASE_IDX 1 +#define regMMVM_INVALIDATE_ENG15_ADDR_RANGE_LO32 0x06e3 +#define regMMVM_INVALIDATE_ENG15_ADDR_RANGE_LO32_BASE_IDX 1 +#define regMMVM_INVALIDATE_ENG15_ADDR_RANGE_HI32 0x06e4 +#define regMMVM_INVALIDATE_ENG15_ADDR_RANGE_HI32_BASE_IDX 1 +#define regMMVM_INVALIDATE_ENG16_SEM 0x06e8 +#define regMMVM_INVALIDATE_ENG16_SEM_BASE_IDX 1 +#define regMMVM_INVALIDATE_ENG16_REQ 0x06e9 +#define regMMVM_INVALIDATE_ENG16_REQ_BASE_IDX 1 +#define regMMVM_INVALIDATE_ENG16_ACK 0x06ea +#define regMMVM_INVALIDATE_ENG16_ACK_BASE_IDX 1 +#define regMMVM_INVALIDATE_ENG16_ADDR_RANGE_LO32 0x06eb +#define regMMVM_INVALIDATE_ENG16_ADDR_RANGE_LO32_BASE_IDX 1 +#define regMMVM_INVALIDATE_ENG16_ADDR_RANGE_HI32 0x06ec +#define regMMVM_INVALIDATE_ENG16_ADDR_RANGE_HI32_BASE_IDX 1 +#define regMMVM_INVALIDATE_ENG17_SEM 0x06f0 +#define regMMVM_INVALIDATE_ENG17_SEM_BASE_IDX 1 +#define regMMVM_INVALIDATE_ENG17_REQ 0x06f1 +#define regMMVM_INVALIDATE_ENG17_REQ_BASE_IDX 1 +#define regMMVM_INVALIDATE_ENG17_ACK 0x06f2 +#define regMMVM_INVALIDATE_ENG17_ACK_BASE_IDX 1 +#define regMMVM_INVALIDATE_ENG17_ADDR_RANGE_LO32 0x06f3 +#define regMMVM_INVALIDATE_ENG17_ADDR_RANGE_LO32_BASE_IDX 1 +#define regMMVM_INVALIDATE_ENG17_ADDR_RANGE_HI32 0x06f4 +#define regMMVM_INVALIDATE_ENG17_ADDR_RANGE_HI32_BASE_IDX 1 + + +// addressBlock: mmhub_mmutcl2_mmvmsharedhvdec +// base address: 0x69c20 +#define regMMVM_PCIE_ATS_CNTL 0x0708 +#define regMMVM_PCIE_ATS_CNTL_BASE_IDX 1 +#define regMMMC_VM_NB_MMIOBASE 0x0709 +#define regMMMC_VM_NB_MMIOBASE_BASE_IDX 1 +#define regMMMC_VM_NB_MMIOLIMIT 0x070a +#define regMMMC_VM_NB_MMIOLIMIT_BASE_IDX 1 +#define regMMMC_VM_NB_PCI_CTRL 0x070b +#define regMMMC_VM_NB_PCI_CTRL_BASE_IDX 1 +#define regMMMC_VM_NB_PCI_ARB 0x070c +#define regMMMC_VM_NB_PCI_ARB_BASE_IDX 1 +#define regMMMC_VM_NB_TOP_OF_DRAM_SLOT1 0x070d +#define regMMMC_VM_NB_TOP_OF_DRAM_SLOT1_BASE_IDX 1 +#define regMMMC_VM_NB_LOWER_TOP_OF_DRAM2 0x070e +#define regMMMC_VM_NB_LOWER_TOP_OF_DRAM2_BASE_IDX 1 +#define regMMMC_VM_NB_UPPER_TOP_OF_DRAM2 0x070f +#define regMMMC_VM_NB_UPPER_TOP_OF_DRAM2_BASE_IDX 1 +#define regMMMC_VM_STEERING 0x0710 +#define regMMMC_VM_STEERING_BASE_IDX 1 +#define regMMMC_SHARED_VIRT_RESET_REQ 0x0711 +#define regMMMC_SHARED_VIRT_RESET_REQ_BASE_IDX 1 +#define regMMMC_VM_CACHEABLE_DRAM_ADDRESS_START 0x0712 +#define regMMMC_VM_CACHEABLE_DRAM_ADDRESS_START_BASE_IDX 1 +#define regMMMC_VM_CACHEABLE_DRAM_ADDRESS_END 0x0713 +#define regMMMC_VM_CACHEABLE_DRAM_ADDRESS_END_BASE_IDX 1 +#define regMMMC_VM_LOCAL_SYSMEM_ADDRESS_START 0x0714 +#define regMMMC_VM_LOCAL_SYSMEM_ADDRESS_START_BASE_IDX 1 +#define regMMMC_VM_LOCAL_SYSMEM_ADDRESS_END 0x0715 +#define regMMMC_VM_LOCAL_SYSMEM_ADDRESS_END_BASE_IDX 1 +#define regMMMC_VM_APT_CNTL 0x0718 +#define regMMMC_VM_APT_CNTL_BASE_IDX 1 +#define regMMUTCL2_HARVEST_BYPASS_GROUPS 0x0719 +#define regMMUTCL2_HARVEST_BYPASS_GROUPS_BASE_IDX 1 + + +// addressBlock: mmhub_mmutcl2_mmatcl2hvdec +// base address: 0x69e10 +#define regMM_ATC_L2_CNTL 0x0784 +#define regMM_ATC_L2_CNTL_BASE_IDX 1 +#define regMM_ATC_L2_CNTL2 0x0785 +#define regMM_ATC_L2_CNTL2_BASE_IDX 1 +#define regMM_ATC_L2_CACHE_DATA0 0x0788 +#define regMM_ATC_L2_CACHE_DATA0_BASE_IDX 1 +#define regMM_ATC_L2_CACHE_DATA1 0x0789 +#define regMM_ATC_L2_CACHE_DATA1_BASE_IDX 1 +#define regMM_ATC_L2_CACHE_DATA2 0x078a +#define regMM_ATC_L2_CACHE_DATA2_BASE_IDX 1 +#define regMM_ATC_L2_CNTL3 0x078c +#define regMM_ATC_L2_CNTL3_BASE_IDX 1 +#define regMM_ATC_L2_CNTL4 0x078d +#define regMM_ATC_L2_CNTL4_BASE_IDX 1 +#define regMM_ATC_L2_CNTL5 0x078e +#define regMM_ATC_L2_CNTL5_BASE_IDX 1 +#define regMM_ATC_L2_MM_GROUP_RT_CLASSES 0x078f +#define regMM_ATC_L2_MM_GROUP_RT_CLASSES_BASE_IDX 1 +#define regMM_ATC_L2_STATUS 0x0790 +#define regMM_ATC_L2_STATUS_BASE_IDX 1 +#define regMM_ATC_L2_MISC_CG 0x0791 +#define regMM_ATC_L2_MISC_CG_BASE_IDX 1 +#define regMM_ATC_L2_CGTT_CLK_CTRL 0x0792 +#define regMM_ATC_L2_CGTT_CLK_CTRL_BASE_IDX 1 +#define regMM_ATC_L2_SDPPORT_CTRL 0x0796 +#define regMM_ATC_L2_SDPPORT_CTRL_BASE_IDX 1 + + +// addressBlock: mmhub_mmutcl2_mmvml2pspdec +// base address: 0x69f20 +#define regMMUTCL2_TRANSLATION_BYPASS_BY_VMID 0x07c8 +#define regMMUTCL2_TRANSLATION_BYPASS_BY_VMID_BASE_IDX 1 +#define regMMVM_IOMMU_GPU_HOST_TRANSLATION_ENABLE 0x07ca +#define regMMVM_IOMMU_GPU_HOST_TRANSLATION_ENABLE_BASE_IDX 1 +#define regMMUTC_GPUVA_VMID_TRANSLATION_ASSIST_CNTL 0x07cb +#define regMMUTC_GPUVA_VMID_TRANSLATION_ASSIST_CNTL_BASE_IDX 1 +#define regMMVM_IOMMU_CONTROL_REGISTER 0x07cc +#define regMMVM_IOMMU_CONTROL_REGISTER_BASE_IDX 1 +#define regMMVM_IOMMU_PERFORMANCE_OPTIMIZATION_CONTROL_REGISTER 0x07cd +#define regMMVM_IOMMU_PERFORMANCE_OPTIMIZATION_CONTROL_REGISTER_BASE_IDX 1 +#define regMMUTC_TRANSLATION_FAULT_CNTL0 0x07ce +#define regMMUTC_TRANSLATION_FAULT_CNTL0_BASE_IDX 1 +#define regMMUTC_TRANSLATION_FAULT_CNTL1 0x07cf +#define regMMUTC_TRANSLATION_FAULT_CNTL1_BASE_IDX 1 +#define regMMUTCL2_FFBM_ENABLE_CNTL 0x07d0 +#define regMMUTCL2_FFBM_ENABLE_CNTL_BASE_IDX 1 +#define regMMUTCL2_VSCH_POWER_STATUS 0x07d1 +#define regMMUTCL2_VSCH_POWER_STATUS_BASE_IDX 1 + + +// addressBlock: mmhub_mmutcl2_mmvmsharedpspdec +// base address: 0x69f90 +#define regMMMC_VM_FB_SIZE_OFFSET_VF0 0x07e4 +#define regMMMC_VM_FB_SIZE_OFFSET_VF0_BASE_IDX 1 +#define regMMMC_VM_FB_SIZE_OFFSET_VF1 0x07e5 +#define regMMMC_VM_FB_SIZE_OFFSET_VF1_BASE_IDX 1 +#define regMMMC_VM_FB_SIZE_OFFSET_VF2 0x07e6 +#define regMMMC_VM_FB_SIZE_OFFSET_VF2_BASE_IDX 1 +#define regMMMC_VM_FB_SIZE_OFFSET_VF3 0x07e7 +#define regMMMC_VM_FB_SIZE_OFFSET_VF3_BASE_IDX 1 +#define regMMMC_VM_FB_SIZE_OFFSET_VF4 0x07e8 +#define regMMMC_VM_FB_SIZE_OFFSET_VF4_BASE_IDX 1 +#define regMMMC_VM_FB_SIZE_OFFSET_VF5 0x07e9 +#define regMMMC_VM_FB_SIZE_OFFSET_VF5_BASE_IDX 1 +#define regMMMC_VM_FB_SIZE_OFFSET_VF6 0x07ea +#define regMMMC_VM_FB_SIZE_OFFSET_VF6_BASE_IDX 1 +#define regMMMC_VM_FB_SIZE_OFFSET_VF7 0x07eb +#define regMMMC_VM_FB_SIZE_OFFSET_VF7_BASE_IDX 1 +#define regMMMC_VM_FB_SIZE_OFFSET_VF8 0x07ec +#define regMMMC_VM_FB_SIZE_OFFSET_VF8_BASE_IDX 1 +#define regMMMC_VM_FB_SIZE_OFFSET_VF9 0x07ed +#define regMMMC_VM_FB_SIZE_OFFSET_VF9_BASE_IDX 1 +#define regMMMC_VM_FB_SIZE_OFFSET_VF10 0x07ee +#define regMMMC_VM_FB_SIZE_OFFSET_VF10_BASE_IDX 1 +#define regMMMC_VM_FB_SIZE_OFFSET_VF11 0x07ef +#define regMMMC_VM_FB_SIZE_OFFSET_VF11_BASE_IDX 1 +#define regMMMC_VM_FB_SIZE_OFFSET_VF12 0x07f0 +#define regMMMC_VM_FB_SIZE_OFFSET_VF12_BASE_IDX 1 +#define regMMMC_VM_FB_SIZE_OFFSET_VF13 0x07f1 +#define regMMMC_VM_FB_SIZE_OFFSET_VF13_BASE_IDX 1 +#define regMMMC_VM_FB_SIZE_OFFSET_VF14 0x07f2 +#define regMMMC_VM_FB_SIZE_OFFSET_VF14_BASE_IDX 1 +#define regMMMC_VM_FB_SIZE_OFFSET_VF15 0x07f3 +#define regMMMC_VM_FB_SIZE_OFFSET_VF15_BASE_IDX 1 +#define regMMMC_VM_FB_SIZE_OFFSET_VF16 0x07f4 +#define regMMMC_VM_FB_SIZE_OFFSET_VF16_BASE_IDX 1 +#define regMMMC_VM_FB_SIZE_OFFSET_VF17 0x07f5 +#define regMMMC_VM_FB_SIZE_OFFSET_VF17_BASE_IDX 1 +#define regMMMC_VM_FB_SIZE_OFFSET_VF18 0x07f6 +#define regMMMC_VM_FB_SIZE_OFFSET_VF18_BASE_IDX 1 +#define regMMMC_VM_FB_SIZE_OFFSET_VF19 0x07f7 +#define regMMMC_VM_FB_SIZE_OFFSET_VF19_BASE_IDX 1 +#define regMMMC_VM_FB_SIZE_OFFSET_VF20 0x07f8 +#define regMMMC_VM_FB_SIZE_OFFSET_VF20_BASE_IDX 1 +#define regMMMC_VM_FB_SIZE_OFFSET_VF21 0x07f9 +#define regMMMC_VM_FB_SIZE_OFFSET_VF21_BASE_IDX 1 +#define regMMMC_VM_FB_SIZE_OFFSET_VF22 0x07fa +#define regMMMC_VM_FB_SIZE_OFFSET_VF22_BASE_IDX 1 +#define regMMMC_VM_FB_SIZE_OFFSET_VF23 0x07fb +#define regMMMC_VM_FB_SIZE_OFFSET_VF23_BASE_IDX 1 +#define regMMMC_VM_FB_SIZE_OFFSET_VF24 0x07fc +#define regMMMC_VM_FB_SIZE_OFFSET_VF24_BASE_IDX 1 +#define regMMMC_VM_FB_SIZE_OFFSET_VF25 0x07fd +#define regMMMC_VM_FB_SIZE_OFFSET_VF25_BASE_IDX 1 +#define regMMMC_VM_FB_SIZE_OFFSET_VF26 0x07fe +#define regMMMC_VM_FB_SIZE_OFFSET_VF26_BASE_IDX 1 +#define regMMMC_VM_FB_SIZE_OFFSET_VF27 0x07ff +#define regMMMC_VM_FB_SIZE_OFFSET_VF27_BASE_IDX 1 +#define regMMMC_VM_FB_SIZE_OFFSET_VF28 0x0800 +#define regMMMC_VM_FB_SIZE_OFFSET_VF28_BASE_IDX 1 +#define regMMMC_VM_FB_SIZE_OFFSET_VF29 0x0801 +#define regMMMC_VM_FB_SIZE_OFFSET_VF29_BASE_IDX 1 +#define regMMMC_VM_FB_SIZE_OFFSET_VF30 0x0802 +#define regMMMC_VM_FB_SIZE_OFFSET_VF30_BASE_IDX 1 #define regMMMC_VM_FB_OFFSET 0x0803 #define regMMMC_VM_FB_OFFSET_BASE_IDX 1 +#define regMMMC_VM_LOCAL_FB_ADDRESS_START 0x0804 +#define regMMMC_VM_LOCAL_FB_ADDRESS_START_BASE_IDX 1 +#define regMMMC_VM_LOCAL_FB_ADDRESS_END 0x0805 +#define regMMMC_VM_LOCAL_FB_ADDRESS_END_BASE_IDX 1 +#define regMMMC_VM_LOCAL_FB_ADDRESS_LOCK_CNTL 0x0806 +#define regMMMC_VM_LOCAL_FB_ADDRESS_LOCK_CNTL_BASE_IDX 1 + + +// addressBlock: mmhub_mmutcl2_mmutcl2ffbmpspdec +// base address: 0x6a080 +#define regMMUTCL2_FFBM_CONFIG 0x0821 +#define regMMUTCL2_FFBM_CONFIG_BASE_IDX 1 +#define regMMUTCL2_FFBM_ACCESS_CNTL 0x0822 +#define regMMUTCL2_FFBM_ACCESS_CNTL_BASE_IDX 1 +#define regMMUTCL2_FFBM_INVALIDATE_RESPONSE 0x0829 +#define regMMUTCL2_FFBM_INVALIDATE_RESPONSE_BASE_IDX 1 + #endif diff --git a/drivers/gpu/drm/amd/include/asic_reg/mmhub/mmhub_5_0_1_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/mmhub/mmhub_5_0_1_sh_mask.h index 0da2bbc4996a..6d149fe2e91c 100644 --- a/drivers/gpu/drm/amd/include/asic_reg/mmhub/mmhub_5_0_1_sh_mask.h +++ b/drivers/gpu/drm/amd/include/asic_reg/mmhub/mmhub_5_0_1_sh_mask.h @@ -1,17 +1,7500 @@ /* - * SPDX-License-Identifier: MIT + * Copyright 2026 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. * - * Copyright (c) 2026 Advanced Micro Devices, Inc. All rights reserved. */ - #ifndef _mmhub_5_0_1_SH_MASK_HEADER #define _mmhub_5_0_1_SH_MASK_HEADER + +// addressBlock: mmhub_dagb_dagbdec +//DAGB0_RDCLI0 +#define DAGB0_RDCLI0__TC__SHIFT 0x0 +#define DAGB0_RDCLI0__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB0_RDCLI0__PRIORITY_ARB1__SHIFT 0x4 +#define DAGB0_RDCLI0__PROFILE_ARB2__SHIFT 0x8 +#define DAGB0_RDCLI0__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB0_RDCLI0__MAX_BW__SHIFT 0xd +#define DAGB0_RDCLI0__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB0_RDCLI0__MIN_BW__SHIFT 0x16 +#define DAGB0_RDCLI0__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB0_RDCLI0__MAX_OSD__SHIFT 0x1a +#define DAGB0_RDCLI0__TC_MASK 0x00000007L +#define DAGB0_RDCLI0__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB0_RDCLI0__PRIORITY_ARB1_MASK 0x000000F0L +#define DAGB0_RDCLI0__PROFILE_ARB2_MASK 0x00000700L +#define DAGB0_RDCLI0__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB0_RDCLI0__MAX_BW_MASK 0x001FE000L +#define DAGB0_RDCLI0__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB0_RDCLI0__MIN_BW_MASK 0x01C00000L +#define DAGB0_RDCLI0__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB0_RDCLI0__MAX_OSD_MASK 0xFC000000L +//DAGB0_RDCLI1 +#define DAGB0_RDCLI1__TC__SHIFT 0x0 +#define DAGB0_RDCLI1__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB0_RDCLI1__PRIORITY_ARB1__SHIFT 0x4 +#define DAGB0_RDCLI1__PROFILE_ARB2__SHIFT 0x8 +#define DAGB0_RDCLI1__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB0_RDCLI1__MAX_BW__SHIFT 0xd +#define DAGB0_RDCLI1__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB0_RDCLI1__MIN_BW__SHIFT 0x16 +#define DAGB0_RDCLI1__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB0_RDCLI1__MAX_OSD__SHIFT 0x1a +#define DAGB0_RDCLI1__TC_MASK 0x00000007L +#define DAGB0_RDCLI1__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB0_RDCLI1__PRIORITY_ARB1_MASK 0x000000F0L +#define DAGB0_RDCLI1__PROFILE_ARB2_MASK 0x00000700L +#define DAGB0_RDCLI1__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB0_RDCLI1__MAX_BW_MASK 0x001FE000L +#define DAGB0_RDCLI1__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB0_RDCLI1__MIN_BW_MASK 0x01C00000L +#define DAGB0_RDCLI1__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB0_RDCLI1__MAX_OSD_MASK 0xFC000000L +//DAGB0_RDCLI2 +#define DAGB0_RDCLI2__TC__SHIFT 0x0 +#define DAGB0_RDCLI2__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB0_RDCLI2__PRIORITY_ARB1__SHIFT 0x4 +#define DAGB0_RDCLI2__PROFILE_ARB2__SHIFT 0x8 +#define DAGB0_RDCLI2__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB0_RDCLI2__MAX_BW__SHIFT 0xd +#define DAGB0_RDCLI2__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB0_RDCLI2__MIN_BW__SHIFT 0x16 +#define DAGB0_RDCLI2__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB0_RDCLI2__MAX_OSD__SHIFT 0x1a +#define DAGB0_RDCLI2__TC_MASK 0x00000007L +#define DAGB0_RDCLI2__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB0_RDCLI2__PRIORITY_ARB1_MASK 0x000000F0L +#define DAGB0_RDCLI2__PROFILE_ARB2_MASK 0x00000700L +#define DAGB0_RDCLI2__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB0_RDCLI2__MAX_BW_MASK 0x001FE000L +#define DAGB0_RDCLI2__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB0_RDCLI2__MIN_BW_MASK 0x01C00000L +#define DAGB0_RDCLI2__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB0_RDCLI2__MAX_OSD_MASK 0xFC000000L +//DAGB0_RDCLI3 +#define DAGB0_RDCLI3__TC__SHIFT 0x0 +#define DAGB0_RDCLI3__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB0_RDCLI3__PRIORITY_ARB1__SHIFT 0x4 +#define DAGB0_RDCLI3__PROFILE_ARB2__SHIFT 0x8 +#define DAGB0_RDCLI3__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB0_RDCLI3__MAX_BW__SHIFT 0xd +#define DAGB0_RDCLI3__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB0_RDCLI3__MIN_BW__SHIFT 0x16 +#define DAGB0_RDCLI3__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB0_RDCLI3__MAX_OSD__SHIFT 0x1a +#define DAGB0_RDCLI3__TC_MASK 0x00000007L +#define DAGB0_RDCLI3__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB0_RDCLI3__PRIORITY_ARB1_MASK 0x000000F0L +#define DAGB0_RDCLI3__PROFILE_ARB2_MASK 0x00000700L +#define DAGB0_RDCLI3__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB0_RDCLI3__MAX_BW_MASK 0x001FE000L +#define DAGB0_RDCLI3__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB0_RDCLI3__MIN_BW_MASK 0x01C00000L +#define DAGB0_RDCLI3__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB0_RDCLI3__MAX_OSD_MASK 0xFC000000L +//DAGB0_RDCLI4 +#define DAGB0_RDCLI4__TC__SHIFT 0x0 +#define DAGB0_RDCLI4__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB0_RDCLI4__PRIORITY_ARB1__SHIFT 0x4 +#define DAGB0_RDCLI4__PROFILE_ARB2__SHIFT 0x8 +#define DAGB0_RDCLI4__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB0_RDCLI4__MAX_BW__SHIFT 0xd +#define DAGB0_RDCLI4__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB0_RDCLI4__MIN_BW__SHIFT 0x16 +#define DAGB0_RDCLI4__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB0_RDCLI4__MAX_OSD__SHIFT 0x1a +#define DAGB0_RDCLI4__TC_MASK 0x00000007L +#define DAGB0_RDCLI4__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB0_RDCLI4__PRIORITY_ARB1_MASK 0x000000F0L +#define DAGB0_RDCLI4__PROFILE_ARB2_MASK 0x00000700L +#define DAGB0_RDCLI4__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB0_RDCLI4__MAX_BW_MASK 0x001FE000L +#define DAGB0_RDCLI4__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB0_RDCLI4__MIN_BW_MASK 0x01C00000L +#define DAGB0_RDCLI4__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB0_RDCLI4__MAX_OSD_MASK 0xFC000000L +//DAGB0_RDCLI5 +#define DAGB0_RDCLI5__TC__SHIFT 0x0 +#define DAGB0_RDCLI5__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB0_RDCLI5__PRIORITY_ARB1__SHIFT 0x4 +#define DAGB0_RDCLI5__PROFILE_ARB2__SHIFT 0x8 +#define DAGB0_RDCLI5__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB0_RDCLI5__MAX_BW__SHIFT 0xd +#define DAGB0_RDCLI5__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB0_RDCLI5__MIN_BW__SHIFT 0x16 +#define DAGB0_RDCLI5__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB0_RDCLI5__MAX_OSD__SHIFT 0x1a +#define DAGB0_RDCLI5__TC_MASK 0x00000007L +#define DAGB0_RDCLI5__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB0_RDCLI5__PRIORITY_ARB1_MASK 0x000000F0L +#define DAGB0_RDCLI5__PROFILE_ARB2_MASK 0x00000700L +#define DAGB0_RDCLI5__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB0_RDCLI5__MAX_BW_MASK 0x001FE000L +#define DAGB0_RDCLI5__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB0_RDCLI5__MIN_BW_MASK 0x01C00000L +#define DAGB0_RDCLI5__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB0_RDCLI5__MAX_OSD_MASK 0xFC000000L +//DAGB0_RDCLI6 +#define DAGB0_RDCLI6__TC__SHIFT 0x0 +#define DAGB0_RDCLI6__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB0_RDCLI6__PRIORITY_ARB1__SHIFT 0x4 +#define DAGB0_RDCLI6__PROFILE_ARB2__SHIFT 0x8 +#define DAGB0_RDCLI6__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB0_RDCLI6__MAX_BW__SHIFT 0xd +#define DAGB0_RDCLI6__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB0_RDCLI6__MIN_BW__SHIFT 0x16 +#define DAGB0_RDCLI6__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB0_RDCLI6__MAX_OSD__SHIFT 0x1a +#define DAGB0_RDCLI6__TC_MASK 0x00000007L +#define DAGB0_RDCLI6__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB0_RDCLI6__PRIORITY_ARB1_MASK 0x000000F0L +#define DAGB0_RDCLI6__PROFILE_ARB2_MASK 0x00000700L +#define DAGB0_RDCLI6__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB0_RDCLI6__MAX_BW_MASK 0x001FE000L +#define DAGB0_RDCLI6__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB0_RDCLI6__MIN_BW_MASK 0x01C00000L +#define DAGB0_RDCLI6__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB0_RDCLI6__MAX_OSD_MASK 0xFC000000L +//DAGB0_RDCLI7 +#define DAGB0_RDCLI7__TC__SHIFT 0x0 +#define DAGB0_RDCLI7__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB0_RDCLI7__PRIORITY_ARB1__SHIFT 0x4 +#define DAGB0_RDCLI7__PROFILE_ARB2__SHIFT 0x8 +#define DAGB0_RDCLI7__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB0_RDCLI7__MAX_BW__SHIFT 0xd +#define DAGB0_RDCLI7__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB0_RDCLI7__MIN_BW__SHIFT 0x16 +#define DAGB0_RDCLI7__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB0_RDCLI7__MAX_OSD__SHIFT 0x1a +#define DAGB0_RDCLI7__TC_MASK 0x00000007L +#define DAGB0_RDCLI7__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB0_RDCLI7__PRIORITY_ARB1_MASK 0x000000F0L +#define DAGB0_RDCLI7__PROFILE_ARB2_MASK 0x00000700L +#define DAGB0_RDCLI7__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB0_RDCLI7__MAX_BW_MASK 0x001FE000L +#define DAGB0_RDCLI7__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB0_RDCLI7__MIN_BW_MASK 0x01C00000L +#define DAGB0_RDCLI7__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB0_RDCLI7__MAX_OSD_MASK 0xFC000000L +//DAGB0_RDCLI8 +#define DAGB0_RDCLI8__TC__SHIFT 0x0 +#define DAGB0_RDCLI8__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB0_RDCLI8__PRIORITY_ARB1__SHIFT 0x4 +#define DAGB0_RDCLI8__PROFILE_ARB2__SHIFT 0x8 +#define DAGB0_RDCLI8__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB0_RDCLI8__MAX_BW__SHIFT 0xd +#define DAGB0_RDCLI8__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB0_RDCLI8__MIN_BW__SHIFT 0x16 +#define DAGB0_RDCLI8__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB0_RDCLI8__MAX_OSD__SHIFT 0x1a +#define DAGB0_RDCLI8__TC_MASK 0x00000007L +#define DAGB0_RDCLI8__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB0_RDCLI8__PRIORITY_ARB1_MASK 0x000000F0L +#define DAGB0_RDCLI8__PROFILE_ARB2_MASK 0x00000700L +#define DAGB0_RDCLI8__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB0_RDCLI8__MAX_BW_MASK 0x001FE000L +#define DAGB0_RDCLI8__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB0_RDCLI8__MIN_BW_MASK 0x01C00000L +#define DAGB0_RDCLI8__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB0_RDCLI8__MAX_OSD_MASK 0xFC000000L +//DAGB0_RDCLI9 +#define DAGB0_RDCLI9__TC__SHIFT 0x0 +#define DAGB0_RDCLI9__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB0_RDCLI9__PRIORITY_ARB1__SHIFT 0x4 +#define DAGB0_RDCLI9__PROFILE_ARB2__SHIFT 0x8 +#define DAGB0_RDCLI9__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB0_RDCLI9__MAX_BW__SHIFT 0xd +#define DAGB0_RDCLI9__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB0_RDCLI9__MIN_BW__SHIFT 0x16 +#define DAGB0_RDCLI9__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB0_RDCLI9__MAX_OSD__SHIFT 0x1a +#define DAGB0_RDCLI9__TC_MASK 0x00000007L +#define DAGB0_RDCLI9__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB0_RDCLI9__PRIORITY_ARB1_MASK 0x000000F0L +#define DAGB0_RDCLI9__PROFILE_ARB2_MASK 0x00000700L +#define DAGB0_RDCLI9__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB0_RDCLI9__MAX_BW_MASK 0x001FE000L +#define DAGB0_RDCLI9__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB0_RDCLI9__MIN_BW_MASK 0x01C00000L +#define DAGB0_RDCLI9__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB0_RDCLI9__MAX_OSD_MASK 0xFC000000L +//DAGB0_RDCLI10 +#define DAGB0_RDCLI10__TC__SHIFT 0x0 +#define DAGB0_RDCLI10__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB0_RDCLI10__PRIORITY_ARB1__SHIFT 0x4 +#define DAGB0_RDCLI10__PROFILE_ARB2__SHIFT 0x8 +#define DAGB0_RDCLI10__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB0_RDCLI10__MAX_BW__SHIFT 0xd +#define DAGB0_RDCLI10__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB0_RDCLI10__MIN_BW__SHIFT 0x16 +#define DAGB0_RDCLI10__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB0_RDCLI10__MAX_OSD__SHIFT 0x1a +#define DAGB0_RDCLI10__TC_MASK 0x00000007L +#define DAGB0_RDCLI10__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB0_RDCLI10__PRIORITY_ARB1_MASK 0x000000F0L +#define DAGB0_RDCLI10__PROFILE_ARB2_MASK 0x00000700L +#define DAGB0_RDCLI10__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB0_RDCLI10__MAX_BW_MASK 0x001FE000L +#define DAGB0_RDCLI10__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB0_RDCLI10__MIN_BW_MASK 0x01C00000L +#define DAGB0_RDCLI10__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB0_RDCLI10__MAX_OSD_MASK 0xFC000000L +//DAGB0_RDCLI11 +#define DAGB0_RDCLI11__TC__SHIFT 0x0 +#define DAGB0_RDCLI11__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB0_RDCLI11__PRIORITY_ARB1__SHIFT 0x4 +#define DAGB0_RDCLI11__PROFILE_ARB2__SHIFT 0x8 +#define DAGB0_RDCLI11__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB0_RDCLI11__MAX_BW__SHIFT 0xd +#define DAGB0_RDCLI11__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB0_RDCLI11__MIN_BW__SHIFT 0x16 +#define DAGB0_RDCLI11__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB0_RDCLI11__MAX_OSD__SHIFT 0x1a +#define DAGB0_RDCLI11__TC_MASK 0x00000007L +#define DAGB0_RDCLI11__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB0_RDCLI11__PRIORITY_ARB1_MASK 0x000000F0L +#define DAGB0_RDCLI11__PROFILE_ARB2_MASK 0x00000700L +#define DAGB0_RDCLI11__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB0_RDCLI11__MAX_BW_MASK 0x001FE000L +#define DAGB0_RDCLI11__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB0_RDCLI11__MIN_BW_MASK 0x01C00000L +#define DAGB0_RDCLI11__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB0_RDCLI11__MAX_OSD_MASK 0xFC000000L +//DAGB0_RDCLI12 +#define DAGB0_RDCLI12__TC__SHIFT 0x0 +#define DAGB0_RDCLI12__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB0_RDCLI12__PRIORITY_ARB1__SHIFT 0x4 +#define DAGB0_RDCLI12__PROFILE_ARB2__SHIFT 0x8 +#define DAGB0_RDCLI12__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB0_RDCLI12__MAX_BW__SHIFT 0xd +#define DAGB0_RDCLI12__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB0_RDCLI12__MIN_BW__SHIFT 0x16 +#define DAGB0_RDCLI12__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB0_RDCLI12__MAX_OSD__SHIFT 0x1a +#define DAGB0_RDCLI12__TC_MASK 0x00000007L +#define DAGB0_RDCLI12__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB0_RDCLI12__PRIORITY_ARB1_MASK 0x000000F0L +#define DAGB0_RDCLI12__PROFILE_ARB2_MASK 0x00000700L +#define DAGB0_RDCLI12__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB0_RDCLI12__MAX_BW_MASK 0x001FE000L +#define DAGB0_RDCLI12__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB0_RDCLI12__MIN_BW_MASK 0x01C00000L +#define DAGB0_RDCLI12__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB0_RDCLI12__MAX_OSD_MASK 0xFC000000L +//DAGB0_RDCLI13 +#define DAGB0_RDCLI13__TC__SHIFT 0x0 +#define DAGB0_RDCLI13__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB0_RDCLI13__PRIORITY_ARB1__SHIFT 0x4 +#define DAGB0_RDCLI13__PROFILE_ARB2__SHIFT 0x8 +#define DAGB0_RDCLI13__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB0_RDCLI13__MAX_BW__SHIFT 0xd +#define DAGB0_RDCLI13__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB0_RDCLI13__MIN_BW__SHIFT 0x16 +#define DAGB0_RDCLI13__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB0_RDCLI13__MAX_OSD__SHIFT 0x1a +#define DAGB0_RDCLI13__TC_MASK 0x00000007L +#define DAGB0_RDCLI13__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB0_RDCLI13__PRIORITY_ARB1_MASK 0x000000F0L +#define DAGB0_RDCLI13__PROFILE_ARB2_MASK 0x00000700L +#define DAGB0_RDCLI13__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB0_RDCLI13__MAX_BW_MASK 0x001FE000L +#define DAGB0_RDCLI13__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB0_RDCLI13__MIN_BW_MASK 0x01C00000L +#define DAGB0_RDCLI13__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB0_RDCLI13__MAX_OSD_MASK 0xFC000000L +//DAGB0_RDCLI14 +#define DAGB0_RDCLI14__TC__SHIFT 0x0 +#define DAGB0_RDCLI14__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB0_RDCLI14__PRIORITY_ARB1__SHIFT 0x4 +#define DAGB0_RDCLI14__PROFILE_ARB2__SHIFT 0x8 +#define DAGB0_RDCLI14__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB0_RDCLI14__MAX_BW__SHIFT 0xd +#define DAGB0_RDCLI14__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB0_RDCLI14__MIN_BW__SHIFT 0x16 +#define DAGB0_RDCLI14__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB0_RDCLI14__MAX_OSD__SHIFT 0x1a +#define DAGB0_RDCLI14__TC_MASK 0x00000007L +#define DAGB0_RDCLI14__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB0_RDCLI14__PRIORITY_ARB1_MASK 0x000000F0L +#define DAGB0_RDCLI14__PROFILE_ARB2_MASK 0x00000700L +#define DAGB0_RDCLI14__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB0_RDCLI14__MAX_BW_MASK 0x001FE000L +#define DAGB0_RDCLI14__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB0_RDCLI14__MIN_BW_MASK 0x01C00000L +#define DAGB0_RDCLI14__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB0_RDCLI14__MAX_OSD_MASK 0xFC000000L +//DAGB0_RDCLI15 +#define DAGB0_RDCLI15__TC__SHIFT 0x0 +#define DAGB0_RDCLI15__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB0_RDCLI15__PRIORITY_ARB1__SHIFT 0x4 +#define DAGB0_RDCLI15__PROFILE_ARB2__SHIFT 0x8 +#define DAGB0_RDCLI15__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB0_RDCLI15__MAX_BW__SHIFT 0xd +#define DAGB0_RDCLI15__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB0_RDCLI15__MIN_BW__SHIFT 0x16 +#define DAGB0_RDCLI15__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB0_RDCLI15__MAX_OSD__SHIFT 0x1a +#define DAGB0_RDCLI15__TC_MASK 0x00000007L +#define DAGB0_RDCLI15__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB0_RDCLI15__PRIORITY_ARB1_MASK 0x000000F0L +#define DAGB0_RDCLI15__PROFILE_ARB2_MASK 0x00000700L +#define DAGB0_RDCLI15__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB0_RDCLI15__MAX_BW_MASK 0x001FE000L +#define DAGB0_RDCLI15__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB0_RDCLI15__MIN_BW_MASK 0x01C00000L +#define DAGB0_RDCLI15__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB0_RDCLI15__MAX_OSD_MASK 0xFC000000L +//DAGB0_RDCLI16 +#define DAGB0_RDCLI16__TC__SHIFT 0x0 +#define DAGB0_RDCLI16__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB0_RDCLI16__PRIORITY_ARB1__SHIFT 0x4 +#define DAGB0_RDCLI16__PROFILE_ARB2__SHIFT 0x8 +#define DAGB0_RDCLI16__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB0_RDCLI16__MAX_BW__SHIFT 0xd +#define DAGB0_RDCLI16__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB0_RDCLI16__MIN_BW__SHIFT 0x16 +#define DAGB0_RDCLI16__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB0_RDCLI16__MAX_OSD__SHIFT 0x1a +#define DAGB0_RDCLI16__TC_MASK 0x00000007L +#define DAGB0_RDCLI16__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB0_RDCLI16__PRIORITY_ARB1_MASK 0x000000F0L +#define DAGB0_RDCLI16__PROFILE_ARB2_MASK 0x00000700L +#define DAGB0_RDCLI16__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB0_RDCLI16__MAX_BW_MASK 0x001FE000L +#define DAGB0_RDCLI16__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB0_RDCLI16__MIN_BW_MASK 0x01C00000L +#define DAGB0_RDCLI16__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB0_RDCLI16__MAX_OSD_MASK 0xFC000000L +//DAGB0_RDCLI17 +#define DAGB0_RDCLI17__TC__SHIFT 0x0 +#define DAGB0_RDCLI17__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB0_RDCLI17__PRIORITY_ARB1__SHIFT 0x4 +#define DAGB0_RDCLI17__PROFILE_ARB2__SHIFT 0x8 +#define DAGB0_RDCLI17__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB0_RDCLI17__MAX_BW__SHIFT 0xd +#define DAGB0_RDCLI17__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB0_RDCLI17__MIN_BW__SHIFT 0x16 +#define DAGB0_RDCLI17__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB0_RDCLI17__MAX_OSD__SHIFT 0x1a +#define DAGB0_RDCLI17__TC_MASK 0x00000007L +#define DAGB0_RDCLI17__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB0_RDCLI17__PRIORITY_ARB1_MASK 0x000000F0L +#define DAGB0_RDCLI17__PROFILE_ARB2_MASK 0x00000700L +#define DAGB0_RDCLI17__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB0_RDCLI17__MAX_BW_MASK 0x001FE000L +#define DAGB0_RDCLI17__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB0_RDCLI17__MIN_BW_MASK 0x01C00000L +#define DAGB0_RDCLI17__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB0_RDCLI17__MAX_OSD_MASK 0xFC000000L +//DAGB0_RDCLI18 +#define DAGB0_RDCLI18__TC__SHIFT 0x0 +#define DAGB0_RDCLI18__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB0_RDCLI18__PRIORITY_ARB1__SHIFT 0x4 +#define DAGB0_RDCLI18__PROFILE_ARB2__SHIFT 0x8 +#define DAGB0_RDCLI18__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB0_RDCLI18__MAX_BW__SHIFT 0xd +#define DAGB0_RDCLI18__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB0_RDCLI18__MIN_BW__SHIFT 0x16 +#define DAGB0_RDCLI18__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB0_RDCLI18__MAX_OSD__SHIFT 0x1a +#define DAGB0_RDCLI18__TC_MASK 0x00000007L +#define DAGB0_RDCLI18__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB0_RDCLI18__PRIORITY_ARB1_MASK 0x000000F0L +#define DAGB0_RDCLI18__PROFILE_ARB2_MASK 0x00000700L +#define DAGB0_RDCLI18__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB0_RDCLI18__MAX_BW_MASK 0x001FE000L +#define DAGB0_RDCLI18__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB0_RDCLI18__MIN_BW_MASK 0x01C00000L +#define DAGB0_RDCLI18__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB0_RDCLI18__MAX_OSD_MASK 0xFC000000L +//DAGB0_RDCLI19 +#define DAGB0_RDCLI19__TC__SHIFT 0x0 +#define DAGB0_RDCLI19__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB0_RDCLI19__PRIORITY_ARB1__SHIFT 0x4 +#define DAGB0_RDCLI19__PROFILE_ARB2__SHIFT 0x8 +#define DAGB0_RDCLI19__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB0_RDCLI19__MAX_BW__SHIFT 0xd +#define DAGB0_RDCLI19__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB0_RDCLI19__MIN_BW__SHIFT 0x16 +#define DAGB0_RDCLI19__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB0_RDCLI19__MAX_OSD__SHIFT 0x1a +#define DAGB0_RDCLI19__TC_MASK 0x00000007L +#define DAGB0_RDCLI19__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB0_RDCLI19__PRIORITY_ARB1_MASK 0x000000F0L +#define DAGB0_RDCLI19__PROFILE_ARB2_MASK 0x00000700L +#define DAGB0_RDCLI19__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB0_RDCLI19__MAX_BW_MASK 0x001FE000L +#define DAGB0_RDCLI19__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB0_RDCLI19__MIN_BW_MASK 0x01C00000L +#define DAGB0_RDCLI19__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB0_RDCLI19__MAX_OSD_MASK 0xFC000000L +//DAGB0_RDCLI20 +#define DAGB0_RDCLI20__TC__SHIFT 0x0 +#define DAGB0_RDCLI20__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB0_RDCLI20__PRIORITY_ARB1__SHIFT 0x4 +#define DAGB0_RDCLI20__PROFILE_ARB2__SHIFT 0x8 +#define DAGB0_RDCLI20__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB0_RDCLI20__MAX_BW__SHIFT 0xd +#define DAGB0_RDCLI20__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB0_RDCLI20__MIN_BW__SHIFT 0x16 +#define DAGB0_RDCLI20__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB0_RDCLI20__MAX_OSD__SHIFT 0x1a +#define DAGB0_RDCLI20__TC_MASK 0x00000007L +#define DAGB0_RDCLI20__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB0_RDCLI20__PRIORITY_ARB1_MASK 0x000000F0L +#define DAGB0_RDCLI20__PROFILE_ARB2_MASK 0x00000700L +#define DAGB0_RDCLI20__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB0_RDCLI20__MAX_BW_MASK 0x001FE000L +#define DAGB0_RDCLI20__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB0_RDCLI20__MIN_BW_MASK 0x01C00000L +#define DAGB0_RDCLI20__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB0_RDCLI20__MAX_OSD_MASK 0xFC000000L +//DAGB0_RDCLI21 +#define DAGB0_RDCLI21__TC__SHIFT 0x0 +#define DAGB0_RDCLI21__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB0_RDCLI21__PRIORITY_ARB1__SHIFT 0x4 +#define DAGB0_RDCLI21__PROFILE_ARB2__SHIFT 0x8 +#define DAGB0_RDCLI21__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB0_RDCLI21__MAX_BW__SHIFT 0xd +#define DAGB0_RDCLI21__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB0_RDCLI21__MIN_BW__SHIFT 0x16 +#define DAGB0_RDCLI21__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB0_RDCLI21__MAX_OSD__SHIFT 0x1a +#define DAGB0_RDCLI21__TC_MASK 0x00000007L +#define DAGB0_RDCLI21__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB0_RDCLI21__PRIORITY_ARB1_MASK 0x000000F0L +#define DAGB0_RDCLI21__PROFILE_ARB2_MASK 0x00000700L +#define DAGB0_RDCLI21__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB0_RDCLI21__MAX_BW_MASK 0x001FE000L +#define DAGB0_RDCLI21__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB0_RDCLI21__MIN_BW_MASK 0x01C00000L +#define DAGB0_RDCLI21__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB0_RDCLI21__MAX_OSD_MASK 0xFC000000L +//DAGB0_RDCLI22 +#define DAGB0_RDCLI22__TC__SHIFT 0x0 +#define DAGB0_RDCLI22__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB0_RDCLI22__PRIORITY_ARB1__SHIFT 0x4 +#define DAGB0_RDCLI22__PROFILE_ARB2__SHIFT 0x8 +#define DAGB0_RDCLI22__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB0_RDCLI22__MAX_BW__SHIFT 0xd +#define DAGB0_RDCLI22__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB0_RDCLI22__MIN_BW__SHIFT 0x16 +#define DAGB0_RDCLI22__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB0_RDCLI22__MAX_OSD__SHIFT 0x1a +#define DAGB0_RDCLI22__TC_MASK 0x00000007L +#define DAGB0_RDCLI22__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB0_RDCLI22__PRIORITY_ARB1_MASK 0x000000F0L +#define DAGB0_RDCLI22__PROFILE_ARB2_MASK 0x00000700L +#define DAGB0_RDCLI22__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB0_RDCLI22__MAX_BW_MASK 0x001FE000L +#define DAGB0_RDCLI22__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB0_RDCLI22__MIN_BW_MASK 0x01C00000L +#define DAGB0_RDCLI22__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB0_RDCLI22__MAX_OSD_MASK 0xFC000000L +//DAGB0_RDCLI23 +#define DAGB0_RDCLI23__TC__SHIFT 0x0 +#define DAGB0_RDCLI23__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB0_RDCLI23__PRIORITY_ARB1__SHIFT 0x4 +#define DAGB0_RDCLI23__PROFILE_ARB2__SHIFT 0x8 +#define DAGB0_RDCLI23__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB0_RDCLI23__MAX_BW__SHIFT 0xd +#define DAGB0_RDCLI23__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB0_RDCLI23__MIN_BW__SHIFT 0x16 +#define DAGB0_RDCLI23__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB0_RDCLI23__MAX_OSD__SHIFT 0x1a +#define DAGB0_RDCLI23__TC_MASK 0x00000007L +#define DAGB0_RDCLI23__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB0_RDCLI23__PRIORITY_ARB1_MASK 0x000000F0L +#define DAGB0_RDCLI23__PROFILE_ARB2_MASK 0x00000700L +#define DAGB0_RDCLI23__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB0_RDCLI23__MAX_BW_MASK 0x001FE000L +#define DAGB0_RDCLI23__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB0_RDCLI23__MIN_BW_MASK 0x01C00000L +#define DAGB0_RDCLI23__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB0_RDCLI23__MAX_OSD_MASK 0xFC000000L +//DAGB0_RD_CNTL +#define DAGB0_RD_CNTL__CLI_MAX_BW_WINDOW__SHIFT 0x0 +#define DAGB0_RD_CNTL__MAX_BW_ENABLE__SHIFT 0x9 +#define DAGB0_RD_CNTL__MAX_BW__SHIFT 0xa +#define DAGB0_RD_CNTL__BUSY_HYSTERESIS_64B_CLI__SHIFT 0x15 +#define DAGB0_RD_CNTL__BW_ALARM_BLOCK_BOOST__SHIFT 0x1d +#define DAGB0_RD_CNTL__CLI_MAX_BW_WINDOW_MASK 0x000001FFL +#define DAGB0_RD_CNTL__MAX_BW_ENABLE_MASK 0x00000200L +#define DAGB0_RD_CNTL__MAX_BW_MASK 0x001FFC00L +#define DAGB0_RD_CNTL__BUSY_HYSTERESIS_64B_CLI_MASK 0x1FE00000L +#define DAGB0_RD_CNTL__BW_ALARM_BLOCK_BOOST_MASK 0x20000000L +//DAGB0_RD_ADDR_DAGB +#define DAGB0_RD_ADDR_DAGB__DAGB_ENABLE__SHIFT 0x0 +#define DAGB0_RD_ADDR_DAGB__ENABLE_JUMP_AHEAD__SHIFT 0x4 +#define DAGB0_RD_ADDR_DAGB__DISABLE_SELF_INIT__SHIFT 0x8 +#define DAGB0_RD_ADDR_DAGB__WHOAMI__SHIFT 0x9 +#define DAGB0_RD_ADDR_DAGB__JUMP_MODE__SHIFT 0xf +#define DAGB0_RD_ADDR_DAGB__DAGB_ENABLE_MASK 0x0000000FL +#define DAGB0_RD_ADDR_DAGB__ENABLE_JUMP_AHEAD_MASK 0x000000F0L +#define DAGB0_RD_ADDR_DAGB__DISABLE_SELF_INIT_MASK 0x00000100L +#define DAGB0_RD_ADDR_DAGB__WHOAMI_MASK 0x00007E00L +#define DAGB0_RD_ADDR_DAGB__JUMP_MODE_MASK 0x00008000L +//DAGB0_RD_CGTT_CLK_CTRL +#define DAGB0_RD_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 +#define DAGB0_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x5 +#define DAGB0_RD_CGTT_CLK_CTRL__LS_ASSERT_HYSTERESIS__SHIFT 0xd +#define DAGB0_RD_CGTT_CLK_CTRL__MIN_MGLS__SHIFT 0x1a +#define DAGB0_RD_CGTT_CLK_CTRL__CGLS_DISABLE__SHIFT 0x1d +#define DAGB0_RD_CGTT_CLK_CTRL__LS_DISABLE__SHIFT 0x1e +#define DAGB0_RD_CGTT_CLK_CTRL__BUSY_OVERRIDE__SHIFT 0x1f +#define DAGB0_RD_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000001FL +#define DAGB0_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00001FE0L +#define DAGB0_RD_CGTT_CLK_CTRL__LS_ASSERT_HYSTERESIS_MASK 0x03FFE000L +#define DAGB0_RD_CGTT_CLK_CTRL__MIN_MGLS_MASK 0x1C000000L +#define DAGB0_RD_CGTT_CLK_CTRL__CGLS_DISABLE_MASK 0x20000000L +#define DAGB0_RD_CGTT_CLK_CTRL__LS_DISABLE_MASK 0x40000000L +#define DAGB0_RD_CGTT_CLK_CTRL__BUSY_OVERRIDE_MASK 0x80000000L +//DAGB0_L1TLB_RD_CGTT_CLK_CTRL +#define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 +#define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x5 +#define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__LS_ASSERT_HYSTERESIS__SHIFT 0xd +#define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__MIN_MGLS__SHIFT 0x1a +#define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__CGLS_DISABLE__SHIFT 0x1d +#define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__LS_DISABLE__SHIFT 0x1e +#define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__BUSY_OVERRIDE__SHIFT 0x1f +#define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000001FL +#define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00001FE0L +#define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__LS_ASSERT_HYSTERESIS_MASK 0x03FFE000L +#define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__MIN_MGLS_MASK 0x1C000000L +#define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__CGLS_DISABLE_MASK 0x20000000L +#define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__LS_DISABLE_MASK 0x40000000L +#define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__BUSY_OVERRIDE_MASK 0x80000000L +//DAGB0_RD_ADDR_DAGB_MAX_BURST0 +#define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT0__SHIFT 0x0 +#define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT1__SHIFT 0x4 +#define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT2__SHIFT 0x8 +#define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT3__SHIFT 0xc +#define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT4__SHIFT 0x10 +#define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT5__SHIFT 0x14 +#define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT6__SHIFT 0x18 +#define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT7__SHIFT 0x1c +#define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT0_MASK 0x0000000FL +#define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT1_MASK 0x000000F0L +#define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT2_MASK 0x00000F00L +#define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT3_MASK 0x0000F000L +#define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT4_MASK 0x000F0000L +#define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT5_MASK 0x00F00000L +#define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT6_MASK 0x0F000000L +#define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT7_MASK 0xF0000000L +//DAGB0_RD_ADDR_DAGB_LAZY_TIMER0 +#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT0__SHIFT 0x0 +#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT1__SHIFT 0x4 +#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT2__SHIFT 0x8 +#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT3__SHIFT 0xc +#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT4__SHIFT 0x10 +#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT5__SHIFT 0x14 +#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT6__SHIFT 0x18 +#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT7__SHIFT 0x1c +#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT0_MASK 0x0000000FL +#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT1_MASK 0x000000F0L +#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT2_MASK 0x00000F00L +#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT3_MASK 0x0000F000L +#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT4_MASK 0x000F0000L +#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT5_MASK 0x00F00000L +#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT6_MASK 0x0F000000L +#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT7_MASK 0xF0000000L +//DAGB0_RD_ADDR_DAGB_MAX_BURST1 +#define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT8__SHIFT 0x0 +#define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT9__SHIFT 0x4 +#define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT10__SHIFT 0x8 +#define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT11__SHIFT 0xc +#define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT12__SHIFT 0x10 +#define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT13__SHIFT 0x14 +#define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT14__SHIFT 0x18 +#define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT15__SHIFT 0x1c +#define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT8_MASK 0x0000000FL +#define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT9_MASK 0x000000F0L +#define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT10_MASK 0x00000F00L +#define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT11_MASK 0x0000F000L +#define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT12_MASK 0x000F0000L +#define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT13_MASK 0x00F00000L +#define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT14_MASK 0x0F000000L +#define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT15_MASK 0xF0000000L +//DAGB0_RD_ADDR_DAGB_LAZY_TIMER1 +#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT8__SHIFT 0x0 +#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT9__SHIFT 0x4 +#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT10__SHIFT 0x8 +#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT11__SHIFT 0xc +#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT12__SHIFT 0x10 +#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT13__SHIFT 0x14 +#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT14__SHIFT 0x18 +#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT15__SHIFT 0x1c +#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT8_MASK 0x0000000FL +#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT9_MASK 0x000000F0L +#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT10_MASK 0x00000F00L +#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT11_MASK 0x0000F000L +#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT12_MASK 0x000F0000L +#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT13_MASK 0x00F00000L +#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT14_MASK 0x0F000000L +#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT15_MASK 0xF0000000L +//DAGB0_RD_ADDR_DAGB_MAX_BURST2 +#define DAGB0_RD_ADDR_DAGB_MAX_BURST2__CLIENT16__SHIFT 0x0 +#define DAGB0_RD_ADDR_DAGB_MAX_BURST2__CLIENT17__SHIFT 0x4 +#define DAGB0_RD_ADDR_DAGB_MAX_BURST2__CLIENT18__SHIFT 0x8 +#define DAGB0_RD_ADDR_DAGB_MAX_BURST2__CLIENT19__SHIFT 0xc +#define DAGB0_RD_ADDR_DAGB_MAX_BURST2__CLIENT20__SHIFT 0x10 +#define DAGB0_RD_ADDR_DAGB_MAX_BURST2__CLIENT21__SHIFT 0x14 +#define DAGB0_RD_ADDR_DAGB_MAX_BURST2__CLIENT22__SHIFT 0x18 +#define DAGB0_RD_ADDR_DAGB_MAX_BURST2__CLIENT23__SHIFT 0x1c +#define DAGB0_RD_ADDR_DAGB_MAX_BURST2__CLIENT16_MASK 0x0000000FL +#define DAGB0_RD_ADDR_DAGB_MAX_BURST2__CLIENT17_MASK 0x000000F0L +#define DAGB0_RD_ADDR_DAGB_MAX_BURST2__CLIENT18_MASK 0x00000F00L +#define DAGB0_RD_ADDR_DAGB_MAX_BURST2__CLIENT19_MASK 0x0000F000L +#define DAGB0_RD_ADDR_DAGB_MAX_BURST2__CLIENT20_MASK 0x000F0000L +#define DAGB0_RD_ADDR_DAGB_MAX_BURST2__CLIENT21_MASK 0x00F00000L +#define DAGB0_RD_ADDR_DAGB_MAX_BURST2__CLIENT22_MASK 0x0F000000L +#define DAGB0_RD_ADDR_DAGB_MAX_BURST2__CLIENT23_MASK 0xF0000000L +//DAGB0_RD_ADDR_DAGB_LAZY_TIMER2 +#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT16__SHIFT 0x0 +#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT17__SHIFT 0x4 +#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT18__SHIFT 0x8 +#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT19__SHIFT 0xc +#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT20__SHIFT 0x10 +#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT21__SHIFT 0x14 +#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT22__SHIFT 0x18 +#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT23__SHIFT 0x1c +#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT16_MASK 0x0000000FL +#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT17_MASK 0x000000F0L +#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT18_MASK 0x00000F00L +#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT19_MASK 0x0000F000L +#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT20_MASK 0x000F0000L +#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT21_MASK 0x00F00000L +#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT22_MASK 0x0F000000L +#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT23_MASK 0xF0000000L +//DAGB0_RD_CNTL_MISC +#define DAGB0_RD_CNTL_MISC__UTCL2_VCI__SHIFT 0x6 +#define DAGB0_RD_CNTL_MISC__CLI_SWITCH_MODE__SHIFT 0x9 +#define DAGB0_RD_CNTL_MISC__CREDIT_SWITCH_MODE__SHIFT 0xb +#define DAGB0_RD_CNTL_MISC__BUDGET_SWITCH_MODE__SHIFT 0xd +#define DAGB0_RD_CNTL_MISC__CLI_CLEAN_MODE__SHIFT 0xf +#define DAGB0_RD_CNTL_MISC__UTCL2_VCI_MASK 0x000001C0L +#define DAGB0_RD_CNTL_MISC__CLI_SWITCH_MODE_MASK 0x00000600L +#define DAGB0_RD_CNTL_MISC__CREDIT_SWITCH_MODE_MASK 0x00001800L +#define DAGB0_RD_CNTL_MISC__BUDGET_SWITCH_MODE_MASK 0x00006000L +#define DAGB0_RD_CNTL_MISC__CLI_CLEAN_MODE_MASK 0x00008000L +//DAGB0_RD_TLB_CREDIT +#define DAGB0_RD_TLB_CREDIT__TLB0__SHIFT 0x0 +#define DAGB0_RD_TLB_CREDIT__TLB1__SHIFT 0x5 +#define DAGB0_RD_TLB_CREDIT__TLB2__SHIFT 0xa +#define DAGB0_RD_TLB_CREDIT__TLB3__SHIFT 0xf +#define DAGB0_RD_TLB_CREDIT__TLB0_MASK 0x0000001FL +#define DAGB0_RD_TLB_CREDIT__TLB1_MASK 0x000003E0L +#define DAGB0_RD_TLB_CREDIT__TLB2_MASK 0x00007C00L +#define DAGB0_RD_TLB_CREDIT__TLB3_MASK 0x000F8000L +//DAGB0_RDCLI_ASK_PENDING +#define DAGB0_RDCLI_ASK_PENDING__BUSY__SHIFT 0x0 +#define DAGB0_RDCLI_ASK_PENDING__BUSY_MASK 0x00FFFFFFL +//DAGB0_RDCLI_GO_PENDING +#define DAGB0_RDCLI_GO_PENDING__BUSY__SHIFT 0x0 +#define DAGB0_RDCLI_GO_PENDING__BUSY_MASK 0x00FFFFFFL +//DAGB0_RDCLI_GBLSEND_PENDING +#define DAGB0_RDCLI_GBLSEND_PENDING__BUSY__SHIFT 0x0 +#define DAGB0_RDCLI_GBLSEND_PENDING__BUSY_MASK 0x00FFFFFFL +//DAGB0_RDCLI_TLB_PENDING +#define DAGB0_RDCLI_TLB_PENDING__BUSY__SHIFT 0x0 +#define DAGB0_RDCLI_TLB_PENDING__BUSY_MASK 0x00FFFFFFL +//DAGB0_RDCLI_OARB_PENDING +#define DAGB0_RDCLI_OARB_PENDING__BUSY__SHIFT 0x0 +#define DAGB0_RDCLI_OARB_PENDING__BUSY_MASK 0x00FFFFFFL +//DAGB0_RDCLI_ASK2DF_PENDING +#define DAGB0_RDCLI_ASK2DF_PENDING__NUM__SHIFT 0x0 +#define DAGB0_RDCLI_ASK2DF_PENDING__NUM_MASK 0x0000FFFFL +//DAGB0_RDCLI_OSD_PENDING +#define DAGB0_RDCLI_OSD_PENDING__BUSY__SHIFT 0x0 +#define DAGB0_RDCLI_OSD_PENDING__BUSY_MASK 0x00FFFFFFL +//DAGB0_RDCLI_ASK_OSD_PENDING +#define DAGB0_RDCLI_ASK_OSD_PENDING__BUSY__SHIFT 0x0 +#define DAGB0_RDCLI_ASK_OSD_PENDING__BUSY_MASK 0x00FFFFFFL +//DAGB0_WRCLI0 +#define DAGB0_WRCLI0__TC__SHIFT 0x0 +#define DAGB0_WRCLI0__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB0_WRCLI0__PRIORITY_ARB1__SHIFT 0x4 +#define DAGB0_WRCLI0__PROFILE_ARB2__SHIFT 0x8 +#define DAGB0_WRCLI0__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB0_WRCLI0__MAX_BW__SHIFT 0xd +#define DAGB0_WRCLI0__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB0_WRCLI0__MIN_BW__SHIFT 0x16 +#define DAGB0_WRCLI0__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB0_WRCLI0__MAX_OSD__SHIFT 0x1a +#define DAGB0_WRCLI0__TC_MASK 0x00000007L +#define DAGB0_WRCLI0__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB0_WRCLI0__PRIORITY_ARB1_MASK 0x000000F0L +#define DAGB0_WRCLI0__PROFILE_ARB2_MASK 0x00000700L +#define DAGB0_WRCLI0__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB0_WRCLI0__MAX_BW_MASK 0x001FE000L +#define DAGB0_WRCLI0__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB0_WRCLI0__MIN_BW_MASK 0x01C00000L +#define DAGB0_WRCLI0__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB0_WRCLI0__MAX_OSD_MASK 0xFC000000L +//DAGB0_WRCLI1 +#define DAGB0_WRCLI1__TC__SHIFT 0x0 +#define DAGB0_WRCLI1__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB0_WRCLI1__PRIORITY_ARB1__SHIFT 0x4 +#define DAGB0_WRCLI1__PROFILE_ARB2__SHIFT 0x8 +#define DAGB0_WRCLI1__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB0_WRCLI1__MAX_BW__SHIFT 0xd +#define DAGB0_WRCLI1__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB0_WRCLI1__MIN_BW__SHIFT 0x16 +#define DAGB0_WRCLI1__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB0_WRCLI1__MAX_OSD__SHIFT 0x1a +#define DAGB0_WRCLI1__TC_MASK 0x00000007L +#define DAGB0_WRCLI1__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB0_WRCLI1__PRIORITY_ARB1_MASK 0x000000F0L +#define DAGB0_WRCLI1__PROFILE_ARB2_MASK 0x00000700L +#define DAGB0_WRCLI1__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB0_WRCLI1__MAX_BW_MASK 0x001FE000L +#define DAGB0_WRCLI1__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB0_WRCLI1__MIN_BW_MASK 0x01C00000L +#define DAGB0_WRCLI1__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB0_WRCLI1__MAX_OSD_MASK 0xFC000000L +//DAGB0_WRCLI2 +#define DAGB0_WRCLI2__TC__SHIFT 0x0 +#define DAGB0_WRCLI2__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB0_WRCLI2__PRIORITY_ARB1__SHIFT 0x4 +#define DAGB0_WRCLI2__PROFILE_ARB2__SHIFT 0x8 +#define DAGB0_WRCLI2__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB0_WRCLI2__MAX_BW__SHIFT 0xd +#define DAGB0_WRCLI2__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB0_WRCLI2__MIN_BW__SHIFT 0x16 +#define DAGB0_WRCLI2__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB0_WRCLI2__MAX_OSD__SHIFT 0x1a +#define DAGB0_WRCLI2__TC_MASK 0x00000007L +#define DAGB0_WRCLI2__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB0_WRCLI2__PRIORITY_ARB1_MASK 0x000000F0L +#define DAGB0_WRCLI2__PROFILE_ARB2_MASK 0x00000700L +#define DAGB0_WRCLI2__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB0_WRCLI2__MAX_BW_MASK 0x001FE000L +#define DAGB0_WRCLI2__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB0_WRCLI2__MIN_BW_MASK 0x01C00000L +#define DAGB0_WRCLI2__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB0_WRCLI2__MAX_OSD_MASK 0xFC000000L +//DAGB0_WRCLI3 +#define DAGB0_WRCLI3__TC__SHIFT 0x0 +#define DAGB0_WRCLI3__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB0_WRCLI3__PRIORITY_ARB1__SHIFT 0x4 +#define DAGB0_WRCLI3__PROFILE_ARB2__SHIFT 0x8 +#define DAGB0_WRCLI3__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB0_WRCLI3__MAX_BW__SHIFT 0xd +#define DAGB0_WRCLI3__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB0_WRCLI3__MIN_BW__SHIFT 0x16 +#define DAGB0_WRCLI3__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB0_WRCLI3__MAX_OSD__SHIFT 0x1a +#define DAGB0_WRCLI3__TC_MASK 0x00000007L +#define DAGB0_WRCLI3__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB0_WRCLI3__PRIORITY_ARB1_MASK 0x000000F0L +#define DAGB0_WRCLI3__PROFILE_ARB2_MASK 0x00000700L +#define DAGB0_WRCLI3__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB0_WRCLI3__MAX_BW_MASK 0x001FE000L +#define DAGB0_WRCLI3__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB0_WRCLI3__MIN_BW_MASK 0x01C00000L +#define DAGB0_WRCLI3__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB0_WRCLI3__MAX_OSD_MASK 0xFC000000L +//DAGB0_WRCLI4 +#define DAGB0_WRCLI4__TC__SHIFT 0x0 +#define DAGB0_WRCLI4__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB0_WRCLI4__PRIORITY_ARB1__SHIFT 0x4 +#define DAGB0_WRCLI4__PROFILE_ARB2__SHIFT 0x8 +#define DAGB0_WRCLI4__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB0_WRCLI4__MAX_BW__SHIFT 0xd +#define DAGB0_WRCLI4__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB0_WRCLI4__MIN_BW__SHIFT 0x16 +#define DAGB0_WRCLI4__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB0_WRCLI4__MAX_OSD__SHIFT 0x1a +#define DAGB0_WRCLI4__TC_MASK 0x00000007L +#define DAGB0_WRCLI4__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB0_WRCLI4__PRIORITY_ARB1_MASK 0x000000F0L +#define DAGB0_WRCLI4__PROFILE_ARB2_MASK 0x00000700L +#define DAGB0_WRCLI4__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB0_WRCLI4__MAX_BW_MASK 0x001FE000L +#define DAGB0_WRCLI4__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB0_WRCLI4__MIN_BW_MASK 0x01C00000L +#define DAGB0_WRCLI4__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB0_WRCLI4__MAX_OSD_MASK 0xFC000000L +//DAGB0_WRCLI5 +#define DAGB0_WRCLI5__TC__SHIFT 0x0 +#define DAGB0_WRCLI5__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB0_WRCLI5__PRIORITY_ARB1__SHIFT 0x4 +#define DAGB0_WRCLI5__PROFILE_ARB2__SHIFT 0x8 +#define DAGB0_WRCLI5__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB0_WRCLI5__MAX_BW__SHIFT 0xd +#define DAGB0_WRCLI5__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB0_WRCLI5__MIN_BW__SHIFT 0x16 +#define DAGB0_WRCLI5__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB0_WRCLI5__MAX_OSD__SHIFT 0x1a +#define DAGB0_WRCLI5__TC_MASK 0x00000007L +#define DAGB0_WRCLI5__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB0_WRCLI5__PRIORITY_ARB1_MASK 0x000000F0L +#define DAGB0_WRCLI5__PROFILE_ARB2_MASK 0x00000700L +#define DAGB0_WRCLI5__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB0_WRCLI5__MAX_BW_MASK 0x001FE000L +#define DAGB0_WRCLI5__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB0_WRCLI5__MIN_BW_MASK 0x01C00000L +#define DAGB0_WRCLI5__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB0_WRCLI5__MAX_OSD_MASK 0xFC000000L +//DAGB0_WRCLI6 +#define DAGB0_WRCLI6__TC__SHIFT 0x0 +#define DAGB0_WRCLI6__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB0_WRCLI6__PRIORITY_ARB1__SHIFT 0x4 +#define DAGB0_WRCLI6__PROFILE_ARB2__SHIFT 0x8 +#define DAGB0_WRCLI6__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB0_WRCLI6__MAX_BW__SHIFT 0xd +#define DAGB0_WRCLI6__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB0_WRCLI6__MIN_BW__SHIFT 0x16 +#define DAGB0_WRCLI6__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB0_WRCLI6__MAX_OSD__SHIFT 0x1a +#define DAGB0_WRCLI6__TC_MASK 0x00000007L +#define DAGB0_WRCLI6__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB0_WRCLI6__PRIORITY_ARB1_MASK 0x000000F0L +#define DAGB0_WRCLI6__PROFILE_ARB2_MASK 0x00000700L +#define DAGB0_WRCLI6__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB0_WRCLI6__MAX_BW_MASK 0x001FE000L +#define DAGB0_WRCLI6__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB0_WRCLI6__MIN_BW_MASK 0x01C00000L +#define DAGB0_WRCLI6__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB0_WRCLI6__MAX_OSD_MASK 0xFC000000L +//DAGB0_WRCLI7 +#define DAGB0_WRCLI7__TC__SHIFT 0x0 +#define DAGB0_WRCLI7__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB0_WRCLI7__PRIORITY_ARB1__SHIFT 0x4 +#define DAGB0_WRCLI7__PROFILE_ARB2__SHIFT 0x8 +#define DAGB0_WRCLI7__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB0_WRCLI7__MAX_BW__SHIFT 0xd +#define DAGB0_WRCLI7__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB0_WRCLI7__MIN_BW__SHIFT 0x16 +#define DAGB0_WRCLI7__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB0_WRCLI7__MAX_OSD__SHIFT 0x1a +#define DAGB0_WRCLI7__TC_MASK 0x00000007L +#define DAGB0_WRCLI7__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB0_WRCLI7__PRIORITY_ARB1_MASK 0x000000F0L +#define DAGB0_WRCLI7__PROFILE_ARB2_MASK 0x00000700L +#define DAGB0_WRCLI7__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB0_WRCLI7__MAX_BW_MASK 0x001FE000L +#define DAGB0_WRCLI7__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB0_WRCLI7__MIN_BW_MASK 0x01C00000L +#define DAGB0_WRCLI7__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB0_WRCLI7__MAX_OSD_MASK 0xFC000000L +//DAGB0_WRCLI8 +#define DAGB0_WRCLI8__TC__SHIFT 0x0 +#define DAGB0_WRCLI8__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB0_WRCLI8__PRIORITY_ARB1__SHIFT 0x4 +#define DAGB0_WRCLI8__PROFILE_ARB2__SHIFT 0x8 +#define DAGB0_WRCLI8__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB0_WRCLI8__MAX_BW__SHIFT 0xd +#define DAGB0_WRCLI8__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB0_WRCLI8__MIN_BW__SHIFT 0x16 +#define DAGB0_WRCLI8__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB0_WRCLI8__MAX_OSD__SHIFT 0x1a +#define DAGB0_WRCLI8__TC_MASK 0x00000007L +#define DAGB0_WRCLI8__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB0_WRCLI8__PRIORITY_ARB1_MASK 0x000000F0L +#define DAGB0_WRCLI8__PROFILE_ARB2_MASK 0x00000700L +#define DAGB0_WRCLI8__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB0_WRCLI8__MAX_BW_MASK 0x001FE000L +#define DAGB0_WRCLI8__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB0_WRCLI8__MIN_BW_MASK 0x01C00000L +#define DAGB0_WRCLI8__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB0_WRCLI8__MAX_OSD_MASK 0xFC000000L +//DAGB0_WRCLI9 +#define DAGB0_WRCLI9__TC__SHIFT 0x0 +#define DAGB0_WRCLI9__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB0_WRCLI9__PRIORITY_ARB1__SHIFT 0x4 +#define DAGB0_WRCLI9__PROFILE_ARB2__SHIFT 0x8 +#define DAGB0_WRCLI9__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB0_WRCLI9__MAX_BW__SHIFT 0xd +#define DAGB0_WRCLI9__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB0_WRCLI9__MIN_BW__SHIFT 0x16 +#define DAGB0_WRCLI9__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB0_WRCLI9__MAX_OSD__SHIFT 0x1a +#define DAGB0_WRCLI9__TC_MASK 0x00000007L +#define DAGB0_WRCLI9__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB0_WRCLI9__PRIORITY_ARB1_MASK 0x000000F0L +#define DAGB0_WRCLI9__PROFILE_ARB2_MASK 0x00000700L +#define DAGB0_WRCLI9__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB0_WRCLI9__MAX_BW_MASK 0x001FE000L +#define DAGB0_WRCLI9__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB0_WRCLI9__MIN_BW_MASK 0x01C00000L +#define DAGB0_WRCLI9__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB0_WRCLI9__MAX_OSD_MASK 0xFC000000L +//DAGB0_WRCLI10 +#define DAGB0_WRCLI10__TC__SHIFT 0x0 +#define DAGB0_WRCLI10__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB0_WRCLI10__PRIORITY_ARB1__SHIFT 0x4 +#define DAGB0_WRCLI10__PROFILE_ARB2__SHIFT 0x8 +#define DAGB0_WRCLI10__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB0_WRCLI10__MAX_BW__SHIFT 0xd +#define DAGB0_WRCLI10__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB0_WRCLI10__MIN_BW__SHIFT 0x16 +#define DAGB0_WRCLI10__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB0_WRCLI10__MAX_OSD__SHIFT 0x1a +#define DAGB0_WRCLI10__TC_MASK 0x00000007L +#define DAGB0_WRCLI10__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB0_WRCLI10__PRIORITY_ARB1_MASK 0x000000F0L +#define DAGB0_WRCLI10__PROFILE_ARB2_MASK 0x00000700L +#define DAGB0_WRCLI10__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB0_WRCLI10__MAX_BW_MASK 0x001FE000L +#define DAGB0_WRCLI10__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB0_WRCLI10__MIN_BW_MASK 0x01C00000L +#define DAGB0_WRCLI10__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB0_WRCLI10__MAX_OSD_MASK 0xFC000000L +//DAGB0_WRCLI11 +#define DAGB0_WRCLI11__TC__SHIFT 0x0 +#define DAGB0_WRCLI11__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB0_WRCLI11__PRIORITY_ARB1__SHIFT 0x4 +#define DAGB0_WRCLI11__PROFILE_ARB2__SHIFT 0x8 +#define DAGB0_WRCLI11__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB0_WRCLI11__MAX_BW__SHIFT 0xd +#define DAGB0_WRCLI11__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB0_WRCLI11__MIN_BW__SHIFT 0x16 +#define DAGB0_WRCLI11__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB0_WRCLI11__MAX_OSD__SHIFT 0x1a +#define DAGB0_WRCLI11__TC_MASK 0x00000007L +#define DAGB0_WRCLI11__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB0_WRCLI11__PRIORITY_ARB1_MASK 0x000000F0L +#define DAGB0_WRCLI11__PROFILE_ARB2_MASK 0x00000700L +#define DAGB0_WRCLI11__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB0_WRCLI11__MAX_BW_MASK 0x001FE000L +#define DAGB0_WRCLI11__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB0_WRCLI11__MIN_BW_MASK 0x01C00000L +#define DAGB0_WRCLI11__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB0_WRCLI11__MAX_OSD_MASK 0xFC000000L +//DAGB0_WRCLI12 +#define DAGB0_WRCLI12__TC__SHIFT 0x0 +#define DAGB0_WRCLI12__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB0_WRCLI12__PRIORITY_ARB1__SHIFT 0x4 +#define DAGB0_WRCLI12__PROFILE_ARB2__SHIFT 0x8 +#define DAGB0_WRCLI12__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB0_WRCLI12__MAX_BW__SHIFT 0xd +#define DAGB0_WRCLI12__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB0_WRCLI12__MIN_BW__SHIFT 0x16 +#define DAGB0_WRCLI12__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB0_WRCLI12__MAX_OSD__SHIFT 0x1a +#define DAGB0_WRCLI12__TC_MASK 0x00000007L +#define DAGB0_WRCLI12__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB0_WRCLI12__PRIORITY_ARB1_MASK 0x000000F0L +#define DAGB0_WRCLI12__PROFILE_ARB2_MASK 0x00000700L +#define DAGB0_WRCLI12__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB0_WRCLI12__MAX_BW_MASK 0x001FE000L +#define DAGB0_WRCLI12__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB0_WRCLI12__MIN_BW_MASK 0x01C00000L +#define DAGB0_WRCLI12__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB0_WRCLI12__MAX_OSD_MASK 0xFC000000L +//DAGB0_WRCLI13 +#define DAGB0_WRCLI13__TC__SHIFT 0x0 +#define DAGB0_WRCLI13__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB0_WRCLI13__PRIORITY_ARB1__SHIFT 0x4 +#define DAGB0_WRCLI13__PROFILE_ARB2__SHIFT 0x8 +#define DAGB0_WRCLI13__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB0_WRCLI13__MAX_BW__SHIFT 0xd +#define DAGB0_WRCLI13__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB0_WRCLI13__MIN_BW__SHIFT 0x16 +#define DAGB0_WRCLI13__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB0_WRCLI13__MAX_OSD__SHIFT 0x1a +#define DAGB0_WRCLI13__TC_MASK 0x00000007L +#define DAGB0_WRCLI13__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB0_WRCLI13__PRIORITY_ARB1_MASK 0x000000F0L +#define DAGB0_WRCLI13__PROFILE_ARB2_MASK 0x00000700L +#define DAGB0_WRCLI13__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB0_WRCLI13__MAX_BW_MASK 0x001FE000L +#define DAGB0_WRCLI13__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB0_WRCLI13__MIN_BW_MASK 0x01C00000L +#define DAGB0_WRCLI13__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB0_WRCLI13__MAX_OSD_MASK 0xFC000000L +//DAGB0_WRCLI14 +#define DAGB0_WRCLI14__TC__SHIFT 0x0 +#define DAGB0_WRCLI14__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB0_WRCLI14__PRIORITY_ARB1__SHIFT 0x4 +#define DAGB0_WRCLI14__PROFILE_ARB2__SHIFT 0x8 +#define DAGB0_WRCLI14__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB0_WRCLI14__MAX_BW__SHIFT 0xd +#define DAGB0_WRCLI14__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB0_WRCLI14__MIN_BW__SHIFT 0x16 +#define DAGB0_WRCLI14__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB0_WRCLI14__MAX_OSD__SHIFT 0x1a +#define DAGB0_WRCLI14__TC_MASK 0x00000007L +#define DAGB0_WRCLI14__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB0_WRCLI14__PRIORITY_ARB1_MASK 0x000000F0L +#define DAGB0_WRCLI14__PROFILE_ARB2_MASK 0x00000700L +#define DAGB0_WRCLI14__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB0_WRCLI14__MAX_BW_MASK 0x001FE000L +#define DAGB0_WRCLI14__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB0_WRCLI14__MIN_BW_MASK 0x01C00000L +#define DAGB0_WRCLI14__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB0_WRCLI14__MAX_OSD_MASK 0xFC000000L +//DAGB0_WRCLI15 +#define DAGB0_WRCLI15__TC__SHIFT 0x0 +#define DAGB0_WRCLI15__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB0_WRCLI15__PRIORITY_ARB1__SHIFT 0x4 +#define DAGB0_WRCLI15__PROFILE_ARB2__SHIFT 0x8 +#define DAGB0_WRCLI15__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB0_WRCLI15__MAX_BW__SHIFT 0xd +#define DAGB0_WRCLI15__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB0_WRCLI15__MIN_BW__SHIFT 0x16 +#define DAGB0_WRCLI15__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB0_WRCLI15__MAX_OSD__SHIFT 0x1a +#define DAGB0_WRCLI15__TC_MASK 0x00000007L +#define DAGB0_WRCLI15__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB0_WRCLI15__PRIORITY_ARB1_MASK 0x000000F0L +#define DAGB0_WRCLI15__PROFILE_ARB2_MASK 0x00000700L +#define DAGB0_WRCLI15__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB0_WRCLI15__MAX_BW_MASK 0x001FE000L +#define DAGB0_WRCLI15__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB0_WRCLI15__MIN_BW_MASK 0x01C00000L +#define DAGB0_WRCLI15__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB0_WRCLI15__MAX_OSD_MASK 0xFC000000L +//DAGB0_WRCLI16 +#define DAGB0_WRCLI16__TC__SHIFT 0x0 +#define DAGB0_WRCLI16__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB0_WRCLI16__PRIORITY_ARB1__SHIFT 0x4 +#define DAGB0_WRCLI16__PROFILE_ARB2__SHIFT 0x8 +#define DAGB0_WRCLI16__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB0_WRCLI16__MAX_BW__SHIFT 0xd +#define DAGB0_WRCLI16__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB0_WRCLI16__MIN_BW__SHIFT 0x16 +#define DAGB0_WRCLI16__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB0_WRCLI16__MAX_OSD__SHIFT 0x1a +#define DAGB0_WRCLI16__TC_MASK 0x00000007L +#define DAGB0_WRCLI16__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB0_WRCLI16__PRIORITY_ARB1_MASK 0x000000F0L +#define DAGB0_WRCLI16__PROFILE_ARB2_MASK 0x00000700L +#define DAGB0_WRCLI16__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB0_WRCLI16__MAX_BW_MASK 0x001FE000L +#define DAGB0_WRCLI16__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB0_WRCLI16__MIN_BW_MASK 0x01C00000L +#define DAGB0_WRCLI16__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB0_WRCLI16__MAX_OSD_MASK 0xFC000000L +//DAGB0_WRCLI17 +#define DAGB0_WRCLI17__TC__SHIFT 0x0 +#define DAGB0_WRCLI17__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB0_WRCLI17__PRIORITY_ARB1__SHIFT 0x4 +#define DAGB0_WRCLI17__PROFILE_ARB2__SHIFT 0x8 +#define DAGB0_WRCLI17__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB0_WRCLI17__MAX_BW__SHIFT 0xd +#define DAGB0_WRCLI17__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB0_WRCLI17__MIN_BW__SHIFT 0x16 +#define DAGB0_WRCLI17__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB0_WRCLI17__MAX_OSD__SHIFT 0x1a +#define DAGB0_WRCLI17__TC_MASK 0x00000007L +#define DAGB0_WRCLI17__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB0_WRCLI17__PRIORITY_ARB1_MASK 0x000000F0L +#define DAGB0_WRCLI17__PROFILE_ARB2_MASK 0x00000700L +#define DAGB0_WRCLI17__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB0_WRCLI17__MAX_BW_MASK 0x001FE000L +#define DAGB0_WRCLI17__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB0_WRCLI17__MIN_BW_MASK 0x01C00000L +#define DAGB0_WRCLI17__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB0_WRCLI17__MAX_OSD_MASK 0xFC000000L +//DAGB0_WRCLI18 +#define DAGB0_WRCLI18__TC__SHIFT 0x0 +#define DAGB0_WRCLI18__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB0_WRCLI18__PRIORITY_ARB1__SHIFT 0x4 +#define DAGB0_WRCLI18__PROFILE_ARB2__SHIFT 0x8 +#define DAGB0_WRCLI18__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB0_WRCLI18__MAX_BW__SHIFT 0xd +#define DAGB0_WRCLI18__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB0_WRCLI18__MIN_BW__SHIFT 0x16 +#define DAGB0_WRCLI18__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB0_WRCLI18__MAX_OSD__SHIFT 0x1a +#define DAGB0_WRCLI18__TC_MASK 0x00000007L +#define DAGB0_WRCLI18__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB0_WRCLI18__PRIORITY_ARB1_MASK 0x000000F0L +#define DAGB0_WRCLI18__PROFILE_ARB2_MASK 0x00000700L +#define DAGB0_WRCLI18__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB0_WRCLI18__MAX_BW_MASK 0x001FE000L +#define DAGB0_WRCLI18__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB0_WRCLI18__MIN_BW_MASK 0x01C00000L +#define DAGB0_WRCLI18__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB0_WRCLI18__MAX_OSD_MASK 0xFC000000L +//DAGB0_WRCLI19 +#define DAGB0_WRCLI19__TC__SHIFT 0x0 +#define DAGB0_WRCLI19__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB0_WRCLI19__PRIORITY_ARB1__SHIFT 0x4 +#define DAGB0_WRCLI19__PROFILE_ARB2__SHIFT 0x8 +#define DAGB0_WRCLI19__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB0_WRCLI19__MAX_BW__SHIFT 0xd +#define DAGB0_WRCLI19__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB0_WRCLI19__MIN_BW__SHIFT 0x16 +#define DAGB0_WRCLI19__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB0_WRCLI19__MAX_OSD__SHIFT 0x1a +#define DAGB0_WRCLI19__TC_MASK 0x00000007L +#define DAGB0_WRCLI19__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB0_WRCLI19__PRIORITY_ARB1_MASK 0x000000F0L +#define DAGB0_WRCLI19__PROFILE_ARB2_MASK 0x00000700L +#define DAGB0_WRCLI19__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB0_WRCLI19__MAX_BW_MASK 0x001FE000L +#define DAGB0_WRCLI19__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB0_WRCLI19__MIN_BW_MASK 0x01C00000L +#define DAGB0_WRCLI19__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB0_WRCLI19__MAX_OSD_MASK 0xFC000000L +//DAGB0_WRCLI20 +#define DAGB0_WRCLI20__TC__SHIFT 0x0 +#define DAGB0_WRCLI20__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB0_WRCLI20__PRIORITY_ARB1__SHIFT 0x4 +#define DAGB0_WRCLI20__PROFILE_ARB2__SHIFT 0x8 +#define DAGB0_WRCLI20__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB0_WRCLI20__MAX_BW__SHIFT 0xd +#define DAGB0_WRCLI20__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB0_WRCLI20__MIN_BW__SHIFT 0x16 +#define DAGB0_WRCLI20__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB0_WRCLI20__MAX_OSD__SHIFT 0x1a +#define DAGB0_WRCLI20__TC_MASK 0x00000007L +#define DAGB0_WRCLI20__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB0_WRCLI20__PRIORITY_ARB1_MASK 0x000000F0L +#define DAGB0_WRCLI20__PROFILE_ARB2_MASK 0x00000700L +#define DAGB0_WRCLI20__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB0_WRCLI20__MAX_BW_MASK 0x001FE000L +#define DAGB0_WRCLI20__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB0_WRCLI20__MIN_BW_MASK 0x01C00000L +#define DAGB0_WRCLI20__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB0_WRCLI20__MAX_OSD_MASK 0xFC000000L +//DAGB0_WRCLI21 +#define DAGB0_WRCLI21__TC__SHIFT 0x0 +#define DAGB0_WRCLI21__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB0_WRCLI21__PRIORITY_ARB1__SHIFT 0x4 +#define DAGB0_WRCLI21__PROFILE_ARB2__SHIFT 0x8 +#define DAGB0_WRCLI21__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB0_WRCLI21__MAX_BW__SHIFT 0xd +#define DAGB0_WRCLI21__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB0_WRCLI21__MIN_BW__SHIFT 0x16 +#define DAGB0_WRCLI21__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB0_WRCLI21__MAX_OSD__SHIFT 0x1a +#define DAGB0_WRCLI21__TC_MASK 0x00000007L +#define DAGB0_WRCLI21__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB0_WRCLI21__PRIORITY_ARB1_MASK 0x000000F0L +#define DAGB0_WRCLI21__PROFILE_ARB2_MASK 0x00000700L +#define DAGB0_WRCLI21__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB0_WRCLI21__MAX_BW_MASK 0x001FE000L +#define DAGB0_WRCLI21__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB0_WRCLI21__MIN_BW_MASK 0x01C00000L +#define DAGB0_WRCLI21__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB0_WRCLI21__MAX_OSD_MASK 0xFC000000L +//DAGB0_WRCLI22 +#define DAGB0_WRCLI22__TC__SHIFT 0x0 +#define DAGB0_WRCLI22__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB0_WRCLI22__PRIORITY_ARB1__SHIFT 0x4 +#define DAGB0_WRCLI22__PROFILE_ARB2__SHIFT 0x8 +#define DAGB0_WRCLI22__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB0_WRCLI22__MAX_BW__SHIFT 0xd +#define DAGB0_WRCLI22__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB0_WRCLI22__MIN_BW__SHIFT 0x16 +#define DAGB0_WRCLI22__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB0_WRCLI22__MAX_OSD__SHIFT 0x1a +#define DAGB0_WRCLI22__TC_MASK 0x00000007L +#define DAGB0_WRCLI22__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB0_WRCLI22__PRIORITY_ARB1_MASK 0x000000F0L +#define DAGB0_WRCLI22__PROFILE_ARB2_MASK 0x00000700L +#define DAGB0_WRCLI22__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB0_WRCLI22__MAX_BW_MASK 0x001FE000L +#define DAGB0_WRCLI22__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB0_WRCLI22__MIN_BW_MASK 0x01C00000L +#define DAGB0_WRCLI22__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB0_WRCLI22__MAX_OSD_MASK 0xFC000000L +//DAGB0_WRCLI23 +#define DAGB0_WRCLI23__TC__SHIFT 0x0 +#define DAGB0_WRCLI23__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB0_WRCLI23__PRIORITY_ARB1__SHIFT 0x4 +#define DAGB0_WRCLI23__PROFILE_ARB2__SHIFT 0x8 +#define DAGB0_WRCLI23__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB0_WRCLI23__MAX_BW__SHIFT 0xd +#define DAGB0_WRCLI23__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB0_WRCLI23__MIN_BW__SHIFT 0x16 +#define DAGB0_WRCLI23__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB0_WRCLI23__MAX_OSD__SHIFT 0x1a +#define DAGB0_WRCLI23__TC_MASK 0x00000007L +#define DAGB0_WRCLI23__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB0_WRCLI23__PRIORITY_ARB1_MASK 0x000000F0L +#define DAGB0_WRCLI23__PROFILE_ARB2_MASK 0x00000700L +#define DAGB0_WRCLI23__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB0_WRCLI23__MAX_BW_MASK 0x001FE000L +#define DAGB0_WRCLI23__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB0_WRCLI23__MIN_BW_MASK 0x01C00000L +#define DAGB0_WRCLI23__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB0_WRCLI23__MAX_OSD_MASK 0xFC000000L +//DAGB0_WR_CNTL +#define DAGB0_WR_CNTL__CLI_MAX_BW_WINDOW__SHIFT 0x0 +#define DAGB0_WR_CNTL__CLI_MAX_BW_WINDOW_MASK 0x000001FFL +//DAGB0_WR_ADDR_DAGB +#define DAGB0_WR_ADDR_DAGB__DAGB_ENABLE__SHIFT 0x0 +#define DAGB0_WR_ADDR_DAGB__ENABLE_JUMP_AHEAD__SHIFT 0x4 +#define DAGB0_WR_ADDR_DAGB__DISABLE_SELF_INIT__SHIFT 0x8 +#define DAGB0_WR_ADDR_DAGB__WHOAMI__SHIFT 0x9 +#define DAGB0_WR_ADDR_DAGB__JUMP_MODE__SHIFT 0xf +#define DAGB0_WR_ADDR_DAGB__DAGB_ENABLE_MASK 0x0000000FL +#define DAGB0_WR_ADDR_DAGB__ENABLE_JUMP_AHEAD_MASK 0x000000F0L +#define DAGB0_WR_ADDR_DAGB__DISABLE_SELF_INIT_MASK 0x00000100L +#define DAGB0_WR_ADDR_DAGB__WHOAMI_MASK 0x00007E00L +#define DAGB0_WR_ADDR_DAGB__JUMP_MODE_MASK 0x00008000L +//DAGB0_WR_CGTT_CLK_CTRL +#define DAGB0_WR_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 +#define DAGB0_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x5 +#define DAGB0_WR_CGTT_CLK_CTRL__LS_ASSERT_HYSTERESIS__SHIFT 0xd +#define DAGB0_WR_CGTT_CLK_CTRL__MIN_MGLS__SHIFT 0x1a +#define DAGB0_WR_CGTT_CLK_CTRL__CGLS_DISABLE__SHIFT 0x1d +#define DAGB0_WR_CGTT_CLK_CTRL__LS_DISABLE__SHIFT 0x1e +#define DAGB0_WR_CGTT_CLK_CTRL__BUSY_OVERRIDE__SHIFT 0x1f +#define DAGB0_WR_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000001FL +#define DAGB0_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00001FE0L +#define DAGB0_WR_CGTT_CLK_CTRL__LS_ASSERT_HYSTERESIS_MASK 0x03FFE000L +#define DAGB0_WR_CGTT_CLK_CTRL__MIN_MGLS_MASK 0x1C000000L +#define DAGB0_WR_CGTT_CLK_CTRL__CGLS_DISABLE_MASK 0x20000000L +#define DAGB0_WR_CGTT_CLK_CTRL__LS_DISABLE_MASK 0x40000000L +#define DAGB0_WR_CGTT_CLK_CTRL__BUSY_OVERRIDE_MASK 0x80000000L +//DAGB0_L1TLB_WR_CGTT_CLK_CTRL +#define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 +#define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x5 +#define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__LS_ASSERT_HYSTERESIS__SHIFT 0xd +#define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__MIN_MGLS__SHIFT 0x1a +#define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__CGLS_DISABLE__SHIFT 0x1d +#define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__LS_DISABLE__SHIFT 0x1e +#define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__BUSY_OVERRIDE__SHIFT 0x1f +#define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000001FL +#define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00001FE0L +#define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__LS_ASSERT_HYSTERESIS_MASK 0x03FFE000L +#define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__MIN_MGLS_MASK 0x1C000000L +#define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__CGLS_DISABLE_MASK 0x20000000L +#define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__LS_DISABLE_MASK 0x40000000L +#define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__BUSY_OVERRIDE_MASK 0x80000000L +//DAGB0_WR_ADDR_DAGB_MAX_BURST0 +#define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT0__SHIFT 0x0 +#define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT1__SHIFT 0x4 +#define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT2__SHIFT 0x8 +#define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT3__SHIFT 0xc +#define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT4__SHIFT 0x10 +#define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT5__SHIFT 0x14 +#define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT6__SHIFT 0x18 +#define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT7__SHIFT 0x1c +#define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT0_MASK 0x0000000FL +#define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT1_MASK 0x000000F0L +#define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT2_MASK 0x00000F00L +#define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT3_MASK 0x0000F000L +#define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT4_MASK 0x000F0000L +#define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT5_MASK 0x00F00000L +#define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT6_MASK 0x0F000000L +#define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT7_MASK 0xF0000000L +//DAGB0_WR_ADDR_DAGB_LAZY_TIMER0 +#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT0__SHIFT 0x0 +#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT1__SHIFT 0x4 +#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT2__SHIFT 0x8 +#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT3__SHIFT 0xc +#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT4__SHIFT 0x10 +#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT5__SHIFT 0x14 +#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT6__SHIFT 0x18 +#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT7__SHIFT 0x1c +#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT0_MASK 0x0000000FL +#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT1_MASK 0x000000F0L +#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT2_MASK 0x00000F00L +#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT3_MASK 0x0000F000L +#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT4_MASK 0x000F0000L +#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT5_MASK 0x00F00000L +#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT6_MASK 0x0F000000L +#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT7_MASK 0xF0000000L +//DAGB0_WR_ADDR_DAGB_MAX_BURST1 +#define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT8__SHIFT 0x0 +#define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT9__SHIFT 0x4 +#define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT10__SHIFT 0x8 +#define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT11__SHIFT 0xc +#define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT12__SHIFT 0x10 +#define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT13__SHIFT 0x14 +#define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT14__SHIFT 0x18 +#define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT15__SHIFT 0x1c +#define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT8_MASK 0x0000000FL +#define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT9_MASK 0x000000F0L +#define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT10_MASK 0x00000F00L +#define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT11_MASK 0x0000F000L +#define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT12_MASK 0x000F0000L +#define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT13_MASK 0x00F00000L +#define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT14_MASK 0x0F000000L +#define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT15_MASK 0xF0000000L +//DAGB0_WR_ADDR_DAGB_LAZY_TIMER1 +#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT8__SHIFT 0x0 +#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT9__SHIFT 0x4 +#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT10__SHIFT 0x8 +#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT11__SHIFT 0xc +#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT12__SHIFT 0x10 +#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT13__SHIFT 0x14 +#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT14__SHIFT 0x18 +#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT15__SHIFT 0x1c +#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT8_MASK 0x0000000FL +#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT9_MASK 0x000000F0L +#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT10_MASK 0x00000F00L +#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT11_MASK 0x0000F000L +#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT12_MASK 0x000F0000L +#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT13_MASK 0x00F00000L +#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT14_MASK 0x0F000000L +#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT15_MASK 0xF0000000L +//DAGB0_WR_ADDR_DAGB_MAX_BURST2 +#define DAGB0_WR_ADDR_DAGB_MAX_BURST2__CLIENT16__SHIFT 0x0 +#define DAGB0_WR_ADDR_DAGB_MAX_BURST2__CLIENT17__SHIFT 0x4 +#define DAGB0_WR_ADDR_DAGB_MAX_BURST2__CLIENT18__SHIFT 0x8 +#define DAGB0_WR_ADDR_DAGB_MAX_BURST2__CLIENT19__SHIFT 0xc +#define DAGB0_WR_ADDR_DAGB_MAX_BURST2__CLIENT20__SHIFT 0x10 +#define DAGB0_WR_ADDR_DAGB_MAX_BURST2__CLIENT21__SHIFT 0x14 +#define DAGB0_WR_ADDR_DAGB_MAX_BURST2__CLIENT22__SHIFT 0x18 +#define DAGB0_WR_ADDR_DAGB_MAX_BURST2__CLIENT23__SHIFT 0x1c +#define DAGB0_WR_ADDR_DAGB_MAX_BURST2__CLIENT16_MASK 0x0000000FL +#define DAGB0_WR_ADDR_DAGB_MAX_BURST2__CLIENT17_MASK 0x000000F0L +#define DAGB0_WR_ADDR_DAGB_MAX_BURST2__CLIENT18_MASK 0x00000F00L +#define DAGB0_WR_ADDR_DAGB_MAX_BURST2__CLIENT19_MASK 0x0000F000L +#define DAGB0_WR_ADDR_DAGB_MAX_BURST2__CLIENT20_MASK 0x000F0000L +#define DAGB0_WR_ADDR_DAGB_MAX_BURST2__CLIENT21_MASK 0x00F00000L +#define DAGB0_WR_ADDR_DAGB_MAX_BURST2__CLIENT22_MASK 0x0F000000L +#define DAGB0_WR_ADDR_DAGB_MAX_BURST2__CLIENT23_MASK 0xF0000000L +//DAGB0_WR_ADDR_DAGB_LAZY_TIMER2 +#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER2__CLIENT16__SHIFT 0x0 +#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER2__CLIENT17__SHIFT 0x4 +#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER2__CLIENT18__SHIFT 0x8 +#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER2__CLIENT19__SHIFT 0xc +#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER2__CLIENT20__SHIFT 0x10 +#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER2__CLIENT21__SHIFT 0x14 +#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER2__CLIENT22__SHIFT 0x18 +#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER2__CLIENT23__SHIFT 0x1c +#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER2__CLIENT16_MASK 0x0000000FL +#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER2__CLIENT17_MASK 0x000000F0L +#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER2__CLIENT18_MASK 0x00000F00L +#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER2__CLIENT19_MASK 0x0000F000L +#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER2__CLIENT20_MASK 0x000F0000L +#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER2__CLIENT21_MASK 0x00F00000L +#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER2__CLIENT22_MASK 0x0F000000L +#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER2__CLIENT23_MASK 0xF0000000L +//DAGB0_WR_DATA_DAGB +#define DAGB0_WR_DATA_DAGB__DAGB_ENABLE__SHIFT 0x0 +#define DAGB0_WR_DATA_DAGB__ENABLE_JUMP_AHEAD__SHIFT 0x4 +#define DAGB0_WR_DATA_DAGB__DISABLE_SELF_INIT__SHIFT 0x8 +#define DAGB0_WR_DATA_DAGB__WHOAMI__SHIFT 0x9 +#define DAGB0_WR_DATA_DAGB__DAGB_ENABLE_MASK 0x0000000FL +#define DAGB0_WR_DATA_DAGB__ENABLE_JUMP_AHEAD_MASK 0x000000F0L +#define DAGB0_WR_DATA_DAGB__DISABLE_SELF_INIT_MASK 0x00000100L +#define DAGB0_WR_DATA_DAGB__WHOAMI_MASK 0x00007E00L +//DAGB0_WR_DATA_DAGB_MAX_BURST0 +#define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT0__SHIFT 0x0 +#define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT1__SHIFT 0x4 +#define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT2__SHIFT 0x8 +#define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT3__SHIFT 0xc +#define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT4__SHIFT 0x10 +#define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT5__SHIFT 0x14 +#define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT6__SHIFT 0x18 +#define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT7__SHIFT 0x1c +#define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT0_MASK 0x0000000FL +#define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT1_MASK 0x000000F0L +#define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT2_MASK 0x00000F00L +#define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT3_MASK 0x0000F000L +#define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT4_MASK 0x000F0000L +#define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT5_MASK 0x00F00000L +#define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT6_MASK 0x0F000000L +#define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT7_MASK 0xF0000000L +//DAGB0_WR_DATA_DAGB_LAZY_TIMER0 +#define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT0__SHIFT 0x0 +#define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT1__SHIFT 0x4 +#define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT2__SHIFT 0x8 +#define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT3__SHIFT 0xc +#define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT4__SHIFT 0x10 +#define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT5__SHIFT 0x14 +#define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT6__SHIFT 0x18 +#define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT7__SHIFT 0x1c +#define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT0_MASK 0x0000000FL +#define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT1_MASK 0x000000F0L +#define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT2_MASK 0x00000F00L +#define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT3_MASK 0x0000F000L +#define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT4_MASK 0x000F0000L +#define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT5_MASK 0x00F00000L +#define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT6_MASK 0x0F000000L +#define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT7_MASK 0xF0000000L +//DAGB0_WR_DATA_DAGB_MAX_BURST1 +#define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT8__SHIFT 0x0 +#define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT9__SHIFT 0x4 +#define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT10__SHIFT 0x8 +#define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT11__SHIFT 0xc +#define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT12__SHIFT 0x10 +#define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT13__SHIFT 0x14 +#define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT14__SHIFT 0x18 +#define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT15__SHIFT 0x1c +#define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT8_MASK 0x0000000FL +#define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT9_MASK 0x000000F0L +#define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT10_MASK 0x00000F00L +#define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT11_MASK 0x0000F000L +#define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT12_MASK 0x000F0000L +#define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT13_MASK 0x00F00000L +#define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT14_MASK 0x0F000000L +#define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT15_MASK 0xF0000000L +//DAGB0_WR_DATA_DAGB_LAZY_TIMER1 +#define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT8__SHIFT 0x0 +#define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT9__SHIFT 0x4 +#define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT10__SHIFT 0x8 +#define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT11__SHIFT 0xc +#define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT12__SHIFT 0x10 +#define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT13__SHIFT 0x14 +#define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT14__SHIFT 0x18 +#define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT15__SHIFT 0x1c +#define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT8_MASK 0x0000000FL +#define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT9_MASK 0x000000F0L +#define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT10_MASK 0x00000F00L +#define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT11_MASK 0x0000F000L +#define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT12_MASK 0x000F0000L +#define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT13_MASK 0x00F00000L +#define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT14_MASK 0x0F000000L +#define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT15_MASK 0xF0000000L +//DAGB0_WR_DATA_DAGB_MAX_BURST2 +#define DAGB0_WR_DATA_DAGB_MAX_BURST2__CLIENT16__SHIFT 0x0 +#define DAGB0_WR_DATA_DAGB_MAX_BURST2__CLIENT17__SHIFT 0x4 +#define DAGB0_WR_DATA_DAGB_MAX_BURST2__CLIENT18__SHIFT 0x8 +#define DAGB0_WR_DATA_DAGB_MAX_BURST2__CLIENT19__SHIFT 0xc +#define DAGB0_WR_DATA_DAGB_MAX_BURST2__CLIENT20__SHIFT 0x10 +#define DAGB0_WR_DATA_DAGB_MAX_BURST2__CLIENT21__SHIFT 0x14 +#define DAGB0_WR_DATA_DAGB_MAX_BURST2__CLIENT22__SHIFT 0x18 +#define DAGB0_WR_DATA_DAGB_MAX_BURST2__CLIENT23__SHIFT 0x1c +#define DAGB0_WR_DATA_DAGB_MAX_BURST2__CLIENT16_MASK 0x0000000FL +#define DAGB0_WR_DATA_DAGB_MAX_BURST2__CLIENT17_MASK 0x000000F0L +#define DAGB0_WR_DATA_DAGB_MAX_BURST2__CLIENT18_MASK 0x00000F00L +#define DAGB0_WR_DATA_DAGB_MAX_BURST2__CLIENT19_MASK 0x0000F000L +#define DAGB0_WR_DATA_DAGB_MAX_BURST2__CLIENT20_MASK 0x000F0000L +#define DAGB0_WR_DATA_DAGB_MAX_BURST2__CLIENT21_MASK 0x00F00000L +#define DAGB0_WR_DATA_DAGB_MAX_BURST2__CLIENT22_MASK 0x0F000000L +#define DAGB0_WR_DATA_DAGB_MAX_BURST2__CLIENT23_MASK 0xF0000000L +//DAGB0_WR_DATA_DAGB_LAZY_TIMER2 +#define DAGB0_WR_DATA_DAGB_LAZY_TIMER2__CLIENT16__SHIFT 0x0 +#define DAGB0_WR_DATA_DAGB_LAZY_TIMER2__CLIENT17__SHIFT 0x4 +#define DAGB0_WR_DATA_DAGB_LAZY_TIMER2__CLIENT18__SHIFT 0x8 +#define DAGB0_WR_DATA_DAGB_LAZY_TIMER2__CLIENT19__SHIFT 0xc +#define DAGB0_WR_DATA_DAGB_LAZY_TIMER2__CLIENT20__SHIFT 0x10 +#define DAGB0_WR_DATA_DAGB_LAZY_TIMER2__CLIENT21__SHIFT 0x14 +#define DAGB0_WR_DATA_DAGB_LAZY_TIMER2__CLIENT22__SHIFT 0x18 +#define DAGB0_WR_DATA_DAGB_LAZY_TIMER2__CLIENT23__SHIFT 0x1c +#define DAGB0_WR_DATA_DAGB_LAZY_TIMER2__CLIENT16_MASK 0x0000000FL +#define DAGB0_WR_DATA_DAGB_LAZY_TIMER2__CLIENT17_MASK 0x000000F0L +#define DAGB0_WR_DATA_DAGB_LAZY_TIMER2__CLIENT18_MASK 0x00000F00L +#define DAGB0_WR_DATA_DAGB_LAZY_TIMER2__CLIENT19_MASK 0x0000F000L +#define DAGB0_WR_DATA_DAGB_LAZY_TIMER2__CLIENT20_MASK 0x000F0000L +#define DAGB0_WR_DATA_DAGB_LAZY_TIMER2__CLIENT21_MASK 0x00F00000L +#define DAGB0_WR_DATA_DAGB_LAZY_TIMER2__CLIENT22_MASK 0x0F000000L +#define DAGB0_WR_DATA_DAGB_LAZY_TIMER2__CLIENT23_MASK 0xF0000000L +//DAGB0_WR_CNTL_MISC +#define DAGB0_WR_CNTL_MISC__HDP_CID__SHIFT 0x6 +#define DAGB0_WR_CNTL_MISC__CLI_SWITCH_MODE__SHIFT 0xb +#define DAGB0_WR_CNTL_MISC__CREDIT_SWITCH_MODE__SHIFT 0xd +#define DAGB0_WR_CNTL_MISC__BUDGET_SWITCH_MODE__SHIFT 0xf +#define DAGB0_WR_CNTL_MISC__CLI_CLEAN_MODE__SHIFT 0x11 +#define DAGB0_WR_CNTL_MISC__HDP_CID_MASK 0x000007C0L +#define DAGB0_WR_CNTL_MISC__CLI_SWITCH_MODE_MASK 0x00001800L +#define DAGB0_WR_CNTL_MISC__CREDIT_SWITCH_MODE_MASK 0x00006000L +#define DAGB0_WR_CNTL_MISC__BUDGET_SWITCH_MODE_MASK 0x00018000L +#define DAGB0_WR_CNTL_MISC__CLI_CLEAN_MODE_MASK 0x00020000L +//DAGB0_WR_TLB_CREDIT +#define DAGB0_WR_TLB_CREDIT__TLB0__SHIFT 0x0 +#define DAGB0_WR_TLB_CREDIT__TLB1__SHIFT 0x5 +#define DAGB0_WR_TLB_CREDIT__TLB2__SHIFT 0xa +#define DAGB0_WR_TLB_CREDIT__TLB3__SHIFT 0xf +#define DAGB0_WR_TLB_CREDIT__TLB0_MASK 0x0000001FL +#define DAGB0_WR_TLB_CREDIT__TLB1_MASK 0x000003E0L +#define DAGB0_WR_TLB_CREDIT__TLB2_MASK 0x00007C00L +#define DAGB0_WR_TLB_CREDIT__TLB3_MASK 0x000F8000L +//DAGB0_WR_DATA_FIFO_CREDIT_CNTL1 +#define DAGB0_WR_DATA_FIFO_CREDIT_CNTL1__TC0_CREDIT__SHIFT 0x0 +#define DAGB0_WR_DATA_FIFO_CREDIT_CNTL1__TC1_CREDIT__SHIFT 0x5 +#define DAGB0_WR_DATA_FIFO_CREDIT_CNTL1__TC2_CREDIT__SHIFT 0xa +#define DAGB0_WR_DATA_FIFO_CREDIT_CNTL1__POOL_CREDIT__SHIFT 0x14 +#define DAGB0_WR_DATA_FIFO_CREDIT_CNTL1__FIX_EQ__SHIFT 0x1d +#define DAGB0_WR_DATA_FIFO_CREDIT_CNTL1__TC0_CREDIT_MASK 0x0000001FL +#define DAGB0_WR_DATA_FIFO_CREDIT_CNTL1__TC1_CREDIT_MASK 0x000003E0L +#define DAGB0_WR_DATA_FIFO_CREDIT_CNTL1__TC2_CREDIT_MASK 0x00007C00L +#define DAGB0_WR_DATA_FIFO_CREDIT_CNTL1__POOL_CREDIT_MASK 0x0FF00000L +#define DAGB0_WR_DATA_FIFO_CREDIT_CNTL1__FIX_EQ_MASK 0x20000000L +//DAGB0_WR_ATOMIC_FIFO_CREDIT_CNTL1 +#define DAGB0_WR_ATOMIC_FIFO_CREDIT_CNTL1__TC0_CREDIT__SHIFT 0x0 +#define DAGB0_WR_ATOMIC_FIFO_CREDIT_CNTL1__TC1_CREDIT__SHIFT 0x5 +#define DAGB0_WR_ATOMIC_FIFO_CREDIT_CNTL1__TC2_CREDIT__SHIFT 0xa +#define DAGB0_WR_ATOMIC_FIFO_CREDIT_CNTL1__POOL_CREDIT__SHIFT 0x14 +#define DAGB0_WR_ATOMIC_FIFO_CREDIT_CNTL1__FIX_EQ_STORE__SHIFT 0x1b +#define DAGB0_WR_ATOMIC_FIFO_CREDIT_CNTL1__FIX_EQ_ATOMIC__SHIFT 0x1c +#define DAGB0_WR_ATOMIC_FIFO_CREDIT_CNTL1__TC0_CREDIT_MASK 0x0000001FL +#define DAGB0_WR_ATOMIC_FIFO_CREDIT_CNTL1__TC1_CREDIT_MASK 0x000003E0L +#define DAGB0_WR_ATOMIC_FIFO_CREDIT_CNTL1__TC2_CREDIT_MASK 0x00007C00L +#define DAGB0_WR_ATOMIC_FIFO_CREDIT_CNTL1__POOL_CREDIT_MASK 0x03F00000L +#define DAGB0_WR_ATOMIC_FIFO_CREDIT_CNTL1__FIX_EQ_STORE_MASK 0x08000000L +#define DAGB0_WR_ATOMIC_FIFO_CREDIT_CNTL1__FIX_EQ_ATOMIC_MASK 0x10000000L +//DAGB0_WRCLI_ASK_PENDING +#define DAGB0_WRCLI_ASK_PENDING__BUSY__SHIFT 0x0 +#define DAGB0_WRCLI_ASK_PENDING__BUSY_MASK 0x00FFFFFFL +//DAGB0_WRCLI_GO_PENDING +#define DAGB0_WRCLI_GO_PENDING__BUSY__SHIFT 0x0 +#define DAGB0_WRCLI_GO_PENDING__BUSY_MASK 0x00FFFFFFL +//DAGB0_WRCLI_GBLSEND_PENDING +#define DAGB0_WRCLI_GBLSEND_PENDING__BUSY__SHIFT 0x0 +#define DAGB0_WRCLI_GBLSEND_PENDING__BUSY_MASK 0x00FFFFFFL +//DAGB0_WRCLI_TLB_PENDING +#define DAGB0_WRCLI_TLB_PENDING__BUSY__SHIFT 0x0 +#define DAGB0_WRCLI_TLB_PENDING__BUSY_MASK 0x00FFFFFFL +//DAGB0_WRCLI_OARB_PENDING +#define DAGB0_WRCLI_OARB_PENDING__BUSY__SHIFT 0x0 +#define DAGB0_WRCLI_OARB_PENDING__BUSY_MASK 0x00FFFFFFL +//DAGB0_WRCLI_ASK2DF_PENDING +#define DAGB0_WRCLI_ASK2DF_PENDING__NUM__SHIFT 0x0 +#define DAGB0_WRCLI_ASK2DF_PENDING__NUM_MASK 0x0000FFFFL +//DAGB0_WRCLI_OSD_PENDING +#define DAGB0_WRCLI_OSD_PENDING__BUSY__SHIFT 0x0 +#define DAGB0_WRCLI_OSD_PENDING__BUSY_MASK 0x00FFFFFFL +//DAGB0_WRCLI_ASK_OSD_PENDING +#define DAGB0_WRCLI_ASK_OSD_PENDING__BUSY__SHIFT 0x0 +#define DAGB0_WRCLI_ASK_OSD_PENDING__BUSY_MASK 0x00FFFFFFL +//DAGB0_WRCLI_DBUS_ASK_PENDING +#define DAGB0_WRCLI_DBUS_ASK_PENDING__BUSY__SHIFT 0x0 +#define DAGB0_WRCLI_DBUS_ASK_PENDING__BUSY_MASK 0x00FFFFFFL +//DAGB0_WRCLI_DBUS_GO_PENDING +#define DAGB0_WRCLI_DBUS_GO_PENDING__BUSY__SHIFT 0x0 +#define DAGB0_WRCLI_DBUS_GO_PENDING__BUSY_MASK 0x00FFFFFFL +//DAGB0_SDP_ERR_STATUS +#define DAGB0_SDP_ERR_STATUS__SDP_RDRSP_STATUS__SHIFT 0x0 +#define DAGB0_SDP_ERR_STATUS__SDP_WRRSP_STATUS__SHIFT 0x4 +#define DAGB0_SDP_ERR_STATUS__SDP_RDRSP_DATASTATUS__SHIFT 0x8 +#define DAGB0_SDP_ERR_STATUS__SDP_RDRSP_METADATA_ERROR__SHIFT 0xa +#define DAGB0_SDP_ERR_STATUS__SDP_RDRSP_DATAPARITY_ERROR__SHIFT 0xb +#define DAGB0_SDP_ERR_STATUS__WR_DATAPARITY_ERROR__SHIFT 0xc +#define DAGB0_SDP_ERR_STATUS__CLEAR_ERROR_STATUS__SHIFT 0xd +#define DAGB0_SDP_ERR_STATUS__BUSY_ON_ERROR__SHIFT 0xe +#define DAGB0_SDP_ERR_STATUS__FATAL_FLAG__SHIFT 0xf +#define DAGB0_SDP_ERR_STATUS__FUE_FLAG__SHIFT 0x10 +#define DAGB0_SDP_ERR_STATUS__FUE_FLAG_CLIENT__SHIFT 0x11 +#define DAGB0_SDP_ERR_STATUS__SDP_RDRSP_STATUS_MASK 0x0000000FL +#define DAGB0_SDP_ERR_STATUS__SDP_WRRSP_STATUS_MASK 0x000000F0L +#define DAGB0_SDP_ERR_STATUS__SDP_RDRSP_DATASTATUS_MASK 0x00000300L +#define DAGB0_SDP_ERR_STATUS__SDP_RDRSP_METADATA_ERROR_MASK 0x00000400L +#define DAGB0_SDP_ERR_STATUS__SDP_RDRSP_DATAPARITY_ERROR_MASK 0x00000800L +#define DAGB0_SDP_ERR_STATUS__WR_DATAPARITY_ERROR_MASK 0x00001000L +#define DAGB0_SDP_ERR_STATUS__CLEAR_ERROR_STATUS_MASK 0x00002000L +#define DAGB0_SDP_ERR_STATUS__BUSY_ON_ERROR_MASK 0x00004000L +#define DAGB0_SDP_ERR_STATUS__FATAL_FLAG_MASK 0x00008000L +#define DAGB0_SDP_ERR_STATUS__FUE_FLAG_MASK 0x00010000L +#define DAGB0_SDP_ERR_STATUS__FUE_FLAG_CLIENT_MASK 0x00020000L +//DAGB0_DAGB_DLY +#define DAGB0_DAGB_DLY__DLY__SHIFT 0x0 +#define DAGB0_DAGB_DLY__CLI__SHIFT 0x8 +#define DAGB0_DAGB_DLY__POS__SHIFT 0x10 +#define DAGB0_DAGB_DLY__DLY_MASK 0x000000FFL +#define DAGB0_DAGB_DLY__CLI_MASK 0x0000FF00L +#define DAGB0_DAGB_DLY__POS_MASK 0x000F0000L +//DAGB0_CNTL_MISC +#define DAGB0_CNTL_MISC__BW_INIT_CYCLE__SHIFT 0x0 +#define DAGB0_CNTL_MISC__OVERRIDE_ILLEGAL_REQ__SHIFT 0x6 +#define DAGB0_CNTL_MISC__BW_INIT_CYCLE_MASK 0x0000003FL +#define DAGB0_CNTL_MISC__OVERRIDE_ILLEGAL_REQ_MASK 0x00000040L +//DAGB0_CNTL_MISC2 +#define DAGB0_CNTL_MISC2__DAGB_BUSY_OVERRIDE__SHIFT 0x0 +#define DAGB0_CNTL_MISC2__SWAP_CTL__SHIFT 0x1 +#define DAGB0_CNTL_MISC2__RDRET_FIFO_PERF__SHIFT 0x2 +#define DAGB0_CNTL_MISC2__DISABLE_RDRET_TAP_CHAIN_FGCG__SHIFT 0x3 +#define DAGB0_CNTL_MISC2__DISABLE_WRRET_TAP_CHAIN_FGCG__SHIFT 0x4 +#define DAGB0_CNTL_MISC2__DISABLE_MCA_INTR_REQ_FGCG__SHIFT 0x5 +#define DAGB0_CNTL_MISC2__DAGB_BUSY_OVERRIDE_MASK 0x00000001L +#define DAGB0_CNTL_MISC2__SWAP_CTL_MASK 0x00000002L +#define DAGB0_CNTL_MISC2__RDRET_FIFO_PERF_MASK 0x00000004L +#define DAGB0_CNTL_MISC2__DISABLE_RDRET_TAP_CHAIN_FGCG_MASK 0x00000008L +#define DAGB0_CNTL_MISC2__DISABLE_WRRET_TAP_CHAIN_FGCG_MASK 0x00000010L +#define DAGB0_CNTL_MISC2__DISABLE_MCA_INTR_REQ_FGCG_MASK 0x00000020L +//DAGB0_FIFO_EMPTY +#define DAGB0_FIFO_EMPTY__EMPTY__SHIFT 0x0 +#define DAGB0_FIFO_EMPTY__EMPTY_MASK 0xFFFFFFFFL +//DAGB0_FIFO_FULL +#define DAGB0_FIFO_FULL__FULL__SHIFT 0x0 +#define DAGB0_FIFO_FULL__FULL_MASK 0xFFFFFFFFL +//DAGB0_RD_CREDITS_FULL +#define DAGB0_RD_CREDITS_FULL__FULL__SHIFT 0x0 +#define DAGB0_RD_CREDITS_FULL__FULL_MASK 0x0000007FL +//DAGB0_WR_CREDITS_FULL +#define DAGB0_WR_CREDITS_FULL__FULL__SHIFT 0x0 +#define DAGB0_WR_CREDITS_FULL__FULL_MASK 0x0001FFFFL +//DAGB0_PERFCOUNTER_LO +#define DAGB0_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0 +#define DAGB0_PERFCOUNTER_LO__COUNTER_LO_MASK 0xFFFFFFFFL +//DAGB0_PERFCOUNTER_HI +#define DAGB0_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0 +#define DAGB0_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10 +#define DAGB0_PERFCOUNTER_HI__COUNTER_HI_MASK 0x0000FFFFL +#define DAGB0_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xFFFF0000L +//DAGB0_PERFCOUNTER0_CFG +#define DAGB0_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0 +#define DAGB0_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8 +#define DAGB0_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18 +#define DAGB0_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c +#define DAGB0_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d +#define DAGB0_PERFCOUNTER0_CFG__PERF_SEL_MASK 0x000000FFL +#define DAGB0_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0x0000FF00L +#define DAGB0_PERFCOUNTER0_CFG__PERF_MODE_MASK 0x0F000000L +#define DAGB0_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000L +#define DAGB0_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000L +//DAGB0_PERFCOUNTER1_CFG +#define DAGB0_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0 +#define DAGB0_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8 +#define DAGB0_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18 +#define DAGB0_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c +#define DAGB0_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d +#define DAGB0_PERFCOUNTER1_CFG__PERF_SEL_MASK 0x000000FFL +#define DAGB0_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0x0000FF00L +#define DAGB0_PERFCOUNTER1_CFG__PERF_MODE_MASK 0x0F000000L +#define DAGB0_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000L +#define DAGB0_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000L +//DAGB0_PERFCOUNTER2_CFG +#define DAGB0_PERFCOUNTER2_CFG__PERF_SEL__SHIFT 0x0 +#define DAGB0_PERFCOUNTER2_CFG__PERF_SEL_END__SHIFT 0x8 +#define DAGB0_PERFCOUNTER2_CFG__PERF_MODE__SHIFT 0x18 +#define DAGB0_PERFCOUNTER2_CFG__ENABLE__SHIFT 0x1c +#define DAGB0_PERFCOUNTER2_CFG__CLEAR__SHIFT 0x1d +#define DAGB0_PERFCOUNTER2_CFG__PERF_SEL_MASK 0x000000FFL +#define DAGB0_PERFCOUNTER2_CFG__PERF_SEL_END_MASK 0x0000FF00L +#define DAGB0_PERFCOUNTER2_CFG__PERF_MODE_MASK 0x0F000000L +#define DAGB0_PERFCOUNTER2_CFG__ENABLE_MASK 0x10000000L +#define DAGB0_PERFCOUNTER2_CFG__CLEAR_MASK 0x20000000L +//DAGB0_PERFCOUNTER_RSLT_CNTL +#define DAGB0_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0 +#define DAGB0_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8 +#define DAGB0_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10 +#define DAGB0_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18 +#define DAGB0_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19 +#define DAGB0_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a +#define DAGB0_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0x00000007L +#define DAGB0_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0x0000FF00L +#define DAGB0_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0x00FF0000L +#define DAGB0_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x01000000L +#define DAGB0_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x02000000L +#define DAGB0_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x04000000L +//DAGB0_L1TLB_REG_RW +#define DAGB0_L1TLB_REG_RW__REG_WRITE_L1TLB_CTRL__SHIFT 0x0 +#define DAGB0_L1TLB_REG_RW__REG_READ_L1TLB_CTRL__SHIFT 0x1 +#define DAGB0_L1TLB_REG_RW__REG_WRITE_L1TLB_CTRL_MASK 0x00000001L +#define DAGB0_L1TLB_REG_RW__REG_READ_L1TLB_CTRL_MASK 0x00000002L +//DAGB0_RESERVE0 +#define DAGB0_RESERVE0__RESERVE__SHIFT 0x0 +#define DAGB0_RESERVE0__RESERVE_MASK 0xFFFFFFFFL +//DAGB0_RESERVE1 +#define DAGB0_RESERVE1__RESERVE__SHIFT 0x0 +#define DAGB0_RESERVE1__RESERVE_MASK 0xFFFFFFFFL +//DAGB0_RESERVE2 +#define DAGB0_RESERVE2__RESERVE__SHIFT 0x0 +#define DAGB0_RESERVE2__RESERVE_MASK 0xFFFFFFFFL +//DAGB0_RESERVE3 +#define DAGB0_RESERVE3__RESERVE__SHIFT 0x0 +#define DAGB0_RESERVE3__RESERVE_MASK 0xFFFFFFFFL +//DAGB0_SDP_RD_BW_CNTL +#define DAGB0_SDP_RD_BW_CNTL__MAX_BW_ENABLE__SHIFT 0x0 +#define DAGB0_SDP_RD_BW_CNTL__MAX_BW__SHIFT 0x1 +#define DAGB0_SDP_RD_BW_CNTL__MIN_BW_ENABLE__SHIFT 0xc +#define DAGB0_SDP_RD_BW_CNTL__MIN_BW__SHIFT 0xd +#define DAGB0_SDP_RD_BW_CNTL__MAX_BW_WINDOW__SHIFT 0x13 +#define DAGB0_SDP_RD_BW_CNTL__MAX_BW_ENABLE_MASK 0x00000001L +#define DAGB0_SDP_RD_BW_CNTL__MAX_BW_MASK 0x000003FEL +#define DAGB0_SDP_RD_BW_CNTL__MIN_BW_ENABLE_MASK 0x00001000L +#define DAGB0_SDP_RD_BW_CNTL__MIN_BW_MASK 0x0007E000L +#define DAGB0_SDP_RD_BW_CNTL__MAX_BW_WINDOW_MASK 0x0FF80000L +//DAGB0_SDP_RD_PRIORITY +#define DAGB0_SDP_RD_PRIORITY__VC0__SHIFT 0x0 +#define DAGB0_SDP_RD_PRIORITY__VC1__SHIFT 0x4 +#define DAGB0_SDP_RD_PRIORITY__VC2__SHIFT 0x8 +#define DAGB0_SDP_RD_PRIORITY__VC3__SHIFT 0xc +#define DAGB0_SDP_RD_PRIORITY__VC4__SHIFT 0x10 +#define DAGB0_SDP_RD_PRIORITY__VC5__SHIFT 0x14 +#define DAGB0_SDP_RD_PRIORITY__VC6__SHIFT 0x18 +#define DAGB0_SDP_RD_PRIORITY__VC7__SHIFT 0x1c +#define DAGB0_SDP_RD_PRIORITY__VC0_MASK 0x0000000FL +#define DAGB0_SDP_RD_PRIORITY__VC1_MASK 0x000000F0L +#define DAGB0_SDP_RD_PRIORITY__VC2_MASK 0x00000F00L +#define DAGB0_SDP_RD_PRIORITY__VC3_MASK 0x0000F000L +#define DAGB0_SDP_RD_PRIORITY__VC4_MASK 0x000F0000L +#define DAGB0_SDP_RD_PRIORITY__VC5_MASK 0x00F00000L +#define DAGB0_SDP_RD_PRIORITY__VC6_MASK 0x0F000000L +#define DAGB0_SDP_RD_PRIORITY__VC7_MASK 0xF0000000L +//DAGB0_SDP_WR_PRIORITY +#define DAGB0_SDP_WR_PRIORITY__VC0__SHIFT 0x0 +#define DAGB0_SDP_WR_PRIORITY__VC1__SHIFT 0x4 +#define DAGB0_SDP_WR_PRIORITY__VC2__SHIFT 0x8 +#define DAGB0_SDP_WR_PRIORITY__VC3__SHIFT 0xc +#define DAGB0_SDP_WR_PRIORITY__VC4__SHIFT 0x10 +#define DAGB0_SDP_WR_PRIORITY__VC5__SHIFT 0x14 +#define DAGB0_SDP_WR_PRIORITY__VC6__SHIFT 0x18 +#define DAGB0_SDP_WR_PRIORITY__VC7__SHIFT 0x1c +#define DAGB0_SDP_WR_PRIORITY__VC0_MASK 0x0000000FL +#define DAGB0_SDP_WR_PRIORITY__VC1_MASK 0x000000F0L +#define DAGB0_SDP_WR_PRIORITY__VC2_MASK 0x00000F00L +#define DAGB0_SDP_WR_PRIORITY__VC3_MASK 0x0000F000L +#define DAGB0_SDP_WR_PRIORITY__VC4_MASK 0x000F0000L +#define DAGB0_SDP_WR_PRIORITY__VC5_MASK 0x00F00000L +#define DAGB0_SDP_WR_PRIORITY__VC6_MASK 0x0F000000L +#define DAGB0_SDP_WR_PRIORITY__VC7_MASK 0xF0000000L +//DAGB0_SDP_RD_CLI2SDP_VC_MAP +#define DAGB0_SDP_RD_CLI2SDP_VC_MAP__SRT_VC_MAP__SHIFT 0x0 +#define DAGB0_SDP_RD_CLI2SDP_VC_MAP__NRT_VC_MAP__SHIFT 0x3 +#define DAGB0_SDP_RD_CLI2SDP_VC_MAP__DLOCK_VC_MAP__SHIFT 0x6 +#define DAGB0_SDP_RD_CLI2SDP_VC_MAP__HRT_VC_MAP__SHIFT 0x9 +#define DAGB0_SDP_RD_CLI2SDP_VC_MAP__IO_VC_MAP__SHIFT 0xc +#define DAGB0_SDP_RD_CLI2SDP_VC_MAP__SRT_VC_MAP_MASK 0x00000007L +#define DAGB0_SDP_RD_CLI2SDP_VC_MAP__NRT_VC_MAP_MASK 0x00000038L +#define DAGB0_SDP_RD_CLI2SDP_VC_MAP__DLOCK_VC_MAP_MASK 0x000001C0L +#define DAGB0_SDP_RD_CLI2SDP_VC_MAP__HRT_VC_MAP_MASK 0x00000E00L +#define DAGB0_SDP_RD_CLI2SDP_VC_MAP__IO_VC_MAP_MASK 0x00007000L +//DAGB0_SDP_WR_CLI2SDP_VC_MAP +#define DAGB0_SDP_WR_CLI2SDP_VC_MAP__SRT_VC_MAP__SHIFT 0x0 +#define DAGB0_SDP_WR_CLI2SDP_VC_MAP__NRT_VC_MAP__SHIFT 0x3 +#define DAGB0_SDP_WR_CLI2SDP_VC_MAP__DLOCK_VC_MAP__SHIFT 0x6 +#define DAGB0_SDP_WR_CLI2SDP_VC_MAP__HRT_VC_MAP__SHIFT 0x9 +#define DAGB0_SDP_WR_CLI2SDP_VC_MAP__IO_VC_MAP__SHIFT 0xc +#define DAGB0_SDP_WR_CLI2SDP_VC_MAP__SRT_VC_MAP_MASK 0x00000007L +#define DAGB0_SDP_WR_CLI2SDP_VC_MAP__NRT_VC_MAP_MASK 0x00000038L +#define DAGB0_SDP_WR_CLI2SDP_VC_MAP__DLOCK_VC_MAP_MASK 0x000001C0L +#define DAGB0_SDP_WR_CLI2SDP_VC_MAP__HRT_VC_MAP_MASK 0x00000E00L +#define DAGB0_SDP_WR_CLI2SDP_VC_MAP__IO_VC_MAP_MASK 0x00007000L +//DAGB0_SDP_ENABLE +#define DAGB0_SDP_ENABLE__ENABLE__SHIFT 0x0 +#define DAGB0_SDP_ENABLE__ENABLE_MASK 0x00000001L +//DAGB0_SDP_CREDITS +#define DAGB0_SDP_CREDITS__TAG_LIMIT__SHIFT 0x0 +#define DAGB0_SDP_CREDITS__WR_RESP_CREDITS__SHIFT 0x8 +#define DAGB0_SDP_CREDITS__RD_RESP_CREDITS__SHIFT 0x10 +#define DAGB0_SDP_CREDITS__TAG_LIMIT_MASK 0x000000FFL +#define DAGB0_SDP_CREDITS__WR_RESP_CREDITS_MASK 0x00007F00L +#define DAGB0_SDP_CREDITS__RD_RESP_CREDITS_MASK 0x01FF0000L +//DAGB0_SDP_TAG_RESERVE0 +#define DAGB0_SDP_TAG_RESERVE0__VC0__SHIFT 0x0 +#define DAGB0_SDP_TAG_RESERVE0__VC1__SHIFT 0x8 +#define DAGB0_SDP_TAG_RESERVE0__VC2__SHIFT 0x10 +#define DAGB0_SDP_TAG_RESERVE0__VC3__SHIFT 0x18 +#define DAGB0_SDP_TAG_RESERVE0__VC0_MASK 0x000000FFL +#define DAGB0_SDP_TAG_RESERVE0__VC1_MASK 0x0000FF00L +#define DAGB0_SDP_TAG_RESERVE0__VC2_MASK 0x00FF0000L +#define DAGB0_SDP_TAG_RESERVE0__VC3_MASK 0xFF000000L +//DAGB0_SDP_TAG_RESERVE1 +#define DAGB0_SDP_TAG_RESERVE1__VC4__SHIFT 0x0 +#define DAGB0_SDP_TAG_RESERVE1__VC5__SHIFT 0x8 +#define DAGB0_SDP_TAG_RESERVE1__VC6__SHIFT 0x10 +#define DAGB0_SDP_TAG_RESERVE1__VC7__SHIFT 0x18 +#define DAGB0_SDP_TAG_RESERVE1__VC4_MASK 0x000000FFL +#define DAGB0_SDP_TAG_RESERVE1__VC5_MASK 0x0000FF00L +#define DAGB0_SDP_TAG_RESERVE1__VC6_MASK 0x00FF0000L +#define DAGB0_SDP_TAG_RESERVE1__VC7_MASK 0xFF000000L +//DAGB0_SDP_VCC_RESERVE0 +#define DAGB0_SDP_VCC_RESERVE0__VC0_CREDITS__SHIFT 0x0 +#define DAGB0_SDP_VCC_RESERVE0__VC1_CREDITS__SHIFT 0x6 +#define DAGB0_SDP_VCC_RESERVE0__VC2_CREDITS__SHIFT 0xc +#define DAGB0_SDP_VCC_RESERVE0__VC3_CREDITS__SHIFT 0x12 +#define DAGB0_SDP_VCC_RESERVE0__VC4_CREDITS__SHIFT 0x18 +#define DAGB0_SDP_VCC_RESERVE0__VC0_CREDITS_MASK 0x0000003FL +#define DAGB0_SDP_VCC_RESERVE0__VC1_CREDITS_MASK 0x00000FC0L +#define DAGB0_SDP_VCC_RESERVE0__VC2_CREDITS_MASK 0x0003F000L +#define DAGB0_SDP_VCC_RESERVE0__VC3_CREDITS_MASK 0x00FC0000L +#define DAGB0_SDP_VCC_RESERVE0__VC4_CREDITS_MASK 0x3F000000L +//DAGB0_SDP_VCC_RESERVE1 +#define DAGB0_SDP_VCC_RESERVE1__VC5_CREDITS__SHIFT 0x0 +#define DAGB0_SDP_VCC_RESERVE1__VC6_CREDITS__SHIFT 0x6 +#define DAGB0_SDP_VCC_RESERVE1__VC7_CREDITS__SHIFT 0xc +#define DAGB0_SDP_VCC_RESERVE1__DISTRIBUTE_POOL__SHIFT 0x1f +#define DAGB0_SDP_VCC_RESERVE1__VC5_CREDITS_MASK 0x0000003FL +#define DAGB0_SDP_VCC_RESERVE1__VC6_CREDITS_MASK 0x00000FC0L +#define DAGB0_SDP_VCC_RESERVE1__VC7_CREDITS_MASK 0x0003F000L +#define DAGB0_SDP_VCC_RESERVE1__DISTRIBUTE_POOL_MASK 0x80000000L +//DAGB0_SDP_REQ_CNTL +#define DAGB0_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_READ__SHIFT 0x0 +#define DAGB0_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_WRITE__SHIFT 0x1 +#define DAGB0_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_ATOMIC__SHIFT 0x2 +#define DAGB0_SDP_REQ_CNTL__REQ_CHAIN_OVERRIDE_DRAM__SHIFT 0x3 +#define DAGB0_SDP_REQ_CNTL__REQ_CHAIN_OVERRIDE_GMI__SHIFT 0x4 +#define DAGB0_SDP_REQ_CNTL__INNER_DOMAIN_MODE__SHIFT 0x5 +#define DAGB0_SDP_REQ_CNTL__OVERRIDE_DOMAIN_EN__SHIFT 0x6 +#define DAGB0_SDP_REQ_CNTL__OVERRIDE_DOMAIN__SHIFT 0x7 +#define DAGB0_SDP_REQ_CNTL__REQ_BLOCK_LEVEL_READ__SHIFT 0x8 +#define DAGB0_SDP_REQ_CNTL__REQ_BLOCK_LEVEL_WRITE__SHIFT 0xa +#define DAGB0_SDP_REQ_CNTL__REQ_BLOCK_LEVEL_ATOMIC__SHIFT 0xc +#define DAGB0_SDP_REQ_CNTL__DRAM_LEGACY_WR_64B_ALIGN__SHIFT 0xe +#define DAGB0_SDP_REQ_CNTL__DRAM_LARGE_WR_64B_UPSIZE__SHIFT 0xf +#define DAGB0_SDP_REQ_CNTL__DRAM_RD_64B_ALIGN_UPSIZE__SHIFT 0x10 +#define DAGB0_SDP_REQ_CNTL__IO_LEGACY_WR_64B_ALIGN__SHIFT 0x12 +#define DAGB0_SDP_REQ_CNTL__IO_LARGE_WR_64B_UPSIZE__SHIFT 0x13 +#define DAGB0_SDP_REQ_CNTL__IO_RD_64B_ALIGN_UPSIZE__SHIFT 0x14 +#define DAGB0_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_READ_MASK 0x00000001L +#define DAGB0_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_WRITE_MASK 0x00000002L +#define DAGB0_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_ATOMIC_MASK 0x00000004L +#define DAGB0_SDP_REQ_CNTL__REQ_CHAIN_OVERRIDE_DRAM_MASK 0x00000008L +#define DAGB0_SDP_REQ_CNTL__REQ_CHAIN_OVERRIDE_GMI_MASK 0x00000010L +#define DAGB0_SDP_REQ_CNTL__INNER_DOMAIN_MODE_MASK 0x00000020L +#define DAGB0_SDP_REQ_CNTL__OVERRIDE_DOMAIN_EN_MASK 0x00000040L +#define DAGB0_SDP_REQ_CNTL__OVERRIDE_DOMAIN_MASK 0x00000080L +#define DAGB0_SDP_REQ_CNTL__REQ_BLOCK_LEVEL_READ_MASK 0x00000300L +#define DAGB0_SDP_REQ_CNTL__REQ_BLOCK_LEVEL_WRITE_MASK 0x00000C00L +#define DAGB0_SDP_REQ_CNTL__REQ_BLOCK_LEVEL_ATOMIC_MASK 0x00003000L +#define DAGB0_SDP_REQ_CNTL__DRAM_LEGACY_WR_64B_ALIGN_MASK 0x00004000L +#define DAGB0_SDP_REQ_CNTL__DRAM_LARGE_WR_64B_UPSIZE_MASK 0x00008000L +#define DAGB0_SDP_REQ_CNTL__DRAM_RD_64B_ALIGN_UPSIZE_MASK 0x00030000L +#define DAGB0_SDP_REQ_CNTL__IO_LEGACY_WR_64B_ALIGN_MASK 0x00040000L +#define DAGB0_SDP_REQ_CNTL__IO_LARGE_WR_64B_UPSIZE_MASK 0x00080000L +#define DAGB0_SDP_REQ_CNTL__IO_RD_64B_ALIGN_UPSIZE_MASK 0x00300000L +//DAGB0_SDP_MISC_AON +#define DAGB0_SDP_MISC_AON__LINKMGR_PARTACK_HYSTERESIS__SHIFT 0x0 +#define DAGB0_SDP_MISC_AON__LINKMGR_PARTACK_DEASSERT_MODE__SHIFT 0x2 +#define DAGB0_SDP_MISC_AON__LINKMGR_PARTACK_HYSTERESIS_MASK 0x00000003L +#define DAGB0_SDP_MISC_AON__LINKMGR_PARTACK_DEASSERT_MODE_MASK 0x00000004L +//DAGB0_SDP_MISC +#define DAGB0_SDP_MISC__EARLYWRRET_ENABLE_VC0__SHIFT 0x0 +#define DAGB0_SDP_MISC__EARLYWRRET_ENABLE_VC1__SHIFT 0x1 +#define DAGB0_SDP_MISC__EARLYWRRET_ENABLE_VC2__SHIFT 0x2 +#define DAGB0_SDP_MISC__EARLYWRRET_ENABLE_VC3__SHIFT 0x3 +#define DAGB0_SDP_MISC__EARLYWRRET_ENABLE_VC4__SHIFT 0x4 +#define DAGB0_SDP_MISC__EARLYWRRET_ENABLE_VC5__SHIFT 0x5 +#define DAGB0_SDP_MISC__EARLYWRRET_ENABLE_VC6__SHIFT 0x6 +#define DAGB0_SDP_MISC__EARLYWRRET_ENABLE_VC7__SHIFT 0x7 +#define DAGB0_SDP_MISC__EARLY_SDP_ORIGDATA__SHIFT 0x8 +#define DAGB0_SDP_MISC__LINKMGR_DYNAMIC_MODE__SHIFT 0x9 +#define DAGB0_SDP_MISC__LINKMGR_HALT_THRESHOLD__SHIFT 0xb +#define DAGB0_SDP_MISC__LINKMGR_RECONNECT_DELAY__SHIFT 0xd +#define DAGB0_SDP_MISC__LINKMGR_IDLE_THRESHOLD__SHIFT 0xf +#define DAGB0_SDP_MISC__SDP_DAT_FIFO0_MARGIN__SHIFT 0x14 +#define DAGB0_SDP_MISC__SDP_DAT_FIFO1_MARGIN__SHIFT 0x16 +#define DAGB0_SDP_MISC__SDP_DAT_FIFO2_MARGIN__SHIFT 0x18 +#define DAGB0_SDP_MISC__EARLYWRRET_ENABLE_VC0_MASK 0x00000001L +#define DAGB0_SDP_MISC__EARLYWRRET_ENABLE_VC1_MASK 0x00000002L +#define DAGB0_SDP_MISC__EARLYWRRET_ENABLE_VC2_MASK 0x00000004L +#define DAGB0_SDP_MISC__EARLYWRRET_ENABLE_VC3_MASK 0x00000008L +#define DAGB0_SDP_MISC__EARLYWRRET_ENABLE_VC4_MASK 0x00000010L +#define DAGB0_SDP_MISC__EARLYWRRET_ENABLE_VC5_MASK 0x00000020L +#define DAGB0_SDP_MISC__EARLYWRRET_ENABLE_VC6_MASK 0x00000040L +#define DAGB0_SDP_MISC__EARLYWRRET_ENABLE_VC7_MASK 0x00000080L +#define DAGB0_SDP_MISC__EARLY_SDP_ORIGDATA_MASK 0x00000100L +#define DAGB0_SDP_MISC__LINKMGR_DYNAMIC_MODE_MASK 0x00000600L +#define DAGB0_SDP_MISC__LINKMGR_HALT_THRESHOLD_MASK 0x00001800L +#define DAGB0_SDP_MISC__LINKMGR_RECONNECT_DELAY_MASK 0x00006000L +#define DAGB0_SDP_MISC__LINKMGR_IDLE_THRESHOLD_MASK 0x000F8000L +#define DAGB0_SDP_MISC__SDP_DAT_FIFO0_MARGIN_MASK 0x00300000L +#define DAGB0_SDP_MISC__SDP_DAT_FIFO1_MARGIN_MASK 0x00C00000L +#define DAGB0_SDP_MISC__SDP_DAT_FIFO2_MARGIN_MASK 0x07000000L +//DAGB0_SDP_MISC2 +#define DAGB0_SDP_MISC2__RRET_SWAP_MODE__SHIFT 0x0 +#define DAGB0_SDP_MISC2__BLOCK_REQUESTS__SHIFT 0x1 +#define DAGB0_SDP_MISC2__REQUESTS_BLOCKED__SHIFT 0x2 +#define DAGB0_SDP_MISC2__RRET_SWAP_MODE_MASK 0x00000001L +#define DAGB0_SDP_MISC2__BLOCK_REQUESTS_MASK 0x00000002L +#define DAGB0_SDP_MISC2__REQUESTS_BLOCKED_MASK 0x00000004L +//DAGB0_SDP_VCD_RESERVE0 +#define DAGB0_SDP_VCD_RESERVE0__VC0_CREDITS__SHIFT 0x0 +#define DAGB0_SDP_VCD_RESERVE0__VC1_CREDITS__SHIFT 0x6 +#define DAGB0_SDP_VCD_RESERVE0__VC2_CREDITS__SHIFT 0xc +#define DAGB0_SDP_VCD_RESERVE0__VC3_CREDITS__SHIFT 0x12 +#define DAGB0_SDP_VCD_RESERVE0__VC4_CREDITS__SHIFT 0x18 +#define DAGB0_SDP_VCD_RESERVE0__RESERVE__SHIFT 0x1e +#define DAGB0_SDP_VCD_RESERVE0__VC0_CREDITS_MASK 0x0000003FL +#define DAGB0_SDP_VCD_RESERVE0__VC1_CREDITS_MASK 0x00000FC0L +#define DAGB0_SDP_VCD_RESERVE0__VC2_CREDITS_MASK 0x0003F000L +#define DAGB0_SDP_VCD_RESERVE0__VC3_CREDITS_MASK 0x00FC0000L +#define DAGB0_SDP_VCD_RESERVE0__VC4_CREDITS_MASK 0x3F000000L +#define DAGB0_SDP_VCD_RESERVE0__RESERVE_MASK 0x40000000L +//DAGB0_SDP_VCD_RESERVE1 +#define DAGB0_SDP_VCD_RESERVE1__VC5_CREDITS__SHIFT 0x0 +#define DAGB0_SDP_VCD_RESERVE1__VC6_CREDITS__SHIFT 0x6 +#define DAGB0_SDP_VCD_RESERVE1__VC7_CREDITS__SHIFT 0xc +#define DAGB0_SDP_VCD_RESERVE1__DISTRIBUTE_POOL__SHIFT 0x1f +#define DAGB0_SDP_VCD_RESERVE1__VC5_CREDITS_MASK 0x0000003FL +#define DAGB0_SDP_VCD_RESERVE1__VC6_CREDITS_MASK 0x00000FC0L +#define DAGB0_SDP_VCD_RESERVE1__VC7_CREDITS_MASK 0x0003F000L +#define DAGB0_SDP_VCD_RESERVE1__DISTRIBUTE_POOL_MASK 0x80000000L +//DAGB0_SDP_ARB_CNTL0 +#define DAGB0_SDP_ARB_CNTL0__EARLY_SW2RD_ON_PRI__SHIFT 0x0 +#define DAGB0_SDP_ARB_CNTL0__EARLY_SW2WR_ON_PRI__SHIFT 0x1 +#define DAGB0_SDP_ARB_CNTL0__EARLY_SW2RD_ON_RES__SHIFT 0x2 +#define DAGB0_SDP_ARB_CNTL0__EARLY_SW2WR_ON_RES__SHIFT 0x3 +#define DAGB0_SDP_ARB_CNTL0__EARLY_SW2RD_ON_PRI_MASK 0x00000001L +#define DAGB0_SDP_ARB_CNTL0__EARLY_SW2WR_ON_PRI_MASK 0x00000002L +#define DAGB0_SDP_ARB_CNTL0__EARLY_SW2RD_ON_RES_MASK 0x00000004L +#define DAGB0_SDP_ARB_CNTL0__EARLY_SW2WR_ON_RES_MASK 0x00000008L +//DAGB0_SDP_ARB_CNTL1 +#define DAGB0_SDP_ARB_CNTL1__RD_BURST_LIMIT_CYCL__SHIFT 0x0 +#define DAGB0_SDP_ARB_CNTL1__WR_BURST_LIMIT_CYCL__SHIFT 0x7 +#define DAGB0_SDP_ARB_CNTL1__RD_BURST_LIMIT_DATA__SHIFT 0xe +#define DAGB0_SDP_ARB_CNTL1__WR_BURST_LIMIT_DATA__SHIFT 0x14 +#define DAGB0_SDP_ARB_CNTL1__RD_BURST_LIMIT_CYCL_MASK 0x0000007FL +#define DAGB0_SDP_ARB_CNTL1__WR_BURST_LIMIT_CYCL_MASK 0x00003F80L +#define DAGB0_SDP_ARB_CNTL1__RD_BURST_LIMIT_DATA_MASK 0x000FC000L +#define DAGB0_SDP_ARB_CNTL1__WR_BURST_LIMIT_DATA_MASK 0x03F00000L +//DAGB0_FATAL_ERROR_CLEAR +#define DAGB0_FATAL_ERROR_CLEAR__CLEAR__SHIFT 0x0 +#define DAGB0_FATAL_ERROR_CLEAR__CLEAR_MASK 0x00000001L +//DAGB0_FATAL_ERROR_STATUS0 +#define DAGB0_FATAL_ERROR_STATUS0__ADDR_HI__SHIFT 0x0 +#define DAGB0_FATAL_ERROR_STATUS0__PARITY_ERROR__SHIFT 0x1f +#define DAGB0_FATAL_ERROR_STATUS0__ADDR_HI_MASK 0x00000FFFL +#define DAGB0_FATAL_ERROR_STATUS0__PARITY_ERROR_MASK 0x80000000L +//DAGB0_FATAL_ERROR_STATUS1 +#define DAGB0_FATAL_ERROR_STATUS1__CID__SHIFT 0x0 +#define DAGB0_FATAL_ERROR_STATUS1__ADDR_LO__SHIFT 0x5 +#define DAGB0_FATAL_ERROR_STATUS1__CID_MASK 0x0000001FL +#define DAGB0_FATAL_ERROR_STATUS1__ADDR_LO_MASK 0xFFFFFFE0L +//DAGB0_FATAL_ERROR_STATUS2 +#define DAGB0_FATAL_ERROR_STATUS2__CLI_TAG__SHIFT 0x0 +#define DAGB0_FATAL_ERROR_STATUS2__SDP_TAG__SHIFT 0x10 +#define DAGB0_FATAL_ERROR_STATUS2__VFID__SHIFT 0x19 +#define DAGB0_FATAL_ERROR_STATUS2__VF__SHIFT 0x1e +#define DAGB0_FATAL_ERROR_STATUS2__CLI_TAG_MASK 0x0000FFFFL +#define DAGB0_FATAL_ERROR_STATUS2__SDP_TAG_MASK 0x01FF0000L +#define DAGB0_FATAL_ERROR_STATUS2__VFID_MASK 0x3E000000L +#define DAGB0_FATAL_ERROR_STATUS2__VF_MASK 0x40000000L +//DAGB0_FATAL_ERROR_STATUS3 +#define DAGB0_FATAL_ERROR_STATUS3__UNITID__SHIFT 0x0 +#define DAGB0_FATAL_ERROR_STATUS3__OP__SHIFT 0x6 +#define DAGB0_FATAL_ERROR_STATUS3__SECLEVEL__SHIFT 0xd +#define DAGB0_FATAL_ERROR_STATUS3__WRTMZ__SHIFT 0x11 +#define DAGB0_FATAL_ERROR_STATUS3__RDTMZ__SHIFT 0x12 +#define DAGB0_FATAL_ERROR_STATUS3__SNOOP__SHIFT 0x13 +#define DAGB0_FATAL_ERROR_STATUS3__INVAL__SHIFT 0x14 +#define DAGB0_FATAL_ERROR_STATUS3__NACK__SHIFT 0x15 +#define DAGB0_FATAL_ERROR_STATUS3__RO__SHIFT 0x17 +#define DAGB0_FATAL_ERROR_STATUS3__MEMLOG__SHIFT 0x18 +#define DAGB0_FATAL_ERROR_STATUS3__INT_FATAL__SHIFT 0x19 +#define DAGB0_FATAL_ERROR_STATUS3__EXT_FATAL__SHIFT 0x1a +#define DAGB0_FATAL_ERROR_STATUS3__UNITID_MASK 0x0000003FL +#define DAGB0_FATAL_ERROR_STATUS3__OP_MASK 0x00001FC0L +#define DAGB0_FATAL_ERROR_STATUS3__SECLEVEL_MASK 0x0001E000L +#define DAGB0_FATAL_ERROR_STATUS3__WRTMZ_MASK 0x00020000L +#define DAGB0_FATAL_ERROR_STATUS3__RDTMZ_MASK 0x00040000L +#define DAGB0_FATAL_ERROR_STATUS3__SNOOP_MASK 0x00080000L +#define DAGB0_FATAL_ERROR_STATUS3__INVAL_MASK 0x00100000L +#define DAGB0_FATAL_ERROR_STATUS3__NACK_MASK 0x00600000L +#define DAGB0_FATAL_ERROR_STATUS3__RO_MASK 0x00800000L +#define DAGB0_FATAL_ERROR_STATUS3__MEMLOG_MASK 0x01000000L +#define DAGB0_FATAL_ERROR_STATUS3__INT_FATAL_MASK 0x02000000L +#define DAGB0_FATAL_ERROR_STATUS3__EXT_FATAL_MASK 0x04000000L +//DAGB0_FATAL_ERROR_STATUS4 +#define DAGB0_FATAL_ERROR_STATUS4__PRI__SHIFT 0x0 +#define DAGB0_FATAL_ERROR_STATUS4__CHAIN__SHIFT 0x4 +#define DAGB0_FATAL_ERROR_STATUS4__FULL__SHIFT 0x5 +#define DAGB0_FATAL_ERROR_STATUS4__DROP__SHIFT 0x6 +#define DAGB0_FATAL_ERROR_STATUS4__SPACE__SHIFT 0x7 +#define DAGB0_FATAL_ERROR_STATUS4__IO__SHIFT 0x8 +#define DAGB0_FATAL_ERROR_STATUS4__SIZE__SHIFT 0x9 +#define DAGB0_FATAL_ERROR_STATUS4__REUSE_HINT__SHIFT 0xa +#define DAGB0_FATAL_ERROR_STATUS4__PRI_MASK 0x0000000FL +#define DAGB0_FATAL_ERROR_STATUS4__CHAIN_MASK 0x00000010L +#define DAGB0_FATAL_ERROR_STATUS4__FULL_MASK 0x00000020L +#define DAGB0_FATAL_ERROR_STATUS4__DROP_MASK 0x00000040L +#define DAGB0_FATAL_ERROR_STATUS4__SPACE_MASK 0x00000080L +#define DAGB0_FATAL_ERROR_STATUS4__IO_MASK 0x00000100L +#define DAGB0_FATAL_ERROR_STATUS4__SIZE_MASK 0x00000200L +#define DAGB0_FATAL_ERROR_STATUS4__REUSE_HINT_MASK 0x00000C00L +//DAGB0_SDP_CGTT_CLK_CTRL +#define DAGB0_SDP_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 +#define DAGB0_SDP_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x5 +#define DAGB0_SDP_CGTT_CLK_CTRL__LS_ASSERT_HYSTERESIS__SHIFT 0xd +#define DAGB0_SDP_CGTT_CLK_CTRL__MIN_MGLS__SHIFT 0x1a +#define DAGB0_SDP_CGTT_CLK_CTRL__CGLS_DISABLE__SHIFT 0x1d +#define DAGB0_SDP_CGTT_CLK_CTRL__LS_DISABLE__SHIFT 0x1e +#define DAGB0_SDP_CGTT_CLK_CTRL__BUSY_OVERRIDE__SHIFT 0x1f +#define DAGB0_SDP_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000001FL +#define DAGB0_SDP_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00001FE0L +#define DAGB0_SDP_CGTT_CLK_CTRL__LS_ASSERT_HYSTERESIS_MASK 0x03FFE000L +#define DAGB0_SDP_CGTT_CLK_CTRL__MIN_MGLS_MASK 0x1C000000L +#define DAGB0_SDP_CGTT_CLK_CTRL__CGLS_DISABLE_MASK 0x20000000L +#define DAGB0_SDP_CGTT_CLK_CTRL__LS_DISABLE_MASK 0x40000000L +#define DAGB0_SDP_CGTT_CLK_CTRL__BUSY_OVERRIDE_MASK 0x80000000L +//DAGB0_SDP_LATENCY_SAMPLING +#define DAGB0_SDP_LATENCY_SAMPLING__SAMPLER0_DRAM__SHIFT 0x0 +#define DAGB0_SDP_LATENCY_SAMPLING__SAMPLER1_DRAM__SHIFT 0x1 +#define DAGB0_SDP_LATENCY_SAMPLING__SAMPLER0_GMI__SHIFT 0x2 +#define DAGB0_SDP_LATENCY_SAMPLING__SAMPLER1_GMI__SHIFT 0x3 +#define DAGB0_SDP_LATENCY_SAMPLING__SAMPLER0_IO__SHIFT 0x4 +#define DAGB0_SDP_LATENCY_SAMPLING__SAMPLER1_IO__SHIFT 0x5 +#define DAGB0_SDP_LATENCY_SAMPLING__SAMPLER0_READ__SHIFT 0x6 +#define DAGB0_SDP_LATENCY_SAMPLING__SAMPLER1_READ__SHIFT 0x7 +#define DAGB0_SDP_LATENCY_SAMPLING__SAMPLER0_WRITE__SHIFT 0x8 +#define DAGB0_SDP_LATENCY_SAMPLING__SAMPLER1_WRITE__SHIFT 0x9 +#define DAGB0_SDP_LATENCY_SAMPLING__SAMPLER0_ATOMIC_RET__SHIFT 0xa +#define DAGB0_SDP_LATENCY_SAMPLING__SAMPLER1_ATOMIC_RET__SHIFT 0xb +#define DAGB0_SDP_LATENCY_SAMPLING__SAMPLER0_ATOMIC_NORET__SHIFT 0xc +#define DAGB0_SDP_LATENCY_SAMPLING__SAMPLER1_ATOMIC_NORET__SHIFT 0xd +#define DAGB0_SDP_LATENCY_SAMPLING__SAMPLER0_VC__SHIFT 0xe +#define DAGB0_SDP_LATENCY_SAMPLING__SAMPLER1_VC__SHIFT 0x16 +#define DAGB0_SDP_LATENCY_SAMPLING__SAMPLER0_DRAM_MASK 0x00000001L +#define DAGB0_SDP_LATENCY_SAMPLING__SAMPLER1_DRAM_MASK 0x00000002L +#define DAGB0_SDP_LATENCY_SAMPLING__SAMPLER0_GMI_MASK 0x00000004L +#define DAGB0_SDP_LATENCY_SAMPLING__SAMPLER1_GMI_MASK 0x00000008L +#define DAGB0_SDP_LATENCY_SAMPLING__SAMPLER0_IO_MASK 0x00000010L +#define DAGB0_SDP_LATENCY_SAMPLING__SAMPLER1_IO_MASK 0x00000020L +#define DAGB0_SDP_LATENCY_SAMPLING__SAMPLER0_READ_MASK 0x00000040L +#define DAGB0_SDP_LATENCY_SAMPLING__SAMPLER1_READ_MASK 0x00000080L +#define DAGB0_SDP_LATENCY_SAMPLING__SAMPLER0_WRITE_MASK 0x00000100L +#define DAGB0_SDP_LATENCY_SAMPLING__SAMPLER1_WRITE_MASK 0x00000200L +#define DAGB0_SDP_LATENCY_SAMPLING__SAMPLER0_ATOMIC_RET_MASK 0x00000400L +#define DAGB0_SDP_LATENCY_SAMPLING__SAMPLER1_ATOMIC_RET_MASK 0x00000800L +#define DAGB0_SDP_LATENCY_SAMPLING__SAMPLER0_ATOMIC_NORET_MASK 0x00001000L +#define DAGB0_SDP_LATENCY_SAMPLING__SAMPLER1_ATOMIC_NORET_MASK 0x00002000L +#define DAGB0_SDP_LATENCY_SAMPLING__SAMPLER0_VC_MASK 0x003FC000L +#define DAGB0_SDP_LATENCY_SAMPLING__SAMPLER1_VC_MASK 0x3FC00000L +//DAGB0_WRCLI_GPU_SNOOP_OVERRIDE +#define DAGB0_WRCLI_GPU_SNOOP_OVERRIDE__ENABLE__SHIFT 0x0 +#define DAGB0_WRCLI_GPU_SNOOP_OVERRIDE__ENABLE_MASK 0x00FFFFFFL +//DAGB0_WRCLI_GPU_SNOOP_OVERRIDE_VALUE +#define DAGB0_WRCLI_GPU_SNOOP_OVERRIDE_VALUE__ENABLE__SHIFT 0x0 +#define DAGB0_WRCLI_GPU_SNOOP_OVERRIDE_VALUE__ENABLE_MASK 0x00FFFFFFL +//DAGB1_RDCLI0 +#define DAGB1_RDCLI0__TC__SHIFT 0x0 +#define DAGB1_RDCLI0__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB1_RDCLI0__PRIORITY_ARB1__SHIFT 0x4 +#define DAGB1_RDCLI0__PROFILE_ARB2__SHIFT 0x8 +#define DAGB1_RDCLI0__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB1_RDCLI0__MAX_BW__SHIFT 0xd +#define DAGB1_RDCLI0__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB1_RDCLI0__MIN_BW__SHIFT 0x16 +#define DAGB1_RDCLI0__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB1_RDCLI0__MAX_OSD__SHIFT 0x1a +#define DAGB1_RDCLI0__TC_MASK 0x00000007L +#define DAGB1_RDCLI0__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB1_RDCLI0__PRIORITY_ARB1_MASK 0x000000F0L +#define DAGB1_RDCLI0__PROFILE_ARB2_MASK 0x00000700L +#define DAGB1_RDCLI0__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB1_RDCLI0__MAX_BW_MASK 0x001FE000L +#define DAGB1_RDCLI0__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB1_RDCLI0__MIN_BW_MASK 0x01C00000L +#define DAGB1_RDCLI0__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB1_RDCLI0__MAX_OSD_MASK 0xFC000000L +//DAGB1_RDCLI1 +#define DAGB1_RDCLI1__TC__SHIFT 0x0 +#define DAGB1_RDCLI1__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB1_RDCLI1__PRIORITY_ARB1__SHIFT 0x4 +#define DAGB1_RDCLI1__PROFILE_ARB2__SHIFT 0x8 +#define DAGB1_RDCLI1__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB1_RDCLI1__MAX_BW__SHIFT 0xd +#define DAGB1_RDCLI1__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB1_RDCLI1__MIN_BW__SHIFT 0x16 +#define DAGB1_RDCLI1__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB1_RDCLI1__MAX_OSD__SHIFT 0x1a +#define DAGB1_RDCLI1__TC_MASK 0x00000007L +#define DAGB1_RDCLI1__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB1_RDCLI1__PRIORITY_ARB1_MASK 0x000000F0L +#define DAGB1_RDCLI1__PROFILE_ARB2_MASK 0x00000700L +#define DAGB1_RDCLI1__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB1_RDCLI1__MAX_BW_MASK 0x001FE000L +#define DAGB1_RDCLI1__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB1_RDCLI1__MIN_BW_MASK 0x01C00000L +#define DAGB1_RDCLI1__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB1_RDCLI1__MAX_OSD_MASK 0xFC000000L +//DAGB1_RDCLI2 +#define DAGB1_RDCLI2__TC__SHIFT 0x0 +#define DAGB1_RDCLI2__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB1_RDCLI2__PRIORITY_ARB1__SHIFT 0x4 +#define DAGB1_RDCLI2__PROFILE_ARB2__SHIFT 0x8 +#define DAGB1_RDCLI2__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB1_RDCLI2__MAX_BW__SHIFT 0xd +#define DAGB1_RDCLI2__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB1_RDCLI2__MIN_BW__SHIFT 0x16 +#define DAGB1_RDCLI2__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB1_RDCLI2__MAX_OSD__SHIFT 0x1a +#define DAGB1_RDCLI2__TC_MASK 0x00000007L +#define DAGB1_RDCLI2__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB1_RDCLI2__PRIORITY_ARB1_MASK 0x000000F0L +#define DAGB1_RDCLI2__PROFILE_ARB2_MASK 0x00000700L +#define DAGB1_RDCLI2__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB1_RDCLI2__MAX_BW_MASK 0x001FE000L +#define DAGB1_RDCLI2__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB1_RDCLI2__MIN_BW_MASK 0x01C00000L +#define DAGB1_RDCLI2__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB1_RDCLI2__MAX_OSD_MASK 0xFC000000L +//DAGB1_RDCLI3 +#define DAGB1_RDCLI3__TC__SHIFT 0x0 +#define DAGB1_RDCLI3__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB1_RDCLI3__PRIORITY_ARB1__SHIFT 0x4 +#define DAGB1_RDCLI3__PROFILE_ARB2__SHIFT 0x8 +#define DAGB1_RDCLI3__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB1_RDCLI3__MAX_BW__SHIFT 0xd +#define DAGB1_RDCLI3__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB1_RDCLI3__MIN_BW__SHIFT 0x16 +#define DAGB1_RDCLI3__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB1_RDCLI3__MAX_OSD__SHIFT 0x1a +#define DAGB1_RDCLI3__TC_MASK 0x00000007L +#define DAGB1_RDCLI3__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB1_RDCLI3__PRIORITY_ARB1_MASK 0x000000F0L +#define DAGB1_RDCLI3__PROFILE_ARB2_MASK 0x00000700L +#define DAGB1_RDCLI3__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB1_RDCLI3__MAX_BW_MASK 0x001FE000L +#define DAGB1_RDCLI3__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB1_RDCLI3__MIN_BW_MASK 0x01C00000L +#define DAGB1_RDCLI3__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB1_RDCLI3__MAX_OSD_MASK 0xFC000000L +//DAGB1_RDCLI4 +#define DAGB1_RDCLI4__TC__SHIFT 0x0 +#define DAGB1_RDCLI4__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB1_RDCLI4__PRIORITY_ARB1__SHIFT 0x4 +#define DAGB1_RDCLI4__PROFILE_ARB2__SHIFT 0x8 +#define DAGB1_RDCLI4__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB1_RDCLI4__MAX_BW__SHIFT 0xd +#define DAGB1_RDCLI4__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB1_RDCLI4__MIN_BW__SHIFT 0x16 +#define DAGB1_RDCLI4__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB1_RDCLI4__MAX_OSD__SHIFT 0x1a +#define DAGB1_RDCLI4__TC_MASK 0x00000007L +#define DAGB1_RDCLI4__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB1_RDCLI4__PRIORITY_ARB1_MASK 0x000000F0L +#define DAGB1_RDCLI4__PROFILE_ARB2_MASK 0x00000700L +#define DAGB1_RDCLI4__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB1_RDCLI4__MAX_BW_MASK 0x001FE000L +#define DAGB1_RDCLI4__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB1_RDCLI4__MIN_BW_MASK 0x01C00000L +#define DAGB1_RDCLI4__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB1_RDCLI4__MAX_OSD_MASK 0xFC000000L +//DAGB1_RDCLI5 +#define DAGB1_RDCLI5__TC__SHIFT 0x0 +#define DAGB1_RDCLI5__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB1_RDCLI5__PRIORITY_ARB1__SHIFT 0x4 +#define DAGB1_RDCLI5__PROFILE_ARB2__SHIFT 0x8 +#define DAGB1_RDCLI5__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB1_RDCLI5__MAX_BW__SHIFT 0xd +#define DAGB1_RDCLI5__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB1_RDCLI5__MIN_BW__SHIFT 0x16 +#define DAGB1_RDCLI5__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB1_RDCLI5__MAX_OSD__SHIFT 0x1a +#define DAGB1_RDCLI5__TC_MASK 0x00000007L +#define DAGB1_RDCLI5__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB1_RDCLI5__PRIORITY_ARB1_MASK 0x000000F0L +#define DAGB1_RDCLI5__PROFILE_ARB2_MASK 0x00000700L +#define DAGB1_RDCLI5__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB1_RDCLI5__MAX_BW_MASK 0x001FE000L +#define DAGB1_RDCLI5__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB1_RDCLI5__MIN_BW_MASK 0x01C00000L +#define DAGB1_RDCLI5__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB1_RDCLI5__MAX_OSD_MASK 0xFC000000L +//DAGB1_RDCLI6 +#define DAGB1_RDCLI6__TC__SHIFT 0x0 +#define DAGB1_RDCLI6__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB1_RDCLI6__PRIORITY_ARB1__SHIFT 0x4 +#define DAGB1_RDCLI6__PROFILE_ARB2__SHIFT 0x8 +#define DAGB1_RDCLI6__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB1_RDCLI6__MAX_BW__SHIFT 0xd +#define DAGB1_RDCLI6__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB1_RDCLI6__MIN_BW__SHIFT 0x16 +#define DAGB1_RDCLI6__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB1_RDCLI6__MAX_OSD__SHIFT 0x1a +#define DAGB1_RDCLI6__TC_MASK 0x00000007L +#define DAGB1_RDCLI6__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB1_RDCLI6__PRIORITY_ARB1_MASK 0x000000F0L +#define DAGB1_RDCLI6__PROFILE_ARB2_MASK 0x00000700L +#define DAGB1_RDCLI6__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB1_RDCLI6__MAX_BW_MASK 0x001FE000L +#define DAGB1_RDCLI6__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB1_RDCLI6__MIN_BW_MASK 0x01C00000L +#define DAGB1_RDCLI6__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB1_RDCLI6__MAX_OSD_MASK 0xFC000000L +//DAGB1_RDCLI7 +#define DAGB1_RDCLI7__TC__SHIFT 0x0 +#define DAGB1_RDCLI7__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB1_RDCLI7__PRIORITY_ARB1__SHIFT 0x4 +#define DAGB1_RDCLI7__PROFILE_ARB2__SHIFT 0x8 +#define DAGB1_RDCLI7__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB1_RDCLI7__MAX_BW__SHIFT 0xd +#define DAGB1_RDCLI7__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB1_RDCLI7__MIN_BW__SHIFT 0x16 +#define DAGB1_RDCLI7__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB1_RDCLI7__MAX_OSD__SHIFT 0x1a +#define DAGB1_RDCLI7__TC_MASK 0x00000007L +#define DAGB1_RDCLI7__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB1_RDCLI7__PRIORITY_ARB1_MASK 0x000000F0L +#define DAGB1_RDCLI7__PROFILE_ARB2_MASK 0x00000700L +#define DAGB1_RDCLI7__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB1_RDCLI7__MAX_BW_MASK 0x001FE000L +#define DAGB1_RDCLI7__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB1_RDCLI7__MIN_BW_MASK 0x01C00000L +#define DAGB1_RDCLI7__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB1_RDCLI7__MAX_OSD_MASK 0xFC000000L +//DAGB1_RDCLI8 +#define DAGB1_RDCLI8__TC__SHIFT 0x0 +#define DAGB1_RDCLI8__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB1_RDCLI8__PRIORITY_ARB1__SHIFT 0x4 +#define DAGB1_RDCLI8__PROFILE_ARB2__SHIFT 0x8 +#define DAGB1_RDCLI8__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB1_RDCLI8__MAX_BW__SHIFT 0xd +#define DAGB1_RDCLI8__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB1_RDCLI8__MIN_BW__SHIFT 0x16 +#define DAGB1_RDCLI8__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB1_RDCLI8__MAX_OSD__SHIFT 0x1a +#define DAGB1_RDCLI8__TC_MASK 0x00000007L +#define DAGB1_RDCLI8__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB1_RDCLI8__PRIORITY_ARB1_MASK 0x000000F0L +#define DAGB1_RDCLI8__PROFILE_ARB2_MASK 0x00000700L +#define DAGB1_RDCLI8__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB1_RDCLI8__MAX_BW_MASK 0x001FE000L +#define DAGB1_RDCLI8__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB1_RDCLI8__MIN_BW_MASK 0x01C00000L +#define DAGB1_RDCLI8__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB1_RDCLI8__MAX_OSD_MASK 0xFC000000L +//DAGB1_RDCLI9 +#define DAGB1_RDCLI9__TC__SHIFT 0x0 +#define DAGB1_RDCLI9__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB1_RDCLI9__PRIORITY_ARB1__SHIFT 0x4 +#define DAGB1_RDCLI9__PROFILE_ARB2__SHIFT 0x8 +#define DAGB1_RDCLI9__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB1_RDCLI9__MAX_BW__SHIFT 0xd +#define DAGB1_RDCLI9__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB1_RDCLI9__MIN_BW__SHIFT 0x16 +#define DAGB1_RDCLI9__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB1_RDCLI9__MAX_OSD__SHIFT 0x1a +#define DAGB1_RDCLI9__TC_MASK 0x00000007L +#define DAGB1_RDCLI9__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB1_RDCLI9__PRIORITY_ARB1_MASK 0x000000F0L +#define DAGB1_RDCLI9__PROFILE_ARB2_MASK 0x00000700L +#define DAGB1_RDCLI9__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB1_RDCLI9__MAX_BW_MASK 0x001FE000L +#define DAGB1_RDCLI9__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB1_RDCLI9__MIN_BW_MASK 0x01C00000L +#define DAGB1_RDCLI9__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB1_RDCLI9__MAX_OSD_MASK 0xFC000000L +//DAGB1_RDCLI10 +#define DAGB1_RDCLI10__TC__SHIFT 0x0 +#define DAGB1_RDCLI10__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB1_RDCLI10__PRIORITY_ARB1__SHIFT 0x4 +#define DAGB1_RDCLI10__PROFILE_ARB2__SHIFT 0x8 +#define DAGB1_RDCLI10__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB1_RDCLI10__MAX_BW__SHIFT 0xd +#define DAGB1_RDCLI10__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB1_RDCLI10__MIN_BW__SHIFT 0x16 +#define DAGB1_RDCLI10__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB1_RDCLI10__MAX_OSD__SHIFT 0x1a +#define DAGB1_RDCLI10__TC_MASK 0x00000007L +#define DAGB1_RDCLI10__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB1_RDCLI10__PRIORITY_ARB1_MASK 0x000000F0L +#define DAGB1_RDCLI10__PROFILE_ARB2_MASK 0x00000700L +#define DAGB1_RDCLI10__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB1_RDCLI10__MAX_BW_MASK 0x001FE000L +#define DAGB1_RDCLI10__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB1_RDCLI10__MIN_BW_MASK 0x01C00000L +#define DAGB1_RDCLI10__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB1_RDCLI10__MAX_OSD_MASK 0xFC000000L +//DAGB1_RDCLI11 +#define DAGB1_RDCLI11__TC__SHIFT 0x0 +#define DAGB1_RDCLI11__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB1_RDCLI11__PRIORITY_ARB1__SHIFT 0x4 +#define DAGB1_RDCLI11__PROFILE_ARB2__SHIFT 0x8 +#define DAGB1_RDCLI11__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB1_RDCLI11__MAX_BW__SHIFT 0xd +#define DAGB1_RDCLI11__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB1_RDCLI11__MIN_BW__SHIFT 0x16 +#define DAGB1_RDCLI11__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB1_RDCLI11__MAX_OSD__SHIFT 0x1a +#define DAGB1_RDCLI11__TC_MASK 0x00000007L +#define DAGB1_RDCLI11__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB1_RDCLI11__PRIORITY_ARB1_MASK 0x000000F0L +#define DAGB1_RDCLI11__PROFILE_ARB2_MASK 0x00000700L +#define DAGB1_RDCLI11__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB1_RDCLI11__MAX_BW_MASK 0x001FE000L +#define DAGB1_RDCLI11__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB1_RDCLI11__MIN_BW_MASK 0x01C00000L +#define DAGB1_RDCLI11__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB1_RDCLI11__MAX_OSD_MASK 0xFC000000L +//DAGB1_RDCLI12 +#define DAGB1_RDCLI12__TC__SHIFT 0x0 +#define DAGB1_RDCLI12__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB1_RDCLI12__PRIORITY_ARB1__SHIFT 0x4 +#define DAGB1_RDCLI12__PROFILE_ARB2__SHIFT 0x8 +#define DAGB1_RDCLI12__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB1_RDCLI12__MAX_BW__SHIFT 0xd +#define DAGB1_RDCLI12__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB1_RDCLI12__MIN_BW__SHIFT 0x16 +#define DAGB1_RDCLI12__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB1_RDCLI12__MAX_OSD__SHIFT 0x1a +#define DAGB1_RDCLI12__TC_MASK 0x00000007L +#define DAGB1_RDCLI12__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB1_RDCLI12__PRIORITY_ARB1_MASK 0x000000F0L +#define DAGB1_RDCLI12__PROFILE_ARB2_MASK 0x00000700L +#define DAGB1_RDCLI12__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB1_RDCLI12__MAX_BW_MASK 0x001FE000L +#define DAGB1_RDCLI12__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB1_RDCLI12__MIN_BW_MASK 0x01C00000L +#define DAGB1_RDCLI12__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB1_RDCLI12__MAX_OSD_MASK 0xFC000000L +//DAGB1_RDCLI13 +#define DAGB1_RDCLI13__TC__SHIFT 0x0 +#define DAGB1_RDCLI13__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB1_RDCLI13__PRIORITY_ARB1__SHIFT 0x4 +#define DAGB1_RDCLI13__PROFILE_ARB2__SHIFT 0x8 +#define DAGB1_RDCLI13__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB1_RDCLI13__MAX_BW__SHIFT 0xd +#define DAGB1_RDCLI13__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB1_RDCLI13__MIN_BW__SHIFT 0x16 +#define DAGB1_RDCLI13__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB1_RDCLI13__MAX_OSD__SHIFT 0x1a +#define DAGB1_RDCLI13__TC_MASK 0x00000007L +#define DAGB1_RDCLI13__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB1_RDCLI13__PRIORITY_ARB1_MASK 0x000000F0L +#define DAGB1_RDCLI13__PROFILE_ARB2_MASK 0x00000700L +#define DAGB1_RDCLI13__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB1_RDCLI13__MAX_BW_MASK 0x001FE000L +#define DAGB1_RDCLI13__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB1_RDCLI13__MIN_BW_MASK 0x01C00000L +#define DAGB1_RDCLI13__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB1_RDCLI13__MAX_OSD_MASK 0xFC000000L +//DAGB1_RDCLI14 +#define DAGB1_RDCLI14__TC__SHIFT 0x0 +#define DAGB1_RDCLI14__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB1_RDCLI14__PRIORITY_ARB1__SHIFT 0x4 +#define DAGB1_RDCLI14__PROFILE_ARB2__SHIFT 0x8 +#define DAGB1_RDCLI14__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB1_RDCLI14__MAX_BW__SHIFT 0xd +#define DAGB1_RDCLI14__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB1_RDCLI14__MIN_BW__SHIFT 0x16 +#define DAGB1_RDCLI14__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB1_RDCLI14__MAX_OSD__SHIFT 0x1a +#define DAGB1_RDCLI14__TC_MASK 0x00000007L +#define DAGB1_RDCLI14__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB1_RDCLI14__PRIORITY_ARB1_MASK 0x000000F0L +#define DAGB1_RDCLI14__PROFILE_ARB2_MASK 0x00000700L +#define DAGB1_RDCLI14__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB1_RDCLI14__MAX_BW_MASK 0x001FE000L +#define DAGB1_RDCLI14__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB1_RDCLI14__MIN_BW_MASK 0x01C00000L +#define DAGB1_RDCLI14__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB1_RDCLI14__MAX_OSD_MASK 0xFC000000L +//DAGB1_RDCLI15 +#define DAGB1_RDCLI15__TC__SHIFT 0x0 +#define DAGB1_RDCLI15__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB1_RDCLI15__PRIORITY_ARB1__SHIFT 0x4 +#define DAGB1_RDCLI15__PROFILE_ARB2__SHIFT 0x8 +#define DAGB1_RDCLI15__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB1_RDCLI15__MAX_BW__SHIFT 0xd +#define DAGB1_RDCLI15__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB1_RDCLI15__MIN_BW__SHIFT 0x16 +#define DAGB1_RDCLI15__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB1_RDCLI15__MAX_OSD__SHIFT 0x1a +#define DAGB1_RDCLI15__TC_MASK 0x00000007L +#define DAGB1_RDCLI15__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB1_RDCLI15__PRIORITY_ARB1_MASK 0x000000F0L +#define DAGB1_RDCLI15__PROFILE_ARB2_MASK 0x00000700L +#define DAGB1_RDCLI15__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB1_RDCLI15__MAX_BW_MASK 0x001FE000L +#define DAGB1_RDCLI15__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB1_RDCLI15__MIN_BW_MASK 0x01C00000L +#define DAGB1_RDCLI15__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB1_RDCLI15__MAX_OSD_MASK 0xFC000000L +//DAGB1_RDCLI16 +#define DAGB1_RDCLI16__TC__SHIFT 0x0 +#define DAGB1_RDCLI16__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB1_RDCLI16__PRIORITY_ARB1__SHIFT 0x4 +#define DAGB1_RDCLI16__PROFILE_ARB2__SHIFT 0x8 +#define DAGB1_RDCLI16__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB1_RDCLI16__MAX_BW__SHIFT 0xd +#define DAGB1_RDCLI16__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB1_RDCLI16__MIN_BW__SHIFT 0x16 +#define DAGB1_RDCLI16__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB1_RDCLI16__MAX_OSD__SHIFT 0x1a +#define DAGB1_RDCLI16__TC_MASK 0x00000007L +#define DAGB1_RDCLI16__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB1_RDCLI16__PRIORITY_ARB1_MASK 0x000000F0L +#define DAGB1_RDCLI16__PROFILE_ARB2_MASK 0x00000700L +#define DAGB1_RDCLI16__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB1_RDCLI16__MAX_BW_MASK 0x001FE000L +#define DAGB1_RDCLI16__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB1_RDCLI16__MIN_BW_MASK 0x01C00000L +#define DAGB1_RDCLI16__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB1_RDCLI16__MAX_OSD_MASK 0xFC000000L +//DAGB1_RDCLI17 +#define DAGB1_RDCLI17__TC__SHIFT 0x0 +#define DAGB1_RDCLI17__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB1_RDCLI17__PRIORITY_ARB1__SHIFT 0x4 +#define DAGB1_RDCLI17__PROFILE_ARB2__SHIFT 0x8 +#define DAGB1_RDCLI17__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB1_RDCLI17__MAX_BW__SHIFT 0xd +#define DAGB1_RDCLI17__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB1_RDCLI17__MIN_BW__SHIFT 0x16 +#define DAGB1_RDCLI17__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB1_RDCLI17__MAX_OSD__SHIFT 0x1a +#define DAGB1_RDCLI17__TC_MASK 0x00000007L +#define DAGB1_RDCLI17__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB1_RDCLI17__PRIORITY_ARB1_MASK 0x000000F0L +#define DAGB1_RDCLI17__PROFILE_ARB2_MASK 0x00000700L +#define DAGB1_RDCLI17__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB1_RDCLI17__MAX_BW_MASK 0x001FE000L +#define DAGB1_RDCLI17__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB1_RDCLI17__MIN_BW_MASK 0x01C00000L +#define DAGB1_RDCLI17__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB1_RDCLI17__MAX_OSD_MASK 0xFC000000L +//DAGB1_RDCLI18 +#define DAGB1_RDCLI18__TC__SHIFT 0x0 +#define DAGB1_RDCLI18__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB1_RDCLI18__PRIORITY_ARB1__SHIFT 0x4 +#define DAGB1_RDCLI18__PROFILE_ARB2__SHIFT 0x8 +#define DAGB1_RDCLI18__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB1_RDCLI18__MAX_BW__SHIFT 0xd +#define DAGB1_RDCLI18__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB1_RDCLI18__MIN_BW__SHIFT 0x16 +#define DAGB1_RDCLI18__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB1_RDCLI18__MAX_OSD__SHIFT 0x1a +#define DAGB1_RDCLI18__TC_MASK 0x00000007L +#define DAGB1_RDCLI18__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB1_RDCLI18__PRIORITY_ARB1_MASK 0x000000F0L +#define DAGB1_RDCLI18__PROFILE_ARB2_MASK 0x00000700L +#define DAGB1_RDCLI18__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB1_RDCLI18__MAX_BW_MASK 0x001FE000L +#define DAGB1_RDCLI18__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB1_RDCLI18__MIN_BW_MASK 0x01C00000L +#define DAGB1_RDCLI18__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB1_RDCLI18__MAX_OSD_MASK 0xFC000000L +//DAGB1_RDCLI19 +#define DAGB1_RDCLI19__TC__SHIFT 0x0 +#define DAGB1_RDCLI19__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB1_RDCLI19__PRIORITY_ARB1__SHIFT 0x4 +#define DAGB1_RDCLI19__PROFILE_ARB2__SHIFT 0x8 +#define DAGB1_RDCLI19__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB1_RDCLI19__MAX_BW__SHIFT 0xd +#define DAGB1_RDCLI19__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB1_RDCLI19__MIN_BW__SHIFT 0x16 +#define DAGB1_RDCLI19__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB1_RDCLI19__MAX_OSD__SHIFT 0x1a +#define DAGB1_RDCLI19__TC_MASK 0x00000007L +#define DAGB1_RDCLI19__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB1_RDCLI19__PRIORITY_ARB1_MASK 0x000000F0L +#define DAGB1_RDCLI19__PROFILE_ARB2_MASK 0x00000700L +#define DAGB1_RDCLI19__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB1_RDCLI19__MAX_BW_MASK 0x001FE000L +#define DAGB1_RDCLI19__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB1_RDCLI19__MIN_BW_MASK 0x01C00000L +#define DAGB1_RDCLI19__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB1_RDCLI19__MAX_OSD_MASK 0xFC000000L +//DAGB1_RDCLI20 +#define DAGB1_RDCLI20__TC__SHIFT 0x0 +#define DAGB1_RDCLI20__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB1_RDCLI20__PRIORITY_ARB1__SHIFT 0x4 +#define DAGB1_RDCLI20__PROFILE_ARB2__SHIFT 0x8 +#define DAGB1_RDCLI20__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB1_RDCLI20__MAX_BW__SHIFT 0xd +#define DAGB1_RDCLI20__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB1_RDCLI20__MIN_BW__SHIFT 0x16 +#define DAGB1_RDCLI20__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB1_RDCLI20__MAX_OSD__SHIFT 0x1a +#define DAGB1_RDCLI20__TC_MASK 0x00000007L +#define DAGB1_RDCLI20__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB1_RDCLI20__PRIORITY_ARB1_MASK 0x000000F0L +#define DAGB1_RDCLI20__PROFILE_ARB2_MASK 0x00000700L +#define DAGB1_RDCLI20__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB1_RDCLI20__MAX_BW_MASK 0x001FE000L +#define DAGB1_RDCLI20__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB1_RDCLI20__MIN_BW_MASK 0x01C00000L +#define DAGB1_RDCLI20__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB1_RDCLI20__MAX_OSD_MASK 0xFC000000L +//DAGB1_RDCLI21 +#define DAGB1_RDCLI21__TC__SHIFT 0x0 +#define DAGB1_RDCLI21__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB1_RDCLI21__PRIORITY_ARB1__SHIFT 0x4 +#define DAGB1_RDCLI21__PROFILE_ARB2__SHIFT 0x8 +#define DAGB1_RDCLI21__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB1_RDCLI21__MAX_BW__SHIFT 0xd +#define DAGB1_RDCLI21__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB1_RDCLI21__MIN_BW__SHIFT 0x16 +#define DAGB1_RDCLI21__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB1_RDCLI21__MAX_OSD__SHIFT 0x1a +#define DAGB1_RDCLI21__TC_MASK 0x00000007L +#define DAGB1_RDCLI21__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB1_RDCLI21__PRIORITY_ARB1_MASK 0x000000F0L +#define DAGB1_RDCLI21__PROFILE_ARB2_MASK 0x00000700L +#define DAGB1_RDCLI21__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB1_RDCLI21__MAX_BW_MASK 0x001FE000L +#define DAGB1_RDCLI21__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB1_RDCLI21__MIN_BW_MASK 0x01C00000L +#define DAGB1_RDCLI21__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB1_RDCLI21__MAX_OSD_MASK 0xFC000000L +//DAGB1_RDCLI22 +#define DAGB1_RDCLI22__TC__SHIFT 0x0 +#define DAGB1_RDCLI22__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB1_RDCLI22__PRIORITY_ARB1__SHIFT 0x4 +#define DAGB1_RDCLI22__PROFILE_ARB2__SHIFT 0x8 +#define DAGB1_RDCLI22__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB1_RDCLI22__MAX_BW__SHIFT 0xd +#define DAGB1_RDCLI22__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB1_RDCLI22__MIN_BW__SHIFT 0x16 +#define DAGB1_RDCLI22__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB1_RDCLI22__MAX_OSD__SHIFT 0x1a +#define DAGB1_RDCLI22__TC_MASK 0x00000007L +#define DAGB1_RDCLI22__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB1_RDCLI22__PRIORITY_ARB1_MASK 0x000000F0L +#define DAGB1_RDCLI22__PROFILE_ARB2_MASK 0x00000700L +#define DAGB1_RDCLI22__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB1_RDCLI22__MAX_BW_MASK 0x001FE000L +#define DAGB1_RDCLI22__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB1_RDCLI22__MIN_BW_MASK 0x01C00000L +#define DAGB1_RDCLI22__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB1_RDCLI22__MAX_OSD_MASK 0xFC000000L +//DAGB1_RDCLI23 +#define DAGB1_RDCLI23__TC__SHIFT 0x0 +#define DAGB1_RDCLI23__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB1_RDCLI23__PRIORITY_ARB1__SHIFT 0x4 +#define DAGB1_RDCLI23__PROFILE_ARB2__SHIFT 0x8 +#define DAGB1_RDCLI23__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB1_RDCLI23__MAX_BW__SHIFT 0xd +#define DAGB1_RDCLI23__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB1_RDCLI23__MIN_BW__SHIFT 0x16 +#define DAGB1_RDCLI23__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB1_RDCLI23__MAX_OSD__SHIFT 0x1a +#define DAGB1_RDCLI23__TC_MASK 0x00000007L +#define DAGB1_RDCLI23__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB1_RDCLI23__PRIORITY_ARB1_MASK 0x000000F0L +#define DAGB1_RDCLI23__PROFILE_ARB2_MASK 0x00000700L +#define DAGB1_RDCLI23__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB1_RDCLI23__MAX_BW_MASK 0x001FE000L +#define DAGB1_RDCLI23__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB1_RDCLI23__MIN_BW_MASK 0x01C00000L +#define DAGB1_RDCLI23__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB1_RDCLI23__MAX_OSD_MASK 0xFC000000L +//DAGB1_RD_CNTL +#define DAGB1_RD_CNTL__CLI_MAX_BW_WINDOW__SHIFT 0x0 +#define DAGB1_RD_CNTL__MAX_BW_ENABLE__SHIFT 0x9 +#define DAGB1_RD_CNTL__MAX_BW__SHIFT 0xa +#define DAGB1_RD_CNTL__BUSY_HYSTERESIS_64B_CLI__SHIFT 0x15 +#define DAGB1_RD_CNTL__BW_ALARM_BLOCK_BOOST__SHIFT 0x1d +#define DAGB1_RD_CNTL__CLI_MAX_BW_WINDOW_MASK 0x000001FFL +#define DAGB1_RD_CNTL__MAX_BW_ENABLE_MASK 0x00000200L +#define DAGB1_RD_CNTL__MAX_BW_MASK 0x001FFC00L +#define DAGB1_RD_CNTL__BUSY_HYSTERESIS_64B_CLI_MASK 0x1FE00000L +#define DAGB1_RD_CNTL__BW_ALARM_BLOCK_BOOST_MASK 0x20000000L +//DAGB1_RD_ADDR_DAGB +#define DAGB1_RD_ADDR_DAGB__DAGB_ENABLE__SHIFT 0x0 +#define DAGB1_RD_ADDR_DAGB__ENABLE_JUMP_AHEAD__SHIFT 0x4 +#define DAGB1_RD_ADDR_DAGB__DISABLE_SELF_INIT__SHIFT 0x8 +#define DAGB1_RD_ADDR_DAGB__WHOAMI__SHIFT 0x9 +#define DAGB1_RD_ADDR_DAGB__JUMP_MODE__SHIFT 0xf +#define DAGB1_RD_ADDR_DAGB__DAGB_ENABLE_MASK 0x0000000FL +#define DAGB1_RD_ADDR_DAGB__ENABLE_JUMP_AHEAD_MASK 0x000000F0L +#define DAGB1_RD_ADDR_DAGB__DISABLE_SELF_INIT_MASK 0x00000100L +#define DAGB1_RD_ADDR_DAGB__WHOAMI_MASK 0x00007E00L +#define DAGB1_RD_ADDR_DAGB__JUMP_MODE_MASK 0x00008000L +//DAGB1_RD_CGTT_CLK_CTRL +#define DAGB1_RD_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 +#define DAGB1_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x5 +#define DAGB1_RD_CGTT_CLK_CTRL__LS_ASSERT_HYSTERESIS__SHIFT 0xd +#define DAGB1_RD_CGTT_CLK_CTRL__MIN_MGLS__SHIFT 0x1a +#define DAGB1_RD_CGTT_CLK_CTRL__CGLS_DISABLE__SHIFT 0x1d +#define DAGB1_RD_CGTT_CLK_CTRL__LS_DISABLE__SHIFT 0x1e +#define DAGB1_RD_CGTT_CLK_CTRL__BUSY_OVERRIDE__SHIFT 0x1f +#define DAGB1_RD_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000001FL +#define DAGB1_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00001FE0L +#define DAGB1_RD_CGTT_CLK_CTRL__LS_ASSERT_HYSTERESIS_MASK 0x03FFE000L +#define DAGB1_RD_CGTT_CLK_CTRL__MIN_MGLS_MASK 0x1C000000L +#define DAGB1_RD_CGTT_CLK_CTRL__CGLS_DISABLE_MASK 0x20000000L +#define DAGB1_RD_CGTT_CLK_CTRL__LS_DISABLE_MASK 0x40000000L +#define DAGB1_RD_CGTT_CLK_CTRL__BUSY_OVERRIDE_MASK 0x80000000L +//DAGB1_L1TLB_RD_CGTT_CLK_CTRL +#define DAGB1_L1TLB_RD_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 +#define DAGB1_L1TLB_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x5 +#define DAGB1_L1TLB_RD_CGTT_CLK_CTRL__LS_ASSERT_HYSTERESIS__SHIFT 0xd +#define DAGB1_L1TLB_RD_CGTT_CLK_CTRL__MIN_MGLS__SHIFT 0x1a +#define DAGB1_L1TLB_RD_CGTT_CLK_CTRL__CGLS_DISABLE__SHIFT 0x1d +#define DAGB1_L1TLB_RD_CGTT_CLK_CTRL__LS_DISABLE__SHIFT 0x1e +#define DAGB1_L1TLB_RD_CGTT_CLK_CTRL__BUSY_OVERRIDE__SHIFT 0x1f +#define DAGB1_L1TLB_RD_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000001FL +#define DAGB1_L1TLB_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00001FE0L +#define DAGB1_L1TLB_RD_CGTT_CLK_CTRL__LS_ASSERT_HYSTERESIS_MASK 0x03FFE000L +#define DAGB1_L1TLB_RD_CGTT_CLK_CTRL__MIN_MGLS_MASK 0x1C000000L +#define DAGB1_L1TLB_RD_CGTT_CLK_CTRL__CGLS_DISABLE_MASK 0x20000000L +#define DAGB1_L1TLB_RD_CGTT_CLK_CTRL__LS_DISABLE_MASK 0x40000000L +#define DAGB1_L1TLB_RD_CGTT_CLK_CTRL__BUSY_OVERRIDE_MASK 0x80000000L +//DAGB1_RD_ADDR_DAGB_MAX_BURST0 +#define DAGB1_RD_ADDR_DAGB_MAX_BURST0__CLIENT0__SHIFT 0x0 +#define DAGB1_RD_ADDR_DAGB_MAX_BURST0__CLIENT1__SHIFT 0x4 +#define DAGB1_RD_ADDR_DAGB_MAX_BURST0__CLIENT2__SHIFT 0x8 +#define DAGB1_RD_ADDR_DAGB_MAX_BURST0__CLIENT3__SHIFT 0xc +#define DAGB1_RD_ADDR_DAGB_MAX_BURST0__CLIENT4__SHIFT 0x10 +#define DAGB1_RD_ADDR_DAGB_MAX_BURST0__CLIENT5__SHIFT 0x14 +#define DAGB1_RD_ADDR_DAGB_MAX_BURST0__CLIENT6__SHIFT 0x18 +#define DAGB1_RD_ADDR_DAGB_MAX_BURST0__CLIENT7__SHIFT 0x1c +#define DAGB1_RD_ADDR_DAGB_MAX_BURST0__CLIENT0_MASK 0x0000000FL +#define DAGB1_RD_ADDR_DAGB_MAX_BURST0__CLIENT1_MASK 0x000000F0L +#define DAGB1_RD_ADDR_DAGB_MAX_BURST0__CLIENT2_MASK 0x00000F00L +#define DAGB1_RD_ADDR_DAGB_MAX_BURST0__CLIENT3_MASK 0x0000F000L +#define DAGB1_RD_ADDR_DAGB_MAX_BURST0__CLIENT4_MASK 0x000F0000L +#define DAGB1_RD_ADDR_DAGB_MAX_BURST0__CLIENT5_MASK 0x00F00000L +#define DAGB1_RD_ADDR_DAGB_MAX_BURST0__CLIENT6_MASK 0x0F000000L +#define DAGB1_RD_ADDR_DAGB_MAX_BURST0__CLIENT7_MASK 0xF0000000L +//DAGB1_RD_ADDR_DAGB_LAZY_TIMER0 +#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT0__SHIFT 0x0 +#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT1__SHIFT 0x4 +#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT2__SHIFT 0x8 +#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT3__SHIFT 0xc +#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT4__SHIFT 0x10 +#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT5__SHIFT 0x14 +#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT6__SHIFT 0x18 +#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT7__SHIFT 0x1c +#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT0_MASK 0x0000000FL +#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT1_MASK 0x000000F0L +#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT2_MASK 0x00000F00L +#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT3_MASK 0x0000F000L +#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT4_MASK 0x000F0000L +#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT5_MASK 0x00F00000L +#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT6_MASK 0x0F000000L +#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT7_MASK 0xF0000000L +//DAGB1_RD_ADDR_DAGB_MAX_BURST1 +#define DAGB1_RD_ADDR_DAGB_MAX_BURST1__CLIENT8__SHIFT 0x0 +#define DAGB1_RD_ADDR_DAGB_MAX_BURST1__CLIENT9__SHIFT 0x4 +#define DAGB1_RD_ADDR_DAGB_MAX_BURST1__CLIENT10__SHIFT 0x8 +#define DAGB1_RD_ADDR_DAGB_MAX_BURST1__CLIENT11__SHIFT 0xc +#define DAGB1_RD_ADDR_DAGB_MAX_BURST1__CLIENT12__SHIFT 0x10 +#define DAGB1_RD_ADDR_DAGB_MAX_BURST1__CLIENT13__SHIFT 0x14 +#define DAGB1_RD_ADDR_DAGB_MAX_BURST1__CLIENT14__SHIFT 0x18 +#define DAGB1_RD_ADDR_DAGB_MAX_BURST1__CLIENT15__SHIFT 0x1c +#define DAGB1_RD_ADDR_DAGB_MAX_BURST1__CLIENT8_MASK 0x0000000FL +#define DAGB1_RD_ADDR_DAGB_MAX_BURST1__CLIENT9_MASK 0x000000F0L +#define DAGB1_RD_ADDR_DAGB_MAX_BURST1__CLIENT10_MASK 0x00000F00L +#define DAGB1_RD_ADDR_DAGB_MAX_BURST1__CLIENT11_MASK 0x0000F000L +#define DAGB1_RD_ADDR_DAGB_MAX_BURST1__CLIENT12_MASK 0x000F0000L +#define DAGB1_RD_ADDR_DAGB_MAX_BURST1__CLIENT13_MASK 0x00F00000L +#define DAGB1_RD_ADDR_DAGB_MAX_BURST1__CLIENT14_MASK 0x0F000000L +#define DAGB1_RD_ADDR_DAGB_MAX_BURST1__CLIENT15_MASK 0xF0000000L +//DAGB1_RD_ADDR_DAGB_LAZY_TIMER1 +#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT8__SHIFT 0x0 +#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT9__SHIFT 0x4 +#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT10__SHIFT 0x8 +#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT11__SHIFT 0xc +#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT12__SHIFT 0x10 +#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT13__SHIFT 0x14 +#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT14__SHIFT 0x18 +#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT15__SHIFT 0x1c +#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT8_MASK 0x0000000FL +#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT9_MASK 0x000000F0L +#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT10_MASK 0x00000F00L +#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT11_MASK 0x0000F000L +#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT12_MASK 0x000F0000L +#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT13_MASK 0x00F00000L +#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT14_MASK 0x0F000000L +#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT15_MASK 0xF0000000L +//DAGB1_RD_ADDR_DAGB_MAX_BURST2 +#define DAGB1_RD_ADDR_DAGB_MAX_BURST2__CLIENT16__SHIFT 0x0 +#define DAGB1_RD_ADDR_DAGB_MAX_BURST2__CLIENT17__SHIFT 0x4 +#define DAGB1_RD_ADDR_DAGB_MAX_BURST2__CLIENT18__SHIFT 0x8 +#define DAGB1_RD_ADDR_DAGB_MAX_BURST2__CLIENT19__SHIFT 0xc +#define DAGB1_RD_ADDR_DAGB_MAX_BURST2__CLIENT20__SHIFT 0x10 +#define DAGB1_RD_ADDR_DAGB_MAX_BURST2__CLIENT21__SHIFT 0x14 +#define DAGB1_RD_ADDR_DAGB_MAX_BURST2__CLIENT22__SHIFT 0x18 +#define DAGB1_RD_ADDR_DAGB_MAX_BURST2__CLIENT23__SHIFT 0x1c +#define DAGB1_RD_ADDR_DAGB_MAX_BURST2__CLIENT16_MASK 0x0000000FL +#define DAGB1_RD_ADDR_DAGB_MAX_BURST2__CLIENT17_MASK 0x000000F0L +#define DAGB1_RD_ADDR_DAGB_MAX_BURST2__CLIENT18_MASK 0x00000F00L +#define DAGB1_RD_ADDR_DAGB_MAX_BURST2__CLIENT19_MASK 0x0000F000L +#define DAGB1_RD_ADDR_DAGB_MAX_BURST2__CLIENT20_MASK 0x000F0000L +#define DAGB1_RD_ADDR_DAGB_MAX_BURST2__CLIENT21_MASK 0x00F00000L +#define DAGB1_RD_ADDR_DAGB_MAX_BURST2__CLIENT22_MASK 0x0F000000L +#define DAGB1_RD_ADDR_DAGB_MAX_BURST2__CLIENT23_MASK 0xF0000000L +//DAGB1_RD_ADDR_DAGB_LAZY_TIMER2 +#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT16__SHIFT 0x0 +#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT17__SHIFT 0x4 +#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT18__SHIFT 0x8 +#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT19__SHIFT 0xc +#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT20__SHIFT 0x10 +#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT21__SHIFT 0x14 +#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT22__SHIFT 0x18 +#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT23__SHIFT 0x1c +#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT16_MASK 0x0000000FL +#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT17_MASK 0x000000F0L +#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT18_MASK 0x00000F00L +#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT19_MASK 0x0000F000L +#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT20_MASK 0x000F0000L +#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT21_MASK 0x00F00000L +#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT22_MASK 0x0F000000L +#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT23_MASK 0xF0000000L +//DAGB1_RD_CNTL_MISC +#define DAGB1_RD_CNTL_MISC__UTCL2_VCI__SHIFT 0x6 +#define DAGB1_RD_CNTL_MISC__CLI_SWITCH_MODE__SHIFT 0x9 +#define DAGB1_RD_CNTL_MISC__CREDIT_SWITCH_MODE__SHIFT 0xb +#define DAGB1_RD_CNTL_MISC__BUDGET_SWITCH_MODE__SHIFT 0xd +#define DAGB1_RD_CNTL_MISC__CLI_CLEAN_MODE__SHIFT 0xf +#define DAGB1_RD_CNTL_MISC__UTCL2_VCI_MASK 0x000001C0L +#define DAGB1_RD_CNTL_MISC__CLI_SWITCH_MODE_MASK 0x00000600L +#define DAGB1_RD_CNTL_MISC__CREDIT_SWITCH_MODE_MASK 0x00001800L +#define DAGB1_RD_CNTL_MISC__BUDGET_SWITCH_MODE_MASK 0x00006000L +#define DAGB1_RD_CNTL_MISC__CLI_CLEAN_MODE_MASK 0x00008000L +//DAGB1_RD_TLB_CREDIT +#define DAGB1_RD_TLB_CREDIT__TLB0__SHIFT 0x0 +#define DAGB1_RD_TLB_CREDIT__TLB1__SHIFT 0x5 +#define DAGB1_RD_TLB_CREDIT__TLB2__SHIFT 0xa +#define DAGB1_RD_TLB_CREDIT__TLB3__SHIFT 0xf +#define DAGB1_RD_TLB_CREDIT__TLB0_MASK 0x0000001FL +#define DAGB1_RD_TLB_CREDIT__TLB1_MASK 0x000003E0L +#define DAGB1_RD_TLB_CREDIT__TLB2_MASK 0x00007C00L +#define DAGB1_RD_TLB_CREDIT__TLB3_MASK 0x000F8000L +//DAGB1_RDCLI_ASK_PENDING +#define DAGB1_RDCLI_ASK_PENDING__BUSY__SHIFT 0x0 +#define DAGB1_RDCLI_ASK_PENDING__BUSY_MASK 0x00FFFFFFL +//DAGB1_RDCLI_GO_PENDING +#define DAGB1_RDCLI_GO_PENDING__BUSY__SHIFT 0x0 +#define DAGB1_RDCLI_GO_PENDING__BUSY_MASK 0x00FFFFFFL +//DAGB1_RDCLI_GBLSEND_PENDING +#define DAGB1_RDCLI_GBLSEND_PENDING__BUSY__SHIFT 0x0 +#define DAGB1_RDCLI_GBLSEND_PENDING__BUSY_MASK 0x00FFFFFFL +//DAGB1_RDCLI_TLB_PENDING +#define DAGB1_RDCLI_TLB_PENDING__BUSY__SHIFT 0x0 +#define DAGB1_RDCLI_TLB_PENDING__BUSY_MASK 0x00FFFFFFL +//DAGB1_RDCLI_OARB_PENDING +#define DAGB1_RDCLI_OARB_PENDING__BUSY__SHIFT 0x0 +#define DAGB1_RDCLI_OARB_PENDING__BUSY_MASK 0x00FFFFFFL +//DAGB1_RDCLI_ASK2DF_PENDING +#define DAGB1_RDCLI_ASK2DF_PENDING__NUM__SHIFT 0x0 +#define DAGB1_RDCLI_ASK2DF_PENDING__NUM_MASK 0x0000FFFFL +//DAGB1_RDCLI_OSD_PENDING +#define DAGB1_RDCLI_OSD_PENDING__BUSY__SHIFT 0x0 +#define DAGB1_RDCLI_OSD_PENDING__BUSY_MASK 0x00FFFFFFL +//DAGB1_RDCLI_ASK_OSD_PENDING +#define DAGB1_RDCLI_ASK_OSD_PENDING__BUSY__SHIFT 0x0 +#define DAGB1_RDCLI_ASK_OSD_PENDING__BUSY_MASK 0x00FFFFFFL +//DAGB1_WRCLI0 +#define DAGB1_WRCLI0__TC__SHIFT 0x0 +#define DAGB1_WRCLI0__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB1_WRCLI0__PRIORITY_ARB1__SHIFT 0x4 +#define DAGB1_WRCLI0__PROFILE_ARB2__SHIFT 0x8 +#define DAGB1_WRCLI0__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB1_WRCLI0__MAX_BW__SHIFT 0xd +#define DAGB1_WRCLI0__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB1_WRCLI0__MIN_BW__SHIFT 0x16 +#define DAGB1_WRCLI0__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB1_WRCLI0__MAX_OSD__SHIFT 0x1a +#define DAGB1_WRCLI0__TC_MASK 0x00000007L +#define DAGB1_WRCLI0__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB1_WRCLI0__PRIORITY_ARB1_MASK 0x000000F0L +#define DAGB1_WRCLI0__PROFILE_ARB2_MASK 0x00000700L +#define DAGB1_WRCLI0__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB1_WRCLI0__MAX_BW_MASK 0x001FE000L +#define DAGB1_WRCLI0__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB1_WRCLI0__MIN_BW_MASK 0x01C00000L +#define DAGB1_WRCLI0__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB1_WRCLI0__MAX_OSD_MASK 0xFC000000L +//DAGB1_WRCLI1 +#define DAGB1_WRCLI1__TC__SHIFT 0x0 +#define DAGB1_WRCLI1__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB1_WRCLI1__PRIORITY_ARB1__SHIFT 0x4 +#define DAGB1_WRCLI1__PROFILE_ARB2__SHIFT 0x8 +#define DAGB1_WRCLI1__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB1_WRCLI1__MAX_BW__SHIFT 0xd +#define DAGB1_WRCLI1__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB1_WRCLI1__MIN_BW__SHIFT 0x16 +#define DAGB1_WRCLI1__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB1_WRCLI1__MAX_OSD__SHIFT 0x1a +#define DAGB1_WRCLI1__TC_MASK 0x00000007L +#define DAGB1_WRCLI1__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB1_WRCLI1__PRIORITY_ARB1_MASK 0x000000F0L +#define DAGB1_WRCLI1__PROFILE_ARB2_MASK 0x00000700L +#define DAGB1_WRCLI1__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB1_WRCLI1__MAX_BW_MASK 0x001FE000L +#define DAGB1_WRCLI1__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB1_WRCLI1__MIN_BW_MASK 0x01C00000L +#define DAGB1_WRCLI1__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB1_WRCLI1__MAX_OSD_MASK 0xFC000000L +//DAGB1_WRCLI2 +#define DAGB1_WRCLI2__TC__SHIFT 0x0 +#define DAGB1_WRCLI2__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB1_WRCLI2__PRIORITY_ARB1__SHIFT 0x4 +#define DAGB1_WRCLI2__PROFILE_ARB2__SHIFT 0x8 +#define DAGB1_WRCLI2__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB1_WRCLI2__MAX_BW__SHIFT 0xd +#define DAGB1_WRCLI2__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB1_WRCLI2__MIN_BW__SHIFT 0x16 +#define DAGB1_WRCLI2__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB1_WRCLI2__MAX_OSD__SHIFT 0x1a +#define DAGB1_WRCLI2__TC_MASK 0x00000007L +#define DAGB1_WRCLI2__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB1_WRCLI2__PRIORITY_ARB1_MASK 0x000000F0L +#define DAGB1_WRCLI2__PROFILE_ARB2_MASK 0x00000700L +#define DAGB1_WRCLI2__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB1_WRCLI2__MAX_BW_MASK 0x001FE000L +#define DAGB1_WRCLI2__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB1_WRCLI2__MIN_BW_MASK 0x01C00000L +#define DAGB1_WRCLI2__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB1_WRCLI2__MAX_OSD_MASK 0xFC000000L +//DAGB1_WRCLI3 +#define DAGB1_WRCLI3__TC__SHIFT 0x0 +#define DAGB1_WRCLI3__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB1_WRCLI3__PRIORITY_ARB1__SHIFT 0x4 +#define DAGB1_WRCLI3__PROFILE_ARB2__SHIFT 0x8 +#define DAGB1_WRCLI3__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB1_WRCLI3__MAX_BW__SHIFT 0xd +#define DAGB1_WRCLI3__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB1_WRCLI3__MIN_BW__SHIFT 0x16 +#define DAGB1_WRCLI3__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB1_WRCLI3__MAX_OSD__SHIFT 0x1a +#define DAGB1_WRCLI3__TC_MASK 0x00000007L +#define DAGB1_WRCLI3__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB1_WRCLI3__PRIORITY_ARB1_MASK 0x000000F0L +#define DAGB1_WRCLI3__PROFILE_ARB2_MASK 0x00000700L +#define DAGB1_WRCLI3__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB1_WRCLI3__MAX_BW_MASK 0x001FE000L +#define DAGB1_WRCLI3__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB1_WRCLI3__MIN_BW_MASK 0x01C00000L +#define DAGB1_WRCLI3__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB1_WRCLI3__MAX_OSD_MASK 0xFC000000L +//DAGB1_WRCLI4 +#define DAGB1_WRCLI4__TC__SHIFT 0x0 +#define DAGB1_WRCLI4__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB1_WRCLI4__PRIORITY_ARB1__SHIFT 0x4 +#define DAGB1_WRCLI4__PROFILE_ARB2__SHIFT 0x8 +#define DAGB1_WRCLI4__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB1_WRCLI4__MAX_BW__SHIFT 0xd +#define DAGB1_WRCLI4__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB1_WRCLI4__MIN_BW__SHIFT 0x16 +#define DAGB1_WRCLI4__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB1_WRCLI4__MAX_OSD__SHIFT 0x1a +#define DAGB1_WRCLI4__TC_MASK 0x00000007L +#define DAGB1_WRCLI4__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB1_WRCLI4__PRIORITY_ARB1_MASK 0x000000F0L +#define DAGB1_WRCLI4__PROFILE_ARB2_MASK 0x00000700L +#define DAGB1_WRCLI4__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB1_WRCLI4__MAX_BW_MASK 0x001FE000L +#define DAGB1_WRCLI4__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB1_WRCLI4__MIN_BW_MASK 0x01C00000L +#define DAGB1_WRCLI4__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB1_WRCLI4__MAX_OSD_MASK 0xFC000000L +//DAGB1_WRCLI5 +#define DAGB1_WRCLI5__TC__SHIFT 0x0 +#define DAGB1_WRCLI5__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB1_WRCLI5__PRIORITY_ARB1__SHIFT 0x4 +#define DAGB1_WRCLI5__PROFILE_ARB2__SHIFT 0x8 +#define DAGB1_WRCLI5__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB1_WRCLI5__MAX_BW__SHIFT 0xd +#define DAGB1_WRCLI5__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB1_WRCLI5__MIN_BW__SHIFT 0x16 +#define DAGB1_WRCLI5__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB1_WRCLI5__MAX_OSD__SHIFT 0x1a +#define DAGB1_WRCLI5__TC_MASK 0x00000007L +#define DAGB1_WRCLI5__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB1_WRCLI5__PRIORITY_ARB1_MASK 0x000000F0L +#define DAGB1_WRCLI5__PROFILE_ARB2_MASK 0x00000700L +#define DAGB1_WRCLI5__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB1_WRCLI5__MAX_BW_MASK 0x001FE000L +#define DAGB1_WRCLI5__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB1_WRCLI5__MIN_BW_MASK 0x01C00000L +#define DAGB1_WRCLI5__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB1_WRCLI5__MAX_OSD_MASK 0xFC000000L +//DAGB1_WRCLI6 +#define DAGB1_WRCLI6__TC__SHIFT 0x0 +#define DAGB1_WRCLI6__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB1_WRCLI6__PRIORITY_ARB1__SHIFT 0x4 +#define DAGB1_WRCLI6__PROFILE_ARB2__SHIFT 0x8 +#define DAGB1_WRCLI6__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB1_WRCLI6__MAX_BW__SHIFT 0xd +#define DAGB1_WRCLI6__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB1_WRCLI6__MIN_BW__SHIFT 0x16 +#define DAGB1_WRCLI6__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB1_WRCLI6__MAX_OSD__SHIFT 0x1a +#define DAGB1_WRCLI6__TC_MASK 0x00000007L +#define DAGB1_WRCLI6__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB1_WRCLI6__PRIORITY_ARB1_MASK 0x000000F0L +#define DAGB1_WRCLI6__PROFILE_ARB2_MASK 0x00000700L +#define DAGB1_WRCLI6__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB1_WRCLI6__MAX_BW_MASK 0x001FE000L +#define DAGB1_WRCLI6__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB1_WRCLI6__MIN_BW_MASK 0x01C00000L +#define DAGB1_WRCLI6__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB1_WRCLI6__MAX_OSD_MASK 0xFC000000L +//DAGB1_WRCLI7 +#define DAGB1_WRCLI7__TC__SHIFT 0x0 +#define DAGB1_WRCLI7__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB1_WRCLI7__PRIORITY_ARB1__SHIFT 0x4 +#define DAGB1_WRCLI7__PROFILE_ARB2__SHIFT 0x8 +#define DAGB1_WRCLI7__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB1_WRCLI7__MAX_BW__SHIFT 0xd +#define DAGB1_WRCLI7__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB1_WRCLI7__MIN_BW__SHIFT 0x16 +#define DAGB1_WRCLI7__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB1_WRCLI7__MAX_OSD__SHIFT 0x1a +#define DAGB1_WRCLI7__TC_MASK 0x00000007L +#define DAGB1_WRCLI7__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB1_WRCLI7__PRIORITY_ARB1_MASK 0x000000F0L +#define DAGB1_WRCLI7__PROFILE_ARB2_MASK 0x00000700L +#define DAGB1_WRCLI7__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB1_WRCLI7__MAX_BW_MASK 0x001FE000L +#define DAGB1_WRCLI7__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB1_WRCLI7__MIN_BW_MASK 0x01C00000L +#define DAGB1_WRCLI7__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB1_WRCLI7__MAX_OSD_MASK 0xFC000000L +//DAGB1_WRCLI8 +#define DAGB1_WRCLI8__TC__SHIFT 0x0 +#define DAGB1_WRCLI8__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB1_WRCLI8__PRIORITY_ARB1__SHIFT 0x4 +#define DAGB1_WRCLI8__PROFILE_ARB2__SHIFT 0x8 +#define DAGB1_WRCLI8__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB1_WRCLI8__MAX_BW__SHIFT 0xd +#define DAGB1_WRCLI8__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB1_WRCLI8__MIN_BW__SHIFT 0x16 +#define DAGB1_WRCLI8__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB1_WRCLI8__MAX_OSD__SHIFT 0x1a +#define DAGB1_WRCLI8__TC_MASK 0x00000007L +#define DAGB1_WRCLI8__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB1_WRCLI8__PRIORITY_ARB1_MASK 0x000000F0L +#define DAGB1_WRCLI8__PROFILE_ARB2_MASK 0x00000700L +#define DAGB1_WRCLI8__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB1_WRCLI8__MAX_BW_MASK 0x001FE000L +#define DAGB1_WRCLI8__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB1_WRCLI8__MIN_BW_MASK 0x01C00000L +#define DAGB1_WRCLI8__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB1_WRCLI8__MAX_OSD_MASK 0xFC000000L +//DAGB1_WRCLI9 +#define DAGB1_WRCLI9__TC__SHIFT 0x0 +#define DAGB1_WRCLI9__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB1_WRCLI9__PRIORITY_ARB1__SHIFT 0x4 +#define DAGB1_WRCLI9__PROFILE_ARB2__SHIFT 0x8 +#define DAGB1_WRCLI9__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB1_WRCLI9__MAX_BW__SHIFT 0xd +#define DAGB1_WRCLI9__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB1_WRCLI9__MIN_BW__SHIFT 0x16 +#define DAGB1_WRCLI9__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB1_WRCLI9__MAX_OSD__SHIFT 0x1a +#define DAGB1_WRCLI9__TC_MASK 0x00000007L +#define DAGB1_WRCLI9__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB1_WRCLI9__PRIORITY_ARB1_MASK 0x000000F0L +#define DAGB1_WRCLI9__PROFILE_ARB2_MASK 0x00000700L +#define DAGB1_WRCLI9__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB1_WRCLI9__MAX_BW_MASK 0x001FE000L +#define DAGB1_WRCLI9__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB1_WRCLI9__MIN_BW_MASK 0x01C00000L +#define DAGB1_WRCLI9__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB1_WRCLI9__MAX_OSD_MASK 0xFC000000L +//DAGB1_WRCLI10 +#define DAGB1_WRCLI10__TC__SHIFT 0x0 +#define DAGB1_WRCLI10__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB1_WRCLI10__PRIORITY_ARB1__SHIFT 0x4 +#define DAGB1_WRCLI10__PROFILE_ARB2__SHIFT 0x8 +#define DAGB1_WRCLI10__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB1_WRCLI10__MAX_BW__SHIFT 0xd +#define DAGB1_WRCLI10__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB1_WRCLI10__MIN_BW__SHIFT 0x16 +#define DAGB1_WRCLI10__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB1_WRCLI10__MAX_OSD__SHIFT 0x1a +#define DAGB1_WRCLI10__TC_MASK 0x00000007L +#define DAGB1_WRCLI10__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB1_WRCLI10__PRIORITY_ARB1_MASK 0x000000F0L +#define DAGB1_WRCLI10__PROFILE_ARB2_MASK 0x00000700L +#define DAGB1_WRCLI10__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB1_WRCLI10__MAX_BW_MASK 0x001FE000L +#define DAGB1_WRCLI10__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB1_WRCLI10__MIN_BW_MASK 0x01C00000L +#define DAGB1_WRCLI10__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB1_WRCLI10__MAX_OSD_MASK 0xFC000000L +//DAGB1_WRCLI11 +#define DAGB1_WRCLI11__TC__SHIFT 0x0 +#define DAGB1_WRCLI11__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB1_WRCLI11__PRIORITY_ARB1__SHIFT 0x4 +#define DAGB1_WRCLI11__PROFILE_ARB2__SHIFT 0x8 +#define DAGB1_WRCLI11__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB1_WRCLI11__MAX_BW__SHIFT 0xd +#define DAGB1_WRCLI11__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB1_WRCLI11__MIN_BW__SHIFT 0x16 +#define DAGB1_WRCLI11__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB1_WRCLI11__MAX_OSD__SHIFT 0x1a +#define DAGB1_WRCLI11__TC_MASK 0x00000007L +#define DAGB1_WRCLI11__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB1_WRCLI11__PRIORITY_ARB1_MASK 0x000000F0L +#define DAGB1_WRCLI11__PROFILE_ARB2_MASK 0x00000700L +#define DAGB1_WRCLI11__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB1_WRCLI11__MAX_BW_MASK 0x001FE000L +#define DAGB1_WRCLI11__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB1_WRCLI11__MIN_BW_MASK 0x01C00000L +#define DAGB1_WRCLI11__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB1_WRCLI11__MAX_OSD_MASK 0xFC000000L +//DAGB1_WRCLI12 +#define DAGB1_WRCLI12__TC__SHIFT 0x0 +#define DAGB1_WRCLI12__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB1_WRCLI12__PRIORITY_ARB1__SHIFT 0x4 +#define DAGB1_WRCLI12__PROFILE_ARB2__SHIFT 0x8 +#define DAGB1_WRCLI12__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB1_WRCLI12__MAX_BW__SHIFT 0xd +#define DAGB1_WRCLI12__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB1_WRCLI12__MIN_BW__SHIFT 0x16 +#define DAGB1_WRCLI12__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB1_WRCLI12__MAX_OSD__SHIFT 0x1a +#define DAGB1_WRCLI12__TC_MASK 0x00000007L +#define DAGB1_WRCLI12__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB1_WRCLI12__PRIORITY_ARB1_MASK 0x000000F0L +#define DAGB1_WRCLI12__PROFILE_ARB2_MASK 0x00000700L +#define DAGB1_WRCLI12__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB1_WRCLI12__MAX_BW_MASK 0x001FE000L +#define DAGB1_WRCLI12__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB1_WRCLI12__MIN_BW_MASK 0x01C00000L +#define DAGB1_WRCLI12__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB1_WRCLI12__MAX_OSD_MASK 0xFC000000L +//DAGB1_WRCLI13 +#define DAGB1_WRCLI13__TC__SHIFT 0x0 +#define DAGB1_WRCLI13__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB1_WRCLI13__PRIORITY_ARB1__SHIFT 0x4 +#define DAGB1_WRCLI13__PROFILE_ARB2__SHIFT 0x8 +#define DAGB1_WRCLI13__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB1_WRCLI13__MAX_BW__SHIFT 0xd +#define DAGB1_WRCLI13__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB1_WRCLI13__MIN_BW__SHIFT 0x16 +#define DAGB1_WRCLI13__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB1_WRCLI13__MAX_OSD__SHIFT 0x1a +#define DAGB1_WRCLI13__TC_MASK 0x00000007L +#define DAGB1_WRCLI13__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB1_WRCLI13__PRIORITY_ARB1_MASK 0x000000F0L +#define DAGB1_WRCLI13__PROFILE_ARB2_MASK 0x00000700L +#define DAGB1_WRCLI13__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB1_WRCLI13__MAX_BW_MASK 0x001FE000L +#define DAGB1_WRCLI13__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB1_WRCLI13__MIN_BW_MASK 0x01C00000L +#define DAGB1_WRCLI13__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB1_WRCLI13__MAX_OSD_MASK 0xFC000000L +//DAGB1_WRCLI14 +#define DAGB1_WRCLI14__TC__SHIFT 0x0 +#define DAGB1_WRCLI14__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB1_WRCLI14__PRIORITY_ARB1__SHIFT 0x4 +#define DAGB1_WRCLI14__PROFILE_ARB2__SHIFT 0x8 +#define DAGB1_WRCLI14__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB1_WRCLI14__MAX_BW__SHIFT 0xd +#define DAGB1_WRCLI14__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB1_WRCLI14__MIN_BW__SHIFT 0x16 +#define DAGB1_WRCLI14__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB1_WRCLI14__MAX_OSD__SHIFT 0x1a +#define DAGB1_WRCLI14__TC_MASK 0x00000007L +#define DAGB1_WRCLI14__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB1_WRCLI14__PRIORITY_ARB1_MASK 0x000000F0L +#define DAGB1_WRCLI14__PROFILE_ARB2_MASK 0x00000700L +#define DAGB1_WRCLI14__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB1_WRCLI14__MAX_BW_MASK 0x001FE000L +#define DAGB1_WRCLI14__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB1_WRCLI14__MIN_BW_MASK 0x01C00000L +#define DAGB1_WRCLI14__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB1_WRCLI14__MAX_OSD_MASK 0xFC000000L +//DAGB1_WRCLI15 +#define DAGB1_WRCLI15__TC__SHIFT 0x0 +#define DAGB1_WRCLI15__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB1_WRCLI15__PRIORITY_ARB1__SHIFT 0x4 +#define DAGB1_WRCLI15__PROFILE_ARB2__SHIFT 0x8 +#define DAGB1_WRCLI15__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB1_WRCLI15__MAX_BW__SHIFT 0xd +#define DAGB1_WRCLI15__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB1_WRCLI15__MIN_BW__SHIFT 0x16 +#define DAGB1_WRCLI15__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB1_WRCLI15__MAX_OSD__SHIFT 0x1a +#define DAGB1_WRCLI15__TC_MASK 0x00000007L +#define DAGB1_WRCLI15__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB1_WRCLI15__PRIORITY_ARB1_MASK 0x000000F0L +#define DAGB1_WRCLI15__PROFILE_ARB2_MASK 0x00000700L +#define DAGB1_WRCLI15__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB1_WRCLI15__MAX_BW_MASK 0x001FE000L +#define DAGB1_WRCLI15__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB1_WRCLI15__MIN_BW_MASK 0x01C00000L +#define DAGB1_WRCLI15__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB1_WRCLI15__MAX_OSD_MASK 0xFC000000L +//DAGB1_WR_CNTL +#define DAGB1_WR_CNTL__CLI_MAX_BW_WINDOW__SHIFT 0x0 +#define DAGB1_WR_CNTL__CLI_MAX_BW_WINDOW_MASK 0x000001FFL +//DAGB1_WR_ADDR_DAGB +#define DAGB1_WR_ADDR_DAGB__DAGB_ENABLE__SHIFT 0x0 +#define DAGB1_WR_ADDR_DAGB__ENABLE_JUMP_AHEAD__SHIFT 0x4 +#define DAGB1_WR_ADDR_DAGB__DISABLE_SELF_INIT__SHIFT 0x8 +#define DAGB1_WR_ADDR_DAGB__WHOAMI__SHIFT 0x9 +#define DAGB1_WR_ADDR_DAGB__JUMP_MODE__SHIFT 0xf +#define DAGB1_WR_ADDR_DAGB__DAGB_ENABLE_MASK 0x0000000FL +#define DAGB1_WR_ADDR_DAGB__ENABLE_JUMP_AHEAD_MASK 0x000000F0L +#define DAGB1_WR_ADDR_DAGB__DISABLE_SELF_INIT_MASK 0x00000100L +#define DAGB1_WR_ADDR_DAGB__WHOAMI_MASK 0x00007E00L +#define DAGB1_WR_ADDR_DAGB__JUMP_MODE_MASK 0x00008000L +//DAGB1_WR_CGTT_CLK_CTRL +#define DAGB1_WR_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 +#define DAGB1_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x5 +#define DAGB1_WR_CGTT_CLK_CTRL__LS_ASSERT_HYSTERESIS__SHIFT 0xd +#define DAGB1_WR_CGTT_CLK_CTRL__MIN_MGLS__SHIFT 0x1a +#define DAGB1_WR_CGTT_CLK_CTRL__CGLS_DISABLE__SHIFT 0x1d +#define DAGB1_WR_CGTT_CLK_CTRL__LS_DISABLE__SHIFT 0x1e +#define DAGB1_WR_CGTT_CLK_CTRL__BUSY_OVERRIDE__SHIFT 0x1f +#define DAGB1_WR_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000001FL +#define DAGB1_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00001FE0L +#define DAGB1_WR_CGTT_CLK_CTRL__LS_ASSERT_HYSTERESIS_MASK 0x03FFE000L +#define DAGB1_WR_CGTT_CLK_CTRL__MIN_MGLS_MASK 0x1C000000L +#define DAGB1_WR_CGTT_CLK_CTRL__CGLS_DISABLE_MASK 0x20000000L +#define DAGB1_WR_CGTT_CLK_CTRL__LS_DISABLE_MASK 0x40000000L +#define DAGB1_WR_CGTT_CLK_CTRL__BUSY_OVERRIDE_MASK 0x80000000L +//DAGB1_L1TLB_WR_CGTT_CLK_CTRL +#define DAGB1_L1TLB_WR_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 +#define DAGB1_L1TLB_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x5 +#define DAGB1_L1TLB_WR_CGTT_CLK_CTRL__LS_ASSERT_HYSTERESIS__SHIFT 0xd +#define DAGB1_L1TLB_WR_CGTT_CLK_CTRL__MIN_MGLS__SHIFT 0x1a +#define DAGB1_L1TLB_WR_CGTT_CLK_CTRL__CGLS_DISABLE__SHIFT 0x1d +#define DAGB1_L1TLB_WR_CGTT_CLK_CTRL__LS_DISABLE__SHIFT 0x1e +#define DAGB1_L1TLB_WR_CGTT_CLK_CTRL__BUSY_OVERRIDE__SHIFT 0x1f +#define DAGB1_L1TLB_WR_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000001FL +#define DAGB1_L1TLB_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00001FE0L +#define DAGB1_L1TLB_WR_CGTT_CLK_CTRL__LS_ASSERT_HYSTERESIS_MASK 0x03FFE000L +#define DAGB1_L1TLB_WR_CGTT_CLK_CTRL__MIN_MGLS_MASK 0x1C000000L +#define DAGB1_L1TLB_WR_CGTT_CLK_CTRL__CGLS_DISABLE_MASK 0x20000000L +#define DAGB1_L1TLB_WR_CGTT_CLK_CTRL__LS_DISABLE_MASK 0x40000000L +#define DAGB1_L1TLB_WR_CGTT_CLK_CTRL__BUSY_OVERRIDE_MASK 0x80000000L +//DAGB1_WR_ADDR_DAGB_MAX_BURST0 +#define DAGB1_WR_ADDR_DAGB_MAX_BURST0__CLIENT0__SHIFT 0x0 +#define DAGB1_WR_ADDR_DAGB_MAX_BURST0__CLIENT1__SHIFT 0x4 +#define DAGB1_WR_ADDR_DAGB_MAX_BURST0__CLIENT2__SHIFT 0x8 +#define DAGB1_WR_ADDR_DAGB_MAX_BURST0__CLIENT3__SHIFT 0xc +#define DAGB1_WR_ADDR_DAGB_MAX_BURST0__CLIENT4__SHIFT 0x10 +#define DAGB1_WR_ADDR_DAGB_MAX_BURST0__CLIENT5__SHIFT 0x14 +#define DAGB1_WR_ADDR_DAGB_MAX_BURST0__CLIENT6__SHIFT 0x18 +#define DAGB1_WR_ADDR_DAGB_MAX_BURST0__CLIENT7__SHIFT 0x1c +#define DAGB1_WR_ADDR_DAGB_MAX_BURST0__CLIENT0_MASK 0x0000000FL +#define DAGB1_WR_ADDR_DAGB_MAX_BURST0__CLIENT1_MASK 0x000000F0L +#define DAGB1_WR_ADDR_DAGB_MAX_BURST0__CLIENT2_MASK 0x00000F00L +#define DAGB1_WR_ADDR_DAGB_MAX_BURST0__CLIENT3_MASK 0x0000F000L +#define DAGB1_WR_ADDR_DAGB_MAX_BURST0__CLIENT4_MASK 0x000F0000L +#define DAGB1_WR_ADDR_DAGB_MAX_BURST0__CLIENT5_MASK 0x00F00000L +#define DAGB1_WR_ADDR_DAGB_MAX_BURST0__CLIENT6_MASK 0x0F000000L +#define DAGB1_WR_ADDR_DAGB_MAX_BURST0__CLIENT7_MASK 0xF0000000L +//DAGB1_WR_ADDR_DAGB_LAZY_TIMER0 +#define DAGB1_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT0__SHIFT 0x0 +#define DAGB1_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT1__SHIFT 0x4 +#define DAGB1_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT2__SHIFT 0x8 +#define DAGB1_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT3__SHIFT 0xc +#define DAGB1_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT4__SHIFT 0x10 +#define DAGB1_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT5__SHIFT 0x14 +#define DAGB1_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT6__SHIFT 0x18 +#define DAGB1_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT7__SHIFT 0x1c +#define DAGB1_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT0_MASK 0x0000000FL +#define DAGB1_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT1_MASK 0x000000F0L +#define DAGB1_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT2_MASK 0x00000F00L +#define DAGB1_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT3_MASK 0x0000F000L +#define DAGB1_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT4_MASK 0x000F0000L +#define DAGB1_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT5_MASK 0x00F00000L +#define DAGB1_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT6_MASK 0x0F000000L +#define DAGB1_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT7_MASK 0xF0000000L +//DAGB1_WR_ADDR_DAGB_MAX_BURST1 +#define DAGB1_WR_ADDR_DAGB_MAX_BURST1__CLIENT8__SHIFT 0x0 +#define DAGB1_WR_ADDR_DAGB_MAX_BURST1__CLIENT9__SHIFT 0x4 +#define DAGB1_WR_ADDR_DAGB_MAX_BURST1__CLIENT10__SHIFT 0x8 +#define DAGB1_WR_ADDR_DAGB_MAX_BURST1__CLIENT11__SHIFT 0xc +#define DAGB1_WR_ADDR_DAGB_MAX_BURST1__CLIENT12__SHIFT 0x10 +#define DAGB1_WR_ADDR_DAGB_MAX_BURST1__CLIENT13__SHIFT 0x14 +#define DAGB1_WR_ADDR_DAGB_MAX_BURST1__CLIENT14__SHIFT 0x18 +#define DAGB1_WR_ADDR_DAGB_MAX_BURST1__CLIENT15__SHIFT 0x1c +#define DAGB1_WR_ADDR_DAGB_MAX_BURST1__CLIENT8_MASK 0x0000000FL +#define DAGB1_WR_ADDR_DAGB_MAX_BURST1__CLIENT9_MASK 0x000000F0L +#define DAGB1_WR_ADDR_DAGB_MAX_BURST1__CLIENT10_MASK 0x00000F00L +#define DAGB1_WR_ADDR_DAGB_MAX_BURST1__CLIENT11_MASK 0x0000F000L +#define DAGB1_WR_ADDR_DAGB_MAX_BURST1__CLIENT12_MASK 0x000F0000L +#define DAGB1_WR_ADDR_DAGB_MAX_BURST1__CLIENT13_MASK 0x00F00000L +#define DAGB1_WR_ADDR_DAGB_MAX_BURST1__CLIENT14_MASK 0x0F000000L +#define DAGB1_WR_ADDR_DAGB_MAX_BURST1__CLIENT15_MASK 0xF0000000L +//DAGB1_WR_ADDR_DAGB_LAZY_TIMER1 +#define DAGB1_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT8__SHIFT 0x0 +#define DAGB1_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT9__SHIFT 0x4 +#define DAGB1_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT10__SHIFT 0x8 +#define DAGB1_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT11__SHIFT 0xc +#define DAGB1_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT12__SHIFT 0x10 +#define DAGB1_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT13__SHIFT 0x14 +#define DAGB1_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT14__SHIFT 0x18 +#define DAGB1_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT15__SHIFT 0x1c +#define DAGB1_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT8_MASK 0x0000000FL +#define DAGB1_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT9_MASK 0x000000F0L +#define DAGB1_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT10_MASK 0x00000F00L +#define DAGB1_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT11_MASK 0x0000F000L +#define DAGB1_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT12_MASK 0x000F0000L +#define DAGB1_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT13_MASK 0x00F00000L +#define DAGB1_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT14_MASK 0x0F000000L +#define DAGB1_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT15_MASK 0xF0000000L +//DAGB1_WR_DATA_DAGB +#define DAGB1_WR_DATA_DAGB__DAGB_ENABLE__SHIFT 0x0 +#define DAGB1_WR_DATA_DAGB__ENABLE_JUMP_AHEAD__SHIFT 0x4 +#define DAGB1_WR_DATA_DAGB__DISABLE_SELF_INIT__SHIFT 0x8 +#define DAGB1_WR_DATA_DAGB__WHOAMI__SHIFT 0x9 +#define DAGB1_WR_DATA_DAGB__DAGB_ENABLE_MASK 0x0000000FL +#define DAGB1_WR_DATA_DAGB__ENABLE_JUMP_AHEAD_MASK 0x000000F0L +#define DAGB1_WR_DATA_DAGB__DISABLE_SELF_INIT_MASK 0x00000100L +#define DAGB1_WR_DATA_DAGB__WHOAMI_MASK 0x00007E00L +//DAGB1_WR_DATA_DAGB_MAX_BURST0 +#define DAGB1_WR_DATA_DAGB_MAX_BURST0__CLIENT0__SHIFT 0x0 +#define DAGB1_WR_DATA_DAGB_MAX_BURST0__CLIENT1__SHIFT 0x4 +#define DAGB1_WR_DATA_DAGB_MAX_BURST0__CLIENT2__SHIFT 0x8 +#define DAGB1_WR_DATA_DAGB_MAX_BURST0__CLIENT3__SHIFT 0xc +#define DAGB1_WR_DATA_DAGB_MAX_BURST0__CLIENT4__SHIFT 0x10 +#define DAGB1_WR_DATA_DAGB_MAX_BURST0__CLIENT5__SHIFT 0x14 +#define DAGB1_WR_DATA_DAGB_MAX_BURST0__CLIENT6__SHIFT 0x18 +#define DAGB1_WR_DATA_DAGB_MAX_BURST0__CLIENT7__SHIFT 0x1c +#define DAGB1_WR_DATA_DAGB_MAX_BURST0__CLIENT0_MASK 0x0000000FL +#define DAGB1_WR_DATA_DAGB_MAX_BURST0__CLIENT1_MASK 0x000000F0L +#define DAGB1_WR_DATA_DAGB_MAX_BURST0__CLIENT2_MASK 0x00000F00L +#define DAGB1_WR_DATA_DAGB_MAX_BURST0__CLIENT3_MASK 0x0000F000L +#define DAGB1_WR_DATA_DAGB_MAX_BURST0__CLIENT4_MASK 0x000F0000L +#define DAGB1_WR_DATA_DAGB_MAX_BURST0__CLIENT5_MASK 0x00F00000L +#define DAGB1_WR_DATA_DAGB_MAX_BURST0__CLIENT6_MASK 0x0F000000L +#define DAGB1_WR_DATA_DAGB_MAX_BURST0__CLIENT7_MASK 0xF0000000L +//DAGB1_WR_DATA_DAGB_LAZY_TIMER0 +#define DAGB1_WR_DATA_DAGB_LAZY_TIMER0__CLIENT0__SHIFT 0x0 +#define DAGB1_WR_DATA_DAGB_LAZY_TIMER0__CLIENT1__SHIFT 0x4 +#define DAGB1_WR_DATA_DAGB_LAZY_TIMER0__CLIENT2__SHIFT 0x8 +#define DAGB1_WR_DATA_DAGB_LAZY_TIMER0__CLIENT3__SHIFT 0xc +#define DAGB1_WR_DATA_DAGB_LAZY_TIMER0__CLIENT4__SHIFT 0x10 +#define DAGB1_WR_DATA_DAGB_LAZY_TIMER0__CLIENT5__SHIFT 0x14 +#define DAGB1_WR_DATA_DAGB_LAZY_TIMER0__CLIENT6__SHIFT 0x18 +#define DAGB1_WR_DATA_DAGB_LAZY_TIMER0__CLIENT7__SHIFT 0x1c +#define DAGB1_WR_DATA_DAGB_LAZY_TIMER0__CLIENT0_MASK 0x0000000FL +#define DAGB1_WR_DATA_DAGB_LAZY_TIMER0__CLIENT1_MASK 0x000000F0L +#define DAGB1_WR_DATA_DAGB_LAZY_TIMER0__CLIENT2_MASK 0x00000F00L +#define DAGB1_WR_DATA_DAGB_LAZY_TIMER0__CLIENT3_MASK 0x0000F000L +#define DAGB1_WR_DATA_DAGB_LAZY_TIMER0__CLIENT4_MASK 0x000F0000L +#define DAGB1_WR_DATA_DAGB_LAZY_TIMER0__CLIENT5_MASK 0x00F00000L +#define DAGB1_WR_DATA_DAGB_LAZY_TIMER0__CLIENT6_MASK 0x0F000000L +#define DAGB1_WR_DATA_DAGB_LAZY_TIMER0__CLIENT7_MASK 0xF0000000L +//DAGB1_WR_DATA_DAGB_MAX_BURST1 +#define DAGB1_WR_DATA_DAGB_MAX_BURST1__CLIENT8__SHIFT 0x0 +#define DAGB1_WR_DATA_DAGB_MAX_BURST1__CLIENT9__SHIFT 0x4 +#define DAGB1_WR_DATA_DAGB_MAX_BURST1__CLIENT10__SHIFT 0x8 +#define DAGB1_WR_DATA_DAGB_MAX_BURST1__CLIENT11__SHIFT 0xc +#define DAGB1_WR_DATA_DAGB_MAX_BURST1__CLIENT12__SHIFT 0x10 +#define DAGB1_WR_DATA_DAGB_MAX_BURST1__CLIENT13__SHIFT 0x14 +#define DAGB1_WR_DATA_DAGB_MAX_BURST1__CLIENT14__SHIFT 0x18 +#define DAGB1_WR_DATA_DAGB_MAX_BURST1__CLIENT15__SHIFT 0x1c +#define DAGB1_WR_DATA_DAGB_MAX_BURST1__CLIENT8_MASK 0x0000000FL +#define DAGB1_WR_DATA_DAGB_MAX_BURST1__CLIENT9_MASK 0x000000F0L +#define DAGB1_WR_DATA_DAGB_MAX_BURST1__CLIENT10_MASK 0x00000F00L +#define DAGB1_WR_DATA_DAGB_MAX_BURST1__CLIENT11_MASK 0x0000F000L +#define DAGB1_WR_DATA_DAGB_MAX_BURST1__CLIENT12_MASK 0x000F0000L +#define DAGB1_WR_DATA_DAGB_MAX_BURST1__CLIENT13_MASK 0x00F00000L +#define DAGB1_WR_DATA_DAGB_MAX_BURST1__CLIENT14_MASK 0x0F000000L +#define DAGB1_WR_DATA_DAGB_MAX_BURST1__CLIENT15_MASK 0xF0000000L +//DAGB1_WR_DATA_DAGB_LAZY_TIMER1 +#define DAGB1_WR_DATA_DAGB_LAZY_TIMER1__CLIENT8__SHIFT 0x0 +#define DAGB1_WR_DATA_DAGB_LAZY_TIMER1__CLIENT9__SHIFT 0x4 +#define DAGB1_WR_DATA_DAGB_LAZY_TIMER1__CLIENT10__SHIFT 0x8 +#define DAGB1_WR_DATA_DAGB_LAZY_TIMER1__CLIENT11__SHIFT 0xc +#define DAGB1_WR_DATA_DAGB_LAZY_TIMER1__CLIENT12__SHIFT 0x10 +#define DAGB1_WR_DATA_DAGB_LAZY_TIMER1__CLIENT13__SHIFT 0x14 +#define DAGB1_WR_DATA_DAGB_LAZY_TIMER1__CLIENT14__SHIFT 0x18 +#define DAGB1_WR_DATA_DAGB_LAZY_TIMER1__CLIENT15__SHIFT 0x1c +#define DAGB1_WR_DATA_DAGB_LAZY_TIMER1__CLIENT8_MASK 0x0000000FL +#define DAGB1_WR_DATA_DAGB_LAZY_TIMER1__CLIENT9_MASK 0x000000F0L +#define DAGB1_WR_DATA_DAGB_LAZY_TIMER1__CLIENT10_MASK 0x00000F00L +#define DAGB1_WR_DATA_DAGB_LAZY_TIMER1__CLIENT11_MASK 0x0000F000L +#define DAGB1_WR_DATA_DAGB_LAZY_TIMER1__CLIENT12_MASK 0x000F0000L +#define DAGB1_WR_DATA_DAGB_LAZY_TIMER1__CLIENT13_MASK 0x00F00000L +#define DAGB1_WR_DATA_DAGB_LAZY_TIMER1__CLIENT14_MASK 0x0F000000L +#define DAGB1_WR_DATA_DAGB_LAZY_TIMER1__CLIENT15_MASK 0xF0000000L +//DAGB1_WR_CNTL_MISC +#define DAGB1_WR_CNTL_MISC__HDP_CID__SHIFT 0x6 +#define DAGB1_WR_CNTL_MISC__CLI_SWITCH_MODE__SHIFT 0xb +#define DAGB1_WR_CNTL_MISC__CREDIT_SWITCH_MODE__SHIFT 0xd +#define DAGB1_WR_CNTL_MISC__BUDGET_SWITCH_MODE__SHIFT 0xf +#define DAGB1_WR_CNTL_MISC__CLI_CLEAN_MODE__SHIFT 0x11 +#define DAGB1_WR_CNTL_MISC__HDP_CID_MASK 0x000007C0L +#define DAGB1_WR_CNTL_MISC__CLI_SWITCH_MODE_MASK 0x00001800L +#define DAGB1_WR_CNTL_MISC__CREDIT_SWITCH_MODE_MASK 0x00006000L +#define DAGB1_WR_CNTL_MISC__BUDGET_SWITCH_MODE_MASK 0x00018000L +#define DAGB1_WR_CNTL_MISC__CLI_CLEAN_MODE_MASK 0x00020000L +//DAGB1_WR_TLB_CREDIT +#define DAGB1_WR_TLB_CREDIT__TLB0__SHIFT 0x0 +#define DAGB1_WR_TLB_CREDIT__TLB1__SHIFT 0x5 +#define DAGB1_WR_TLB_CREDIT__TLB2__SHIFT 0xa +#define DAGB1_WR_TLB_CREDIT__TLB3__SHIFT 0xf +#define DAGB1_WR_TLB_CREDIT__TLB0_MASK 0x0000001FL +#define DAGB1_WR_TLB_CREDIT__TLB1_MASK 0x000003E0L +#define DAGB1_WR_TLB_CREDIT__TLB2_MASK 0x00007C00L +#define DAGB1_WR_TLB_CREDIT__TLB3_MASK 0x000F8000L +//DAGB1_WR_ATOMIC_FIFO_CREDIT_CNTL1 +#define DAGB1_WR_ATOMIC_FIFO_CREDIT_CNTL1__TC0_CREDIT__SHIFT 0x0 +#define DAGB1_WR_ATOMIC_FIFO_CREDIT_CNTL1__TC1_CREDIT__SHIFT 0x5 +#define DAGB1_WR_ATOMIC_FIFO_CREDIT_CNTL1__TC2_CREDIT__SHIFT 0xa +#define DAGB1_WR_ATOMIC_FIFO_CREDIT_CNTL1__POOL_CREDIT__SHIFT 0x14 +#define DAGB1_WR_ATOMIC_FIFO_CREDIT_CNTL1__FIX_EQ_STORE__SHIFT 0x1b +#define DAGB1_WR_ATOMIC_FIFO_CREDIT_CNTL1__FIX_EQ_ATOMIC__SHIFT 0x1c +#define DAGB1_WR_ATOMIC_FIFO_CREDIT_CNTL1__TC0_CREDIT_MASK 0x0000001FL +#define DAGB1_WR_ATOMIC_FIFO_CREDIT_CNTL1__TC1_CREDIT_MASK 0x000003E0L +#define DAGB1_WR_ATOMIC_FIFO_CREDIT_CNTL1__TC2_CREDIT_MASK 0x00007C00L +#define DAGB1_WR_ATOMIC_FIFO_CREDIT_CNTL1__POOL_CREDIT_MASK 0x03F00000L +#define DAGB1_WR_ATOMIC_FIFO_CREDIT_CNTL1__FIX_EQ_STORE_MASK 0x08000000L +#define DAGB1_WR_ATOMIC_FIFO_CREDIT_CNTL1__FIX_EQ_ATOMIC_MASK 0x10000000L +//DAGB1_WRCLI_ASK_PENDING +#define DAGB1_WRCLI_ASK_PENDING__BUSY__SHIFT 0x0 +#define DAGB1_WRCLI_ASK_PENDING__BUSY_MASK 0x00FFFFFFL +//DAGB1_WRCLI_GO_PENDING +#define DAGB1_WRCLI_GO_PENDING__BUSY__SHIFT 0x0 +#define DAGB1_WRCLI_GO_PENDING__BUSY_MASK 0x00FFFFFFL +//DAGB1_WRCLI_GBLSEND_PENDING +#define DAGB1_WRCLI_GBLSEND_PENDING__BUSY__SHIFT 0x0 +#define DAGB1_WRCLI_GBLSEND_PENDING__BUSY_MASK 0x00FFFFFFL +//DAGB1_WRCLI_TLB_PENDING +#define DAGB1_WRCLI_TLB_PENDING__BUSY__SHIFT 0x0 +#define DAGB1_WRCLI_TLB_PENDING__BUSY_MASK 0x00FFFFFFL +//DAGB1_WRCLI_OARB_PENDING +#define DAGB1_WRCLI_OARB_PENDING__BUSY__SHIFT 0x0 +#define DAGB1_WRCLI_OARB_PENDING__BUSY_MASK 0x00FFFFFFL +//DAGB1_WRCLI_OSD_PENDING +#define DAGB1_WRCLI_OSD_PENDING__BUSY__SHIFT 0x0 +#define DAGB1_WRCLI_OSD_PENDING__BUSY_MASK 0x00FFFFFFL +//DAGB1_WRCLI_DBUS_ASK_PENDING +#define DAGB1_WRCLI_DBUS_ASK_PENDING__BUSY__SHIFT 0x0 +#define DAGB1_WRCLI_DBUS_ASK_PENDING__BUSY_MASK 0x00FFFFFFL +//DAGB1_WRCLI_DBUS_GO_PENDING +#define DAGB1_WRCLI_DBUS_GO_PENDING__BUSY__SHIFT 0x0 +#define DAGB1_WRCLI_DBUS_GO_PENDING__BUSY_MASK 0x00FFFFFFL +//DAGB1_SDP_ERR_STATUS +#define DAGB1_SDP_ERR_STATUS__SDP_RDRSP_STATUS__SHIFT 0x0 +#define DAGB1_SDP_ERR_STATUS__SDP_WRRSP_STATUS__SHIFT 0x4 +#define DAGB1_SDP_ERR_STATUS__SDP_RDRSP_DATASTATUS__SHIFT 0x8 +#define DAGB1_SDP_ERR_STATUS__SDP_RDRSP_METADATA_ERROR__SHIFT 0xa +#define DAGB1_SDP_ERR_STATUS__SDP_RDRSP_DATAPARITY_ERROR__SHIFT 0xb +#define DAGB1_SDP_ERR_STATUS__WR_DATAPARITY_ERROR__SHIFT 0xc +#define DAGB1_SDP_ERR_STATUS__CLEAR_ERROR_STATUS__SHIFT 0xd +#define DAGB1_SDP_ERR_STATUS__BUSY_ON_ERROR__SHIFT 0xe +#define DAGB1_SDP_ERR_STATUS__FATAL_FLAG__SHIFT 0xf +#define DAGB1_SDP_ERR_STATUS__FUE_FLAG__SHIFT 0x10 +#define DAGB1_SDP_ERR_STATUS__FUE_FLAG_CLIENT__SHIFT 0x11 +#define DAGB1_SDP_ERR_STATUS__SDP_RDRSP_STATUS_MASK 0x0000000FL +#define DAGB1_SDP_ERR_STATUS__SDP_WRRSP_STATUS_MASK 0x000000F0L +#define DAGB1_SDP_ERR_STATUS__SDP_RDRSP_DATASTATUS_MASK 0x00000300L +#define DAGB1_SDP_ERR_STATUS__SDP_RDRSP_METADATA_ERROR_MASK 0x00000400L +#define DAGB1_SDP_ERR_STATUS__SDP_RDRSP_DATAPARITY_ERROR_MASK 0x00000800L +#define DAGB1_SDP_ERR_STATUS__WR_DATAPARITY_ERROR_MASK 0x00001000L +#define DAGB1_SDP_ERR_STATUS__CLEAR_ERROR_STATUS_MASK 0x00002000L +#define DAGB1_SDP_ERR_STATUS__BUSY_ON_ERROR_MASK 0x00004000L +#define DAGB1_SDP_ERR_STATUS__FATAL_FLAG_MASK 0x00008000L +#define DAGB1_SDP_ERR_STATUS__FUE_FLAG_MASK 0x00010000L +#define DAGB1_SDP_ERR_STATUS__FUE_FLAG_CLIENT_MASK 0x00020000L +//DAGB1_DAGB_DLY +#define DAGB1_DAGB_DLY__DLY__SHIFT 0x0 +#define DAGB1_DAGB_DLY__CLI__SHIFT 0x8 +#define DAGB1_DAGB_DLY__POS__SHIFT 0x10 +#define DAGB1_DAGB_DLY__DLY_MASK 0x000000FFL +#define DAGB1_DAGB_DLY__CLI_MASK 0x0000FF00L +#define DAGB1_DAGB_DLY__POS_MASK 0x000F0000L +//DAGB1_CNTL_MISC +#define DAGB1_CNTL_MISC__BW_INIT_CYCLE__SHIFT 0x0 +#define DAGB1_CNTL_MISC__OVERRIDE_ILLEGAL_REQ__SHIFT 0x6 +#define DAGB1_CNTL_MISC__BW_INIT_CYCLE_MASK 0x0000003FL +#define DAGB1_CNTL_MISC__OVERRIDE_ILLEGAL_REQ_MASK 0x00000040L +//DAGB1_CNTL_MISC2 +#define DAGB1_CNTL_MISC2__DAGB_BUSY_OVERRIDE__SHIFT 0x0 +#define DAGB1_CNTL_MISC2__SWAP_CTL__SHIFT 0x1 +#define DAGB1_CNTL_MISC2__RDRET_FIFO_PERF__SHIFT 0x2 +#define DAGB1_CNTL_MISC2__DISABLE_RDRET_TAP_CHAIN_FGCG__SHIFT 0x3 +#define DAGB1_CNTL_MISC2__DISABLE_WRRET_TAP_CHAIN_FGCG__SHIFT 0x4 +#define DAGB1_CNTL_MISC2__DISABLE_MCA_INTR_REQ_FGCG__SHIFT 0x5 +#define DAGB1_CNTL_MISC2__DAGB_BUSY_OVERRIDE_MASK 0x00000001L +#define DAGB1_CNTL_MISC2__SWAP_CTL_MASK 0x00000002L +#define DAGB1_CNTL_MISC2__RDRET_FIFO_PERF_MASK 0x00000004L +#define DAGB1_CNTL_MISC2__DISABLE_RDRET_TAP_CHAIN_FGCG_MASK 0x00000008L +#define DAGB1_CNTL_MISC2__DISABLE_WRRET_TAP_CHAIN_FGCG_MASK 0x00000010L +#define DAGB1_CNTL_MISC2__DISABLE_MCA_INTR_REQ_FGCG_MASK 0x00000020L +//DAGB1_FIFO_EMPTY +#define DAGB1_FIFO_EMPTY__EMPTY__SHIFT 0x0 +#define DAGB1_FIFO_EMPTY__EMPTY_MASK 0xFFFFFFFFL +//DAGB1_FIFO_FULL +#define DAGB1_FIFO_FULL__FULL__SHIFT 0x0 +#define DAGB1_FIFO_FULL__FULL_MASK 0xFFFFFFFFL +//DAGB1_RD_CREDITS_FULL +#define DAGB1_RD_CREDITS_FULL__FULL__SHIFT 0x0 +#define DAGB1_RD_CREDITS_FULL__FULL_MASK 0x0000007FL +//DAGB1_WR_CREDITS_FULL +#define DAGB1_WR_CREDITS_FULL__FULL__SHIFT 0x0 +#define DAGB1_WR_CREDITS_FULL__FULL_MASK 0x0001FFFFL +//DAGB1_PERFCOUNTER_LO +#define DAGB1_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0 +#define DAGB1_PERFCOUNTER_LO__COUNTER_LO_MASK 0xFFFFFFFFL +//DAGB1_PERFCOUNTER_HI +#define DAGB1_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0 +#define DAGB1_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10 +#define DAGB1_PERFCOUNTER_HI__COUNTER_HI_MASK 0x0000FFFFL +#define DAGB1_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xFFFF0000L +//DAGB1_PERFCOUNTER0_CFG +#define DAGB1_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0 +#define DAGB1_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8 +#define DAGB1_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18 +#define DAGB1_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c +#define DAGB1_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d +#define DAGB1_PERFCOUNTER0_CFG__PERF_SEL_MASK 0x000000FFL +#define DAGB1_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0x0000FF00L +#define DAGB1_PERFCOUNTER0_CFG__PERF_MODE_MASK 0x0F000000L +#define DAGB1_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000L +#define DAGB1_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000L +//DAGB1_PERFCOUNTER1_CFG +#define DAGB1_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0 +#define DAGB1_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8 +#define DAGB1_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18 +#define DAGB1_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c +#define DAGB1_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d +#define DAGB1_PERFCOUNTER1_CFG__PERF_SEL_MASK 0x000000FFL +#define DAGB1_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0x0000FF00L +#define DAGB1_PERFCOUNTER1_CFG__PERF_MODE_MASK 0x0F000000L +#define DAGB1_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000L +#define DAGB1_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000L +//DAGB1_PERFCOUNTER2_CFG +#define DAGB1_PERFCOUNTER2_CFG__PERF_SEL__SHIFT 0x0 +#define DAGB1_PERFCOUNTER2_CFG__PERF_SEL_END__SHIFT 0x8 +#define DAGB1_PERFCOUNTER2_CFG__PERF_MODE__SHIFT 0x18 +#define DAGB1_PERFCOUNTER2_CFG__ENABLE__SHIFT 0x1c +#define DAGB1_PERFCOUNTER2_CFG__CLEAR__SHIFT 0x1d +#define DAGB1_PERFCOUNTER2_CFG__PERF_SEL_MASK 0x000000FFL +#define DAGB1_PERFCOUNTER2_CFG__PERF_SEL_END_MASK 0x0000FF00L +#define DAGB1_PERFCOUNTER2_CFG__PERF_MODE_MASK 0x0F000000L +#define DAGB1_PERFCOUNTER2_CFG__ENABLE_MASK 0x10000000L +#define DAGB1_PERFCOUNTER2_CFG__CLEAR_MASK 0x20000000L +//DAGB1_PERFCOUNTER_RSLT_CNTL +#define DAGB1_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0 +#define DAGB1_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8 +#define DAGB1_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10 +#define DAGB1_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18 +#define DAGB1_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19 +#define DAGB1_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a +#define DAGB1_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0x00000007L +#define DAGB1_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0x0000FF00L +#define DAGB1_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0x00FF0000L +#define DAGB1_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x01000000L +#define DAGB1_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x02000000L +#define DAGB1_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x04000000L +//DAGB1_L1TLB_REG_RW +#define DAGB1_L1TLB_REG_RW__REG_WRITE_L1TLB_CTRL__SHIFT 0x0 +#define DAGB1_L1TLB_REG_RW__REG_READ_L1TLB_CTRL__SHIFT 0x1 +#define DAGB1_L1TLB_REG_RW__REG_WRITE_L1TLB_CTRL_MASK 0x00000001L +#define DAGB1_L1TLB_REG_RW__REG_READ_L1TLB_CTRL_MASK 0x00000002L +//DAGB1_RESERVE0 +#define DAGB1_RESERVE0__RESERVE__SHIFT 0x0 +#define DAGB1_RESERVE0__RESERVE_MASK 0xFFFFFFFFL +//DAGB1_RESERVE1 +#define DAGB1_RESERVE1__RESERVE__SHIFT 0x0 +#define DAGB1_RESERVE1__RESERVE_MASK 0xFFFFFFFFL +//DAGB1_RESERVE2 +#define DAGB1_RESERVE2__RESERVE__SHIFT 0x0 +#define DAGB1_RESERVE2__RESERVE_MASK 0xFFFFFFFFL +//DAGB1_RESERVE3 +#define DAGB1_RESERVE3__RESERVE__SHIFT 0x0 +#define DAGB1_RESERVE3__RESERVE_MASK 0xFFFFFFFFL +//DAGB1_SDP_RD_BW_CNTL +#define DAGB1_SDP_RD_BW_CNTL__MAX_BW_ENABLE__SHIFT 0x0 +#define DAGB1_SDP_RD_BW_CNTL__MAX_BW__SHIFT 0x1 +#define DAGB1_SDP_RD_BW_CNTL__MIN_BW_ENABLE__SHIFT 0xc +#define DAGB1_SDP_RD_BW_CNTL__MIN_BW__SHIFT 0xd +#define DAGB1_SDP_RD_BW_CNTL__MAX_BW_WINDOW__SHIFT 0x13 +#define DAGB1_SDP_RD_BW_CNTL__MAX_BW_ENABLE_MASK 0x00000001L +#define DAGB1_SDP_RD_BW_CNTL__MAX_BW_MASK 0x000003FEL +#define DAGB1_SDP_RD_BW_CNTL__MIN_BW_ENABLE_MASK 0x00001000L +#define DAGB1_SDP_RD_BW_CNTL__MIN_BW_MASK 0x0007E000L +#define DAGB1_SDP_RD_BW_CNTL__MAX_BW_WINDOW_MASK 0x0FF80000L +//DAGB1_SDP_RD_PRIORITY +#define DAGB1_SDP_RD_PRIORITY__VC0__SHIFT 0x0 +#define DAGB1_SDP_RD_PRIORITY__VC1__SHIFT 0x4 +#define DAGB1_SDP_RD_PRIORITY__VC2__SHIFT 0x8 +#define DAGB1_SDP_RD_PRIORITY__VC3__SHIFT 0xc +#define DAGB1_SDP_RD_PRIORITY__VC4__SHIFT 0x10 +#define DAGB1_SDP_RD_PRIORITY__VC5__SHIFT 0x14 +#define DAGB1_SDP_RD_PRIORITY__VC6__SHIFT 0x18 +#define DAGB1_SDP_RD_PRIORITY__VC7__SHIFT 0x1c +#define DAGB1_SDP_RD_PRIORITY__VC0_MASK 0x0000000FL +#define DAGB1_SDP_RD_PRIORITY__VC1_MASK 0x000000F0L +#define DAGB1_SDP_RD_PRIORITY__VC2_MASK 0x00000F00L +#define DAGB1_SDP_RD_PRIORITY__VC3_MASK 0x0000F000L +#define DAGB1_SDP_RD_PRIORITY__VC4_MASK 0x000F0000L +#define DAGB1_SDP_RD_PRIORITY__VC5_MASK 0x00F00000L +#define DAGB1_SDP_RD_PRIORITY__VC6_MASK 0x0F000000L +#define DAGB1_SDP_RD_PRIORITY__VC7_MASK 0xF0000000L +//DAGB1_SDP_RD_CLI2SDP_VC_MAP +#define DAGB1_SDP_RD_CLI2SDP_VC_MAP__SRT_VC_MAP__SHIFT 0x0 +#define DAGB1_SDP_RD_CLI2SDP_VC_MAP__NRT_VC_MAP__SHIFT 0x3 +#define DAGB1_SDP_RD_CLI2SDP_VC_MAP__DLOCK_VC_MAP__SHIFT 0x6 +#define DAGB1_SDP_RD_CLI2SDP_VC_MAP__HRT_VC_MAP__SHIFT 0x9 +#define DAGB1_SDP_RD_CLI2SDP_VC_MAP__IO_VC_MAP__SHIFT 0xc +#define DAGB1_SDP_RD_CLI2SDP_VC_MAP__SRT_VC_MAP_MASK 0x00000007L +#define DAGB1_SDP_RD_CLI2SDP_VC_MAP__NRT_VC_MAP_MASK 0x00000038L +#define DAGB1_SDP_RD_CLI2SDP_VC_MAP__DLOCK_VC_MAP_MASK 0x000001C0L +#define DAGB1_SDP_RD_CLI2SDP_VC_MAP__HRT_VC_MAP_MASK 0x00000E00L +#define DAGB1_SDP_RD_CLI2SDP_VC_MAP__IO_VC_MAP_MASK 0x00007000L +//DAGB1_SDP_ENABLE +#define DAGB1_SDP_ENABLE__ENABLE__SHIFT 0x0 +#define DAGB1_SDP_ENABLE__ENABLE_MASK 0x00000001L +//DAGB1_SDP_CREDITS +#define DAGB1_SDP_CREDITS__TAG_LIMIT__SHIFT 0x0 +#define DAGB1_SDP_CREDITS__WR_RESP_CREDITS__SHIFT 0x8 +#define DAGB1_SDP_CREDITS__RD_RESP_CREDITS__SHIFT 0x10 +#define DAGB1_SDP_CREDITS__TAG_LIMIT_MASK 0x000000FFL +#define DAGB1_SDP_CREDITS__WR_RESP_CREDITS_MASK 0x00007F00L +#define DAGB1_SDP_CREDITS__RD_RESP_CREDITS_MASK 0x01FF0000L +//DAGB1_SDP_TAG_RESERVE0 +#define DAGB1_SDP_TAG_RESERVE0__VC0__SHIFT 0x0 +#define DAGB1_SDP_TAG_RESERVE0__VC1__SHIFT 0x8 +#define DAGB1_SDP_TAG_RESERVE0__VC2__SHIFT 0x10 +#define DAGB1_SDP_TAG_RESERVE0__VC3__SHIFT 0x18 +#define DAGB1_SDP_TAG_RESERVE0__VC0_MASK 0x000000FFL +#define DAGB1_SDP_TAG_RESERVE0__VC1_MASK 0x0000FF00L +#define DAGB1_SDP_TAG_RESERVE0__VC2_MASK 0x00FF0000L +#define DAGB1_SDP_TAG_RESERVE0__VC3_MASK 0xFF000000L +//DAGB1_SDP_TAG_RESERVE1 +#define DAGB1_SDP_TAG_RESERVE1__VC4__SHIFT 0x0 +#define DAGB1_SDP_TAG_RESERVE1__VC5__SHIFT 0x8 +#define DAGB1_SDP_TAG_RESERVE1__VC6__SHIFT 0x10 +#define DAGB1_SDP_TAG_RESERVE1__VC7__SHIFT 0x18 +#define DAGB1_SDP_TAG_RESERVE1__VC4_MASK 0x000000FFL +#define DAGB1_SDP_TAG_RESERVE1__VC5_MASK 0x0000FF00L +#define DAGB1_SDP_TAG_RESERVE1__VC6_MASK 0x00FF0000L +#define DAGB1_SDP_TAG_RESERVE1__VC7_MASK 0xFF000000L +//DAGB1_SDP_VCC_RESERVE0 +#define DAGB1_SDP_VCC_RESERVE0__VC0_CREDITS__SHIFT 0x0 +#define DAGB1_SDP_VCC_RESERVE0__VC1_CREDITS__SHIFT 0x6 +#define DAGB1_SDP_VCC_RESERVE0__VC2_CREDITS__SHIFT 0xc +#define DAGB1_SDP_VCC_RESERVE0__VC3_CREDITS__SHIFT 0x12 +#define DAGB1_SDP_VCC_RESERVE0__VC4_CREDITS__SHIFT 0x18 +#define DAGB1_SDP_VCC_RESERVE0__VC0_CREDITS_MASK 0x0000003FL +#define DAGB1_SDP_VCC_RESERVE0__VC1_CREDITS_MASK 0x00000FC0L +#define DAGB1_SDP_VCC_RESERVE0__VC2_CREDITS_MASK 0x0003F000L +#define DAGB1_SDP_VCC_RESERVE0__VC3_CREDITS_MASK 0x00FC0000L +#define DAGB1_SDP_VCC_RESERVE0__VC4_CREDITS_MASK 0x3F000000L +//DAGB1_SDP_VCC_RESERVE1 +#define DAGB1_SDP_VCC_RESERVE1__VC5_CREDITS__SHIFT 0x0 +#define DAGB1_SDP_VCC_RESERVE1__VC6_CREDITS__SHIFT 0x6 +#define DAGB1_SDP_VCC_RESERVE1__VC7_CREDITS__SHIFT 0xc +#define DAGB1_SDP_VCC_RESERVE1__DISTRIBUTE_POOL__SHIFT 0x1f +#define DAGB1_SDP_VCC_RESERVE1__VC5_CREDITS_MASK 0x0000003FL +#define DAGB1_SDP_VCC_RESERVE1__VC6_CREDITS_MASK 0x00000FC0L +#define DAGB1_SDP_VCC_RESERVE1__VC7_CREDITS_MASK 0x0003F000L +#define DAGB1_SDP_VCC_RESERVE1__DISTRIBUTE_POOL_MASK 0x80000000L +//DAGB1_SDP_REQ_CNTL +#define DAGB1_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_READ__SHIFT 0x0 +#define DAGB1_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_WRITE__SHIFT 0x1 +#define DAGB1_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_ATOMIC__SHIFT 0x2 +#define DAGB1_SDP_REQ_CNTL__REQ_CHAIN_OVERRIDE_DRAM__SHIFT 0x3 +#define DAGB1_SDP_REQ_CNTL__REQ_CHAIN_OVERRIDE_GMI__SHIFT 0x4 +#define DAGB1_SDP_REQ_CNTL__INNER_DOMAIN_MODE__SHIFT 0x5 +#define DAGB1_SDP_REQ_CNTL__OVERRIDE_DOMAIN_EN__SHIFT 0x6 +#define DAGB1_SDP_REQ_CNTL__OVERRIDE_DOMAIN__SHIFT 0x7 +#define DAGB1_SDP_REQ_CNTL__REQ_BLOCK_LEVEL_READ__SHIFT 0x8 +#define DAGB1_SDP_REQ_CNTL__REQ_BLOCK_LEVEL_WRITE__SHIFT 0xa +#define DAGB1_SDP_REQ_CNTL__REQ_BLOCK_LEVEL_ATOMIC__SHIFT 0xc +#define DAGB1_SDP_REQ_CNTL__DRAM_LEGACY_WR_64B_ALIGN__SHIFT 0xe +#define DAGB1_SDP_REQ_CNTL__DRAM_LARGE_WR_64B_UPSIZE__SHIFT 0xf +#define DAGB1_SDP_REQ_CNTL__DRAM_RD_64B_ALIGN_UPSIZE__SHIFT 0x10 +#define DAGB1_SDP_REQ_CNTL__IO_LEGACY_WR_64B_ALIGN__SHIFT 0x12 +#define DAGB1_SDP_REQ_CNTL__IO_LARGE_WR_64B_UPSIZE__SHIFT 0x13 +#define DAGB1_SDP_REQ_CNTL__IO_RD_64B_ALIGN_UPSIZE__SHIFT 0x14 +#define DAGB1_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_READ_MASK 0x00000001L +#define DAGB1_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_WRITE_MASK 0x00000002L +#define DAGB1_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_ATOMIC_MASK 0x00000004L +#define DAGB1_SDP_REQ_CNTL__REQ_CHAIN_OVERRIDE_DRAM_MASK 0x00000008L +#define DAGB1_SDP_REQ_CNTL__REQ_CHAIN_OVERRIDE_GMI_MASK 0x00000010L +#define DAGB1_SDP_REQ_CNTL__INNER_DOMAIN_MODE_MASK 0x00000020L +#define DAGB1_SDP_REQ_CNTL__OVERRIDE_DOMAIN_EN_MASK 0x00000040L +#define DAGB1_SDP_REQ_CNTL__OVERRIDE_DOMAIN_MASK 0x00000080L +#define DAGB1_SDP_REQ_CNTL__REQ_BLOCK_LEVEL_READ_MASK 0x00000300L +#define DAGB1_SDP_REQ_CNTL__REQ_BLOCK_LEVEL_WRITE_MASK 0x00000C00L +#define DAGB1_SDP_REQ_CNTL__REQ_BLOCK_LEVEL_ATOMIC_MASK 0x00003000L +#define DAGB1_SDP_REQ_CNTL__DRAM_LEGACY_WR_64B_ALIGN_MASK 0x00004000L +#define DAGB1_SDP_REQ_CNTL__DRAM_LARGE_WR_64B_UPSIZE_MASK 0x00008000L +#define DAGB1_SDP_REQ_CNTL__DRAM_RD_64B_ALIGN_UPSIZE_MASK 0x00030000L +#define DAGB1_SDP_REQ_CNTL__IO_LEGACY_WR_64B_ALIGN_MASK 0x00040000L +#define DAGB1_SDP_REQ_CNTL__IO_LARGE_WR_64B_UPSIZE_MASK 0x00080000L +#define DAGB1_SDP_REQ_CNTL__IO_RD_64B_ALIGN_UPSIZE_MASK 0x00300000L +//DAGB1_SDP_MISC_AON +#define DAGB1_SDP_MISC_AON__LINKMGR_PARTACK_HYSTERESIS__SHIFT 0x0 +#define DAGB1_SDP_MISC_AON__LINKMGR_PARTACK_DEASSERT_MODE__SHIFT 0x2 +#define DAGB1_SDP_MISC_AON__LINKMGR_PARTACK_HYSTERESIS_MASK 0x00000003L +#define DAGB1_SDP_MISC_AON__LINKMGR_PARTACK_DEASSERT_MODE_MASK 0x00000004L +//DAGB1_SDP_MISC +#define DAGB1_SDP_MISC__EARLYWRRET_ENABLE_VC0__SHIFT 0x0 +#define DAGB1_SDP_MISC__EARLYWRRET_ENABLE_VC1__SHIFT 0x1 +#define DAGB1_SDP_MISC__EARLYWRRET_ENABLE_VC2__SHIFT 0x2 +#define DAGB1_SDP_MISC__EARLYWRRET_ENABLE_VC3__SHIFT 0x3 +#define DAGB1_SDP_MISC__EARLYWRRET_ENABLE_VC4__SHIFT 0x4 +#define DAGB1_SDP_MISC__EARLYWRRET_ENABLE_VC5__SHIFT 0x5 +#define DAGB1_SDP_MISC__EARLYWRRET_ENABLE_VC6__SHIFT 0x6 +#define DAGB1_SDP_MISC__EARLYWRRET_ENABLE_VC7__SHIFT 0x7 +#define DAGB1_SDP_MISC__EARLY_SDP_ORIGDATA__SHIFT 0x8 +#define DAGB1_SDP_MISC__LINKMGR_DYNAMIC_MODE__SHIFT 0x9 +#define DAGB1_SDP_MISC__LINKMGR_HALT_THRESHOLD__SHIFT 0xb +#define DAGB1_SDP_MISC__LINKMGR_RECONNECT_DELAY__SHIFT 0xd +#define DAGB1_SDP_MISC__LINKMGR_IDLE_THRESHOLD__SHIFT 0xf +#define DAGB1_SDP_MISC__SDP_DAT_FIFO0_MARGIN__SHIFT 0x14 +#define DAGB1_SDP_MISC__SDP_DAT_FIFO1_MARGIN__SHIFT 0x16 +#define DAGB1_SDP_MISC__SDP_DAT_FIFO2_MARGIN__SHIFT 0x18 +#define DAGB1_SDP_MISC__EARLYWRRET_ENABLE_VC0_MASK 0x00000001L +#define DAGB1_SDP_MISC__EARLYWRRET_ENABLE_VC1_MASK 0x00000002L +#define DAGB1_SDP_MISC__EARLYWRRET_ENABLE_VC2_MASK 0x00000004L +#define DAGB1_SDP_MISC__EARLYWRRET_ENABLE_VC3_MASK 0x00000008L +#define DAGB1_SDP_MISC__EARLYWRRET_ENABLE_VC4_MASK 0x00000010L +#define DAGB1_SDP_MISC__EARLYWRRET_ENABLE_VC5_MASK 0x00000020L +#define DAGB1_SDP_MISC__EARLYWRRET_ENABLE_VC6_MASK 0x00000040L +#define DAGB1_SDP_MISC__EARLYWRRET_ENABLE_VC7_MASK 0x00000080L +#define DAGB1_SDP_MISC__EARLY_SDP_ORIGDATA_MASK 0x00000100L +#define DAGB1_SDP_MISC__LINKMGR_DYNAMIC_MODE_MASK 0x00000600L +#define DAGB1_SDP_MISC__LINKMGR_HALT_THRESHOLD_MASK 0x00001800L +#define DAGB1_SDP_MISC__LINKMGR_RECONNECT_DELAY_MASK 0x00006000L +#define DAGB1_SDP_MISC__LINKMGR_IDLE_THRESHOLD_MASK 0x000F8000L +#define DAGB1_SDP_MISC__SDP_DAT_FIFO0_MARGIN_MASK 0x00300000L +#define DAGB1_SDP_MISC__SDP_DAT_FIFO1_MARGIN_MASK 0x00C00000L +#define DAGB1_SDP_MISC__SDP_DAT_FIFO2_MARGIN_MASK 0x07000000L +//DAGB1_SDP_MISC2 +#define DAGB1_SDP_MISC2__RRET_SWAP_MODE__SHIFT 0x0 +#define DAGB1_SDP_MISC2__BLOCK_REQUESTS__SHIFT 0x1 +#define DAGB1_SDP_MISC2__REQUESTS_BLOCKED__SHIFT 0x2 +#define DAGB1_SDP_MISC2__RRET_SWAP_MODE_MASK 0x00000001L +#define DAGB1_SDP_MISC2__BLOCK_REQUESTS_MASK 0x00000002L +#define DAGB1_SDP_MISC2__REQUESTS_BLOCKED_MASK 0x00000004L +//DAGB1_SDP_ARB_CNTL0 +#define DAGB1_SDP_ARB_CNTL0__EARLY_SW2RD_ON_PRI__SHIFT 0x0 +#define DAGB1_SDP_ARB_CNTL0__EARLY_SW2WR_ON_PRI__SHIFT 0x1 +#define DAGB1_SDP_ARB_CNTL0__EARLY_SW2RD_ON_RES__SHIFT 0x2 +#define DAGB1_SDP_ARB_CNTL0__EARLY_SW2WR_ON_RES__SHIFT 0x3 +#define DAGB1_SDP_ARB_CNTL0__EARLY_SW2RD_ON_PRI_MASK 0x00000001L +#define DAGB1_SDP_ARB_CNTL0__EARLY_SW2WR_ON_PRI_MASK 0x00000002L +#define DAGB1_SDP_ARB_CNTL0__EARLY_SW2RD_ON_RES_MASK 0x00000004L +#define DAGB1_SDP_ARB_CNTL0__EARLY_SW2WR_ON_RES_MASK 0x00000008L +//DAGB1_SDP_ARB_CNTL1 +#define DAGB1_SDP_ARB_CNTL1__RD_BURST_LIMIT_CYCL__SHIFT 0x0 +#define DAGB1_SDP_ARB_CNTL1__WR_BURST_LIMIT_CYCL__SHIFT 0x7 +#define DAGB1_SDP_ARB_CNTL1__RD_BURST_LIMIT_DATA__SHIFT 0xe +#define DAGB1_SDP_ARB_CNTL1__WR_BURST_LIMIT_DATA__SHIFT 0x14 +#define DAGB1_SDP_ARB_CNTL1__RD_BURST_LIMIT_CYCL_MASK 0x0000007FL +#define DAGB1_SDP_ARB_CNTL1__WR_BURST_LIMIT_CYCL_MASK 0x00003F80L +#define DAGB1_SDP_ARB_CNTL1__RD_BURST_LIMIT_DATA_MASK 0x000FC000L +#define DAGB1_SDP_ARB_CNTL1__WR_BURST_LIMIT_DATA_MASK 0x03F00000L +//DAGB1_FATAL_ERROR_CLEAR +#define DAGB1_FATAL_ERROR_CLEAR__CLEAR__SHIFT 0x0 +#define DAGB1_FATAL_ERROR_CLEAR__CLEAR_MASK 0x00000001L +//DAGB1_FATAL_ERROR_STATUS0 +#define DAGB1_FATAL_ERROR_STATUS0__ADDR_HI__SHIFT 0x0 +#define DAGB1_FATAL_ERROR_STATUS0__PARITY_ERROR__SHIFT 0x1f +#define DAGB1_FATAL_ERROR_STATUS0__ADDR_HI_MASK 0x00000FFFL +#define DAGB1_FATAL_ERROR_STATUS0__PARITY_ERROR_MASK 0x80000000L +//DAGB1_FATAL_ERROR_STATUS1 +#define DAGB1_FATAL_ERROR_STATUS1__CID__SHIFT 0x0 +#define DAGB1_FATAL_ERROR_STATUS1__ADDR_LO__SHIFT 0x5 +#define DAGB1_FATAL_ERROR_STATUS1__CID_MASK 0x0000001FL +#define DAGB1_FATAL_ERROR_STATUS1__ADDR_LO_MASK 0xFFFFFFE0L +//DAGB1_FATAL_ERROR_STATUS2 +#define DAGB1_FATAL_ERROR_STATUS2__CLI_TAG__SHIFT 0x0 +#define DAGB1_FATAL_ERROR_STATUS2__SDP_TAG__SHIFT 0x10 +#define DAGB1_FATAL_ERROR_STATUS2__VFID__SHIFT 0x19 +#define DAGB1_FATAL_ERROR_STATUS2__VF__SHIFT 0x1e +#define DAGB1_FATAL_ERROR_STATUS2__CLI_TAG_MASK 0x0000FFFFL +#define DAGB1_FATAL_ERROR_STATUS2__SDP_TAG_MASK 0x01FF0000L +#define DAGB1_FATAL_ERROR_STATUS2__VFID_MASK 0x3E000000L +#define DAGB1_FATAL_ERROR_STATUS2__VF_MASK 0x40000000L +//DAGB1_FATAL_ERROR_STATUS3 +#define DAGB1_FATAL_ERROR_STATUS3__UNITID__SHIFT 0x0 +#define DAGB1_FATAL_ERROR_STATUS3__OP__SHIFT 0x6 +#define DAGB1_FATAL_ERROR_STATUS3__SECLEVEL__SHIFT 0xd +#define DAGB1_FATAL_ERROR_STATUS3__WRTMZ__SHIFT 0x11 +#define DAGB1_FATAL_ERROR_STATUS3__RDTMZ__SHIFT 0x12 +#define DAGB1_FATAL_ERROR_STATUS3__SNOOP__SHIFT 0x13 +#define DAGB1_FATAL_ERROR_STATUS3__INVAL__SHIFT 0x14 +#define DAGB1_FATAL_ERROR_STATUS3__NACK__SHIFT 0x15 +#define DAGB1_FATAL_ERROR_STATUS3__RO__SHIFT 0x17 +#define DAGB1_FATAL_ERROR_STATUS3__MEMLOG__SHIFT 0x18 +#define DAGB1_FATAL_ERROR_STATUS3__INT_FATAL__SHIFT 0x19 +#define DAGB1_FATAL_ERROR_STATUS3__EXT_FATAL__SHIFT 0x1a +#define DAGB1_FATAL_ERROR_STATUS3__UNITID_MASK 0x0000003FL +#define DAGB1_FATAL_ERROR_STATUS3__OP_MASK 0x00001FC0L +#define DAGB1_FATAL_ERROR_STATUS3__SECLEVEL_MASK 0x0001E000L +#define DAGB1_FATAL_ERROR_STATUS3__WRTMZ_MASK 0x00020000L +#define DAGB1_FATAL_ERROR_STATUS3__RDTMZ_MASK 0x00040000L +#define DAGB1_FATAL_ERROR_STATUS3__SNOOP_MASK 0x00080000L +#define DAGB1_FATAL_ERROR_STATUS3__INVAL_MASK 0x00100000L +#define DAGB1_FATAL_ERROR_STATUS3__NACK_MASK 0x00600000L +#define DAGB1_FATAL_ERROR_STATUS3__RO_MASK 0x00800000L +#define DAGB1_FATAL_ERROR_STATUS3__MEMLOG_MASK 0x01000000L +#define DAGB1_FATAL_ERROR_STATUS3__INT_FATAL_MASK 0x02000000L +#define DAGB1_FATAL_ERROR_STATUS3__EXT_FATAL_MASK 0x04000000L +//DAGB1_SDP_CGTT_CLK_CTRL +#define DAGB1_SDP_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 +#define DAGB1_SDP_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x5 +#define DAGB1_SDP_CGTT_CLK_CTRL__LS_ASSERT_HYSTERESIS__SHIFT 0xd +#define DAGB1_SDP_CGTT_CLK_CTRL__MIN_MGLS__SHIFT 0x1a +#define DAGB1_SDP_CGTT_CLK_CTRL__CGLS_DISABLE__SHIFT 0x1d +#define DAGB1_SDP_CGTT_CLK_CTRL__LS_DISABLE__SHIFT 0x1e +#define DAGB1_SDP_CGTT_CLK_CTRL__BUSY_OVERRIDE__SHIFT 0x1f +#define DAGB1_SDP_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000001FL +#define DAGB1_SDP_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00001FE0L +#define DAGB1_SDP_CGTT_CLK_CTRL__LS_ASSERT_HYSTERESIS_MASK 0x03FFE000L +#define DAGB1_SDP_CGTT_CLK_CTRL__MIN_MGLS_MASK 0x1C000000L +#define DAGB1_SDP_CGTT_CLK_CTRL__CGLS_DISABLE_MASK 0x20000000L +#define DAGB1_SDP_CGTT_CLK_CTRL__LS_DISABLE_MASK 0x40000000L +#define DAGB1_SDP_CGTT_CLK_CTRL__BUSY_OVERRIDE_MASK 0x80000000L +//DAGB1_SDP_LATENCY_SAMPLING +#define DAGB1_SDP_LATENCY_SAMPLING__SAMPLER0_DRAM__SHIFT 0x0 +#define DAGB1_SDP_LATENCY_SAMPLING__SAMPLER1_DRAM__SHIFT 0x1 +#define DAGB1_SDP_LATENCY_SAMPLING__SAMPLER0_GMI__SHIFT 0x2 +#define DAGB1_SDP_LATENCY_SAMPLING__SAMPLER1_GMI__SHIFT 0x3 +#define DAGB1_SDP_LATENCY_SAMPLING__SAMPLER0_IO__SHIFT 0x4 +#define DAGB1_SDP_LATENCY_SAMPLING__SAMPLER1_IO__SHIFT 0x5 +#define DAGB1_SDP_LATENCY_SAMPLING__SAMPLER0_READ__SHIFT 0x6 +#define DAGB1_SDP_LATENCY_SAMPLING__SAMPLER1_READ__SHIFT 0x7 +#define DAGB1_SDP_LATENCY_SAMPLING__SAMPLER0_WRITE__SHIFT 0x8 +#define DAGB1_SDP_LATENCY_SAMPLING__SAMPLER1_WRITE__SHIFT 0x9 +#define DAGB1_SDP_LATENCY_SAMPLING__SAMPLER0_ATOMIC_RET__SHIFT 0xa +#define DAGB1_SDP_LATENCY_SAMPLING__SAMPLER1_ATOMIC_RET__SHIFT 0xb +#define DAGB1_SDP_LATENCY_SAMPLING__SAMPLER0_ATOMIC_NORET__SHIFT 0xc +#define DAGB1_SDP_LATENCY_SAMPLING__SAMPLER1_ATOMIC_NORET__SHIFT 0xd +#define DAGB1_SDP_LATENCY_SAMPLING__SAMPLER0_VC__SHIFT 0xe +#define DAGB1_SDP_LATENCY_SAMPLING__SAMPLER1_VC__SHIFT 0x16 +#define DAGB1_SDP_LATENCY_SAMPLING__SAMPLER0_DRAM_MASK 0x00000001L +#define DAGB1_SDP_LATENCY_SAMPLING__SAMPLER1_DRAM_MASK 0x00000002L +#define DAGB1_SDP_LATENCY_SAMPLING__SAMPLER0_GMI_MASK 0x00000004L +#define DAGB1_SDP_LATENCY_SAMPLING__SAMPLER1_GMI_MASK 0x00000008L +#define DAGB1_SDP_LATENCY_SAMPLING__SAMPLER0_IO_MASK 0x00000010L +#define DAGB1_SDP_LATENCY_SAMPLING__SAMPLER1_IO_MASK 0x00000020L +#define DAGB1_SDP_LATENCY_SAMPLING__SAMPLER0_READ_MASK 0x00000040L +#define DAGB1_SDP_LATENCY_SAMPLING__SAMPLER1_READ_MASK 0x00000080L +#define DAGB1_SDP_LATENCY_SAMPLING__SAMPLER0_WRITE_MASK 0x00000100L +#define DAGB1_SDP_LATENCY_SAMPLING__SAMPLER1_WRITE_MASK 0x00000200L +#define DAGB1_SDP_LATENCY_SAMPLING__SAMPLER0_ATOMIC_RET_MASK 0x00000400L +#define DAGB1_SDP_LATENCY_SAMPLING__SAMPLER1_ATOMIC_RET_MASK 0x00000800L +#define DAGB1_SDP_LATENCY_SAMPLING__SAMPLER0_ATOMIC_NORET_MASK 0x00001000L +#define DAGB1_SDP_LATENCY_SAMPLING__SAMPLER1_ATOMIC_NORET_MASK 0x00002000L +#define DAGB1_SDP_LATENCY_SAMPLING__SAMPLER0_VC_MASK 0x003FC000L +#define DAGB1_SDP_LATENCY_SAMPLING__SAMPLER1_VC_MASK 0x3FC00000L +//DAGB1_WRCLI_GPU_SNOOP_OVERRIDE +#define DAGB1_WRCLI_GPU_SNOOP_OVERRIDE__ENABLE__SHIFT 0x0 +#define DAGB1_WRCLI_GPU_SNOOP_OVERRIDE__ENABLE_MASK 0x00FFFFFFL +//DAGB1_WRCLI_GPU_SNOOP_OVERRIDE_VALUE +#define DAGB1_WRCLI_GPU_SNOOP_OVERRIDE_VALUE__ENABLE__SHIFT 0x0 +#define DAGB1_WRCLI_GPU_SNOOP_OVERRIDE_VALUE__ENABLE_MASK 0x00FFFFFFL + + +// addressBlock: mmhub_pctldec +//PCTL_CTRL +#define PCTL_CTRL__PG_ENABLE__SHIFT 0x0 +#define PCTL_CTRL__ALLOW_DEEP_SLEEP_MODE__SHIFT 0x1 +#define PCTL_CTRL__RSMU_RDTIMER_ENABLE__SHIFT 0x4 +#define PCTL_CTRL__RSMU_RDTIMER_THRESHOLD__SHIFT 0x5 +#define PCTL_CTRL__STCTRL_RSMU_IDLE_THRESHOLD__SHIFT 0x7 +#define PCTL_CTRL__STCTRL_DAGB_IDLE_THRESHOLD__SHIFT 0xe +#define PCTL_CTRL__STCTRL_IGNORE_PROTECTION_FAULT__SHIFT 0x13 +#define PCTL_CTRL__UTCL2_LEGACY_MODE__SHIFT 0x14 +#define PCTL_CTRL__SDP_DISCONNECT_MODE__SHIFT 0x15 +#define PCTL_CTRL__STCTRL_ZSC_IDLE_THRESHOLD__SHIFT 0x16 +#define PCTL_CTRL__ZSC_TIMER_ENABLE__SHIFT 0x1b +#define PCTL_CTRL__Z9_PWRDOWN__SHIFT 0x1c +#define PCTL_CTRL__Z9_PWRUP__SHIFT 0x1d +#define PCTL_CTRL__REF_COUNTER_DISABLE__SHIFT 0x1e +#define PCTL_CTRL__WRACK_GUARD__SHIFT 0x1f +#define PCTL_CTRL__PG_ENABLE_MASK 0x00000001L +#define PCTL_CTRL__ALLOW_DEEP_SLEEP_MODE_MASK 0x0000000EL +#define PCTL_CTRL__RSMU_RDTIMER_ENABLE_MASK 0x00000010L +#define PCTL_CTRL__RSMU_RDTIMER_THRESHOLD_MASK 0x00000060L +#define PCTL_CTRL__STCTRL_RSMU_IDLE_THRESHOLD_MASK 0x00003F80L +#define PCTL_CTRL__STCTRL_DAGB_IDLE_THRESHOLD_MASK 0x0007C000L +#define PCTL_CTRL__STCTRL_IGNORE_PROTECTION_FAULT_MASK 0x00080000L +#define PCTL_CTRL__UTCL2_LEGACY_MODE_MASK 0x00100000L +#define PCTL_CTRL__SDP_DISCONNECT_MODE_MASK 0x00200000L +#define PCTL_CTRL__STCTRL_ZSC_IDLE_THRESHOLD_MASK 0x07C00000L +#define PCTL_CTRL__ZSC_TIMER_ENABLE_MASK 0x08000000L +#define PCTL_CTRL__Z9_PWRDOWN_MASK 0x10000000L +#define PCTL_CTRL__Z9_PWRUP_MASK 0x20000000L +#define PCTL_CTRL__REF_COUNTER_DISABLE_MASK 0x40000000L +#define PCTL_CTRL__WRACK_GUARD_MASK 0x80000000L +//PCTL_MMHUB_DEEPSLEEP_IB +#define PCTL_MMHUB_DEEPSLEEP_IB__DS0__SHIFT 0x0 +#define PCTL_MMHUB_DEEPSLEEP_IB__DS1__SHIFT 0x1 +#define PCTL_MMHUB_DEEPSLEEP_IB__DS2__SHIFT 0x2 +#define PCTL_MMHUB_DEEPSLEEP_IB__DS3__SHIFT 0x3 +#define PCTL_MMHUB_DEEPSLEEP_IB__DS4__SHIFT 0x4 +#define PCTL_MMHUB_DEEPSLEEP_IB__DS5__SHIFT 0x5 +#define PCTL_MMHUB_DEEPSLEEP_IB__DS6__SHIFT 0x6 +#define PCTL_MMHUB_DEEPSLEEP_IB__DS7__SHIFT 0x7 +#define PCTL_MMHUB_DEEPSLEEP_IB__DS8__SHIFT 0x8 +#define PCTL_MMHUB_DEEPSLEEP_IB__DS9__SHIFT 0x9 +#define PCTL_MMHUB_DEEPSLEEP_IB__DS10__SHIFT 0xa +#define PCTL_MMHUB_DEEPSLEEP_IB__DS11__SHIFT 0xb +#define PCTL_MMHUB_DEEPSLEEP_IB__DS12__SHIFT 0xc +#define PCTL_MMHUB_DEEPSLEEP_IB__DS13__SHIFT 0xd +#define PCTL_MMHUB_DEEPSLEEP_IB__DS14__SHIFT 0xe +#define PCTL_MMHUB_DEEPSLEEP_IB__DS15__SHIFT 0xf +#define PCTL_MMHUB_DEEPSLEEP_IB__DS16__SHIFT 0x10 +#define PCTL_MMHUB_DEEPSLEEP_IB__SETCLEAR__SHIFT 0x1f +#define PCTL_MMHUB_DEEPSLEEP_IB__DS0_MASK 0x00000001L +#define PCTL_MMHUB_DEEPSLEEP_IB__DS1_MASK 0x00000002L +#define PCTL_MMHUB_DEEPSLEEP_IB__DS2_MASK 0x00000004L +#define PCTL_MMHUB_DEEPSLEEP_IB__DS3_MASK 0x00000008L +#define PCTL_MMHUB_DEEPSLEEP_IB__DS4_MASK 0x00000010L +#define PCTL_MMHUB_DEEPSLEEP_IB__DS5_MASK 0x00000020L +#define PCTL_MMHUB_DEEPSLEEP_IB__DS6_MASK 0x00000040L +#define PCTL_MMHUB_DEEPSLEEP_IB__DS7_MASK 0x00000080L +#define PCTL_MMHUB_DEEPSLEEP_IB__DS8_MASK 0x00000100L +#define PCTL_MMHUB_DEEPSLEEP_IB__DS9_MASK 0x00000200L +#define PCTL_MMHUB_DEEPSLEEP_IB__DS10_MASK 0x00000400L +#define PCTL_MMHUB_DEEPSLEEP_IB__DS11_MASK 0x00000800L +#define PCTL_MMHUB_DEEPSLEEP_IB__DS12_MASK 0x00001000L +#define PCTL_MMHUB_DEEPSLEEP_IB__DS13_MASK 0x00002000L +#define PCTL_MMHUB_DEEPSLEEP_IB__DS14_MASK 0x00004000L +#define PCTL_MMHUB_DEEPSLEEP_IB__DS15_MASK 0x00008000L +#define PCTL_MMHUB_DEEPSLEEP_IB__DS16_MASK 0x00010000L +#define PCTL_MMHUB_DEEPSLEEP_IB__SETCLEAR_MASK 0x80000000L +//PCTL_MMHUB_DEEPSLEEP_OVERRIDE +#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS0__SHIFT 0x0 +#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS1__SHIFT 0x1 +#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS2__SHIFT 0x2 +#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS3__SHIFT 0x3 +#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS4__SHIFT 0x4 +#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS5__SHIFT 0x5 +#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS6__SHIFT 0x6 +#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS7__SHIFT 0x7 +#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS8__SHIFT 0x8 +#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS9__SHIFT 0x9 +#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS10__SHIFT 0xa +#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS11__SHIFT 0xb +#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS12__SHIFT 0xc +#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS13__SHIFT 0xd +#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS14__SHIFT 0xe +#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS15__SHIFT 0xf +#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS16__SHIFT 0x10 +#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS_ATHUB__SHIFT 0x11 +#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS0_MASK 0x00000001L +#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS1_MASK 0x00000002L +#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS2_MASK 0x00000004L +#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS3_MASK 0x00000008L +#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS4_MASK 0x00000010L +#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS5_MASK 0x00000020L +#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS6_MASK 0x00000040L +#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS7_MASK 0x00000080L +#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS8_MASK 0x00000100L +#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS9_MASK 0x00000200L +#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS10_MASK 0x00000400L +#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS11_MASK 0x00000800L +#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS12_MASK 0x00001000L +#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS13_MASK 0x00002000L +#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS14_MASK 0x00004000L +#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS15_MASK 0x00008000L +#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS16_MASK 0x00010000L +#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS_ATHUB_MASK 0x00020000L +//PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB +#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS0__SHIFT 0x0 +#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS1__SHIFT 0x1 +#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS2__SHIFT 0x2 +#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS3__SHIFT 0x3 +#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS4__SHIFT 0x4 +#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS5__SHIFT 0x5 +#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS6__SHIFT 0x6 +#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS7__SHIFT 0x7 +#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS8__SHIFT 0x8 +#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS9__SHIFT 0x9 +#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS10__SHIFT 0xa +#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS11__SHIFT 0xb +#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS12__SHIFT 0xc +#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS13__SHIFT 0xd +#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS14__SHIFT 0xe +#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS15__SHIFT 0xf +#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS16__SHIFT 0x10 +#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS0_MASK 0x00000001L +#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS1_MASK 0x00000002L +#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS2_MASK 0x00000004L +#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS3_MASK 0x00000008L +#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS4_MASK 0x00000010L +#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS5_MASK 0x00000020L +#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS6_MASK 0x00000040L +#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS7_MASK 0x00000080L +#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS8_MASK 0x00000100L +#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS9_MASK 0x00000200L +#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS10_MASK 0x00000400L +#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS11_MASK 0x00000800L +#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS12_MASK 0x00001000L +#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS13_MASK 0x00002000L +#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS14_MASK 0x00004000L +#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS15_MASK 0x00008000L +#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS16_MASK 0x00010000L +//PCTL_PG_IGNORE_DEEPSLEEP +#define PCTL_PG_IGNORE_DEEPSLEEP__DS0__SHIFT 0x0 +#define PCTL_PG_IGNORE_DEEPSLEEP__DS1__SHIFT 0x1 +#define PCTL_PG_IGNORE_DEEPSLEEP__DS2__SHIFT 0x2 +#define PCTL_PG_IGNORE_DEEPSLEEP__DS3__SHIFT 0x3 +#define PCTL_PG_IGNORE_DEEPSLEEP__DS4__SHIFT 0x4 +#define PCTL_PG_IGNORE_DEEPSLEEP__DS5__SHIFT 0x5 +#define PCTL_PG_IGNORE_DEEPSLEEP__DS6__SHIFT 0x6 +#define PCTL_PG_IGNORE_DEEPSLEEP__DS7__SHIFT 0x7 +#define PCTL_PG_IGNORE_DEEPSLEEP__DS8__SHIFT 0x8 +#define PCTL_PG_IGNORE_DEEPSLEEP__DS9__SHIFT 0x9 +#define PCTL_PG_IGNORE_DEEPSLEEP__DS10__SHIFT 0xa +#define PCTL_PG_IGNORE_DEEPSLEEP__DS11__SHIFT 0xb +#define PCTL_PG_IGNORE_DEEPSLEEP__DS12__SHIFT 0xc +#define PCTL_PG_IGNORE_DEEPSLEEP__DS13__SHIFT 0xd +#define PCTL_PG_IGNORE_DEEPSLEEP__DS14__SHIFT 0xe +#define PCTL_PG_IGNORE_DEEPSLEEP__DS15__SHIFT 0xf +#define PCTL_PG_IGNORE_DEEPSLEEP__DS16__SHIFT 0x10 +#define PCTL_PG_IGNORE_DEEPSLEEP__DS_ATHUB__SHIFT 0x11 +#define PCTL_PG_IGNORE_DEEPSLEEP__ALLIPS__SHIFT 0x12 +#define PCTL_PG_IGNORE_DEEPSLEEP__DS0_MASK 0x00000001L +#define PCTL_PG_IGNORE_DEEPSLEEP__DS1_MASK 0x00000002L +#define PCTL_PG_IGNORE_DEEPSLEEP__DS2_MASK 0x00000004L +#define PCTL_PG_IGNORE_DEEPSLEEP__DS3_MASK 0x00000008L +#define PCTL_PG_IGNORE_DEEPSLEEP__DS4_MASK 0x00000010L +#define PCTL_PG_IGNORE_DEEPSLEEP__DS5_MASK 0x00000020L +#define PCTL_PG_IGNORE_DEEPSLEEP__DS6_MASK 0x00000040L +#define PCTL_PG_IGNORE_DEEPSLEEP__DS7_MASK 0x00000080L +#define PCTL_PG_IGNORE_DEEPSLEEP__DS8_MASK 0x00000100L +#define PCTL_PG_IGNORE_DEEPSLEEP__DS9_MASK 0x00000200L +#define PCTL_PG_IGNORE_DEEPSLEEP__DS10_MASK 0x00000400L +#define PCTL_PG_IGNORE_DEEPSLEEP__DS11_MASK 0x00000800L +#define PCTL_PG_IGNORE_DEEPSLEEP__DS12_MASK 0x00001000L +#define PCTL_PG_IGNORE_DEEPSLEEP__DS13_MASK 0x00002000L +#define PCTL_PG_IGNORE_DEEPSLEEP__DS14_MASK 0x00004000L +#define PCTL_PG_IGNORE_DEEPSLEEP__DS15_MASK 0x00008000L +#define PCTL_PG_IGNORE_DEEPSLEEP__DS16_MASK 0x00010000L +#define PCTL_PG_IGNORE_DEEPSLEEP__DS_ATHUB_MASK 0x00020000L +#define PCTL_PG_IGNORE_DEEPSLEEP__ALLIPS_MASK 0x00040000L +//PCTL_PG_IGNORE_DEEPSLEEP_IB +#define PCTL_PG_IGNORE_DEEPSLEEP_IB__DS0__SHIFT 0x0 +#define PCTL_PG_IGNORE_DEEPSLEEP_IB__DS1__SHIFT 0x1 +#define PCTL_PG_IGNORE_DEEPSLEEP_IB__DS2__SHIFT 0x2 +#define PCTL_PG_IGNORE_DEEPSLEEP_IB__DS3__SHIFT 0x3 +#define PCTL_PG_IGNORE_DEEPSLEEP_IB__DS4__SHIFT 0x4 +#define PCTL_PG_IGNORE_DEEPSLEEP_IB__DS5__SHIFT 0x5 +#define PCTL_PG_IGNORE_DEEPSLEEP_IB__DS6__SHIFT 0x6 +#define PCTL_PG_IGNORE_DEEPSLEEP_IB__DS7__SHIFT 0x7 +#define PCTL_PG_IGNORE_DEEPSLEEP_IB__DS8__SHIFT 0x8 +#define PCTL_PG_IGNORE_DEEPSLEEP_IB__DS9__SHIFT 0x9 +#define PCTL_PG_IGNORE_DEEPSLEEP_IB__DS10__SHIFT 0xa +#define PCTL_PG_IGNORE_DEEPSLEEP_IB__DS11__SHIFT 0xb +#define PCTL_PG_IGNORE_DEEPSLEEP_IB__DS12__SHIFT 0xc +#define PCTL_PG_IGNORE_DEEPSLEEP_IB__DS13__SHIFT 0xd +#define PCTL_PG_IGNORE_DEEPSLEEP_IB__DS14__SHIFT 0xe +#define PCTL_PG_IGNORE_DEEPSLEEP_IB__DS15__SHIFT 0xf +#define PCTL_PG_IGNORE_DEEPSLEEP_IB__DS16__SHIFT 0x10 +#define PCTL_PG_IGNORE_DEEPSLEEP_IB__ALLIPS__SHIFT 0x11 +#define PCTL_PG_IGNORE_DEEPSLEEP_IB__DS0_MASK 0x00000001L +#define PCTL_PG_IGNORE_DEEPSLEEP_IB__DS1_MASK 0x00000002L +#define PCTL_PG_IGNORE_DEEPSLEEP_IB__DS2_MASK 0x00000004L +#define PCTL_PG_IGNORE_DEEPSLEEP_IB__DS3_MASK 0x00000008L +#define PCTL_PG_IGNORE_DEEPSLEEP_IB__DS4_MASK 0x00000010L +#define PCTL_PG_IGNORE_DEEPSLEEP_IB__DS5_MASK 0x00000020L +#define PCTL_PG_IGNORE_DEEPSLEEP_IB__DS6_MASK 0x00000040L +#define PCTL_PG_IGNORE_DEEPSLEEP_IB__DS7_MASK 0x00000080L +#define PCTL_PG_IGNORE_DEEPSLEEP_IB__DS8_MASK 0x00000100L +#define PCTL_PG_IGNORE_DEEPSLEEP_IB__DS9_MASK 0x00000200L +#define PCTL_PG_IGNORE_DEEPSLEEP_IB__DS10_MASK 0x00000400L +#define PCTL_PG_IGNORE_DEEPSLEEP_IB__DS11_MASK 0x00000800L +#define PCTL_PG_IGNORE_DEEPSLEEP_IB__DS12_MASK 0x00001000L +#define PCTL_PG_IGNORE_DEEPSLEEP_IB__DS13_MASK 0x00002000L +#define PCTL_PG_IGNORE_DEEPSLEEP_IB__DS14_MASK 0x00004000L +#define PCTL_PG_IGNORE_DEEPSLEEP_IB__DS15_MASK 0x00008000L +#define PCTL_PG_IGNORE_DEEPSLEEP_IB__DS16_MASK 0x00010000L +#define PCTL_PG_IGNORE_DEEPSLEEP_IB__ALLIPS_MASK 0x00020000L +//PCTL_UTCL2_MISC +#define PCTL_UTCL2_MISC__RENG_EXECUTE_NONSECURE_START_PTR__SHIFT 0x0 +#define PCTL_UTCL2_MISC__CRITICAL_REGS_LOCK__SHIFT 0xb +#define PCTL_UTCL2_MISC__TILE_IDLE_THRESHOLD__SHIFT 0xc +#define PCTL_UTCL2_MISC__RENG_MEM_LS_ENABLE__SHIFT 0xf +#define PCTL_UTCL2_MISC__STCTRL_FORCE_PGFSM_CMD_DONE__SHIFT 0x10 +#define PCTL_UTCL2_MISC__RENG_EXECUTE_ON_REG_UPDATE__SHIFT 0x11 +#define PCTL_UTCL2_MISC__RD_TIMER_ENABLE__SHIFT 0x12 +#define PCTL_UTCL2_MISC__RENG_MEM_DS_ENABLE__SHIFT 0x13 +#define PCTL_UTCL2_MISC__RENG_MEM_LS_TIMER__SHIFT 0x14 +#define PCTL_UTCL2_MISC__RENG_MEM_SLEEP_TIMER__SHIFT 0x1a +#define PCTL_UTCL2_MISC__RENG_EXECUTE_NONSECURE_START_PTR_MASK 0x000007FFL +#define PCTL_UTCL2_MISC__CRITICAL_REGS_LOCK_MASK 0x00000800L +#define PCTL_UTCL2_MISC__TILE_IDLE_THRESHOLD_MASK 0x00007000L +#define PCTL_UTCL2_MISC__RENG_MEM_LS_ENABLE_MASK 0x00008000L +#define PCTL_UTCL2_MISC__STCTRL_FORCE_PGFSM_CMD_DONE_MASK 0x00010000L +#define PCTL_UTCL2_MISC__RENG_EXECUTE_ON_REG_UPDATE_MASK 0x00020000L +#define PCTL_UTCL2_MISC__RD_TIMER_ENABLE_MASK 0x00040000L +#define PCTL_UTCL2_MISC__RENG_MEM_DS_ENABLE_MASK 0x00080000L +#define PCTL_UTCL2_MISC__RENG_MEM_LS_TIMER_MASK 0x03F00000L +#define PCTL_UTCL2_MISC__RENG_MEM_SLEEP_TIMER_MASK 0x3C000000L +//PCTL_SLICE0_CFG_DAGB_WRBUSY +#define PCTL_SLICE0_CFG_DAGB_WRBUSY__DB_LNCFG__SHIFT 0x0 +#define PCTL_SLICE0_CFG_DAGB_WRBUSY__DB_LNCFG_MASK 0xFFFFFFFFL +//PCTL_SLICE0_CFG_DAGB_RDBUSY +#define PCTL_SLICE0_CFG_DAGB_RDBUSY__DB_LNCFG__SHIFT 0x0 +#define PCTL_SLICE0_CFG_DAGB_RDBUSY__DB_LNCFG_MASK 0xFFFFFFFFL +//PCTL_SLICE0_CFG_DS_ALLOW +#define PCTL_SLICE0_CFG_DS_ALLOW__DS0__SHIFT 0x0 +#define PCTL_SLICE0_CFG_DS_ALLOW__DS1__SHIFT 0x1 +#define PCTL_SLICE0_CFG_DS_ALLOW__DS2__SHIFT 0x2 +#define PCTL_SLICE0_CFG_DS_ALLOW__DS3__SHIFT 0x3 +#define PCTL_SLICE0_CFG_DS_ALLOW__DS4__SHIFT 0x4 +#define PCTL_SLICE0_CFG_DS_ALLOW__DS5__SHIFT 0x5 +#define PCTL_SLICE0_CFG_DS_ALLOW__DS6__SHIFT 0x6 +#define PCTL_SLICE0_CFG_DS_ALLOW__DS7__SHIFT 0x7 +#define PCTL_SLICE0_CFG_DS_ALLOW__DS8__SHIFT 0x8 +#define PCTL_SLICE0_CFG_DS_ALLOW__DS9__SHIFT 0x9 +#define PCTL_SLICE0_CFG_DS_ALLOW__DS10__SHIFT 0xa +#define PCTL_SLICE0_CFG_DS_ALLOW__DS11__SHIFT 0xb +#define PCTL_SLICE0_CFG_DS_ALLOW__DS12__SHIFT 0xc +#define PCTL_SLICE0_CFG_DS_ALLOW__DS13__SHIFT 0xd +#define PCTL_SLICE0_CFG_DS_ALLOW__DS14__SHIFT 0xe +#define PCTL_SLICE0_CFG_DS_ALLOW__DS15__SHIFT 0xf +#define PCTL_SLICE0_CFG_DS_ALLOW__DS16__SHIFT 0x10 +#define PCTL_SLICE0_CFG_DS_ALLOW__DS0_MASK 0x00000001L +#define PCTL_SLICE0_CFG_DS_ALLOW__DS1_MASK 0x00000002L +#define PCTL_SLICE0_CFG_DS_ALLOW__DS2_MASK 0x00000004L +#define PCTL_SLICE0_CFG_DS_ALLOW__DS3_MASK 0x00000008L +#define PCTL_SLICE0_CFG_DS_ALLOW__DS4_MASK 0x00000010L +#define PCTL_SLICE0_CFG_DS_ALLOW__DS5_MASK 0x00000020L +#define PCTL_SLICE0_CFG_DS_ALLOW__DS6_MASK 0x00000040L +#define PCTL_SLICE0_CFG_DS_ALLOW__DS7_MASK 0x00000080L +#define PCTL_SLICE0_CFG_DS_ALLOW__DS8_MASK 0x00000100L +#define PCTL_SLICE0_CFG_DS_ALLOW__DS9_MASK 0x00000200L +#define PCTL_SLICE0_CFG_DS_ALLOW__DS10_MASK 0x00000400L +#define PCTL_SLICE0_CFG_DS_ALLOW__DS11_MASK 0x00000800L +#define PCTL_SLICE0_CFG_DS_ALLOW__DS12_MASK 0x00001000L +#define PCTL_SLICE0_CFG_DS_ALLOW__DS13_MASK 0x00002000L +#define PCTL_SLICE0_CFG_DS_ALLOW__DS14_MASK 0x00004000L +#define PCTL_SLICE0_CFG_DS_ALLOW__DS15_MASK 0x00008000L +#define PCTL_SLICE0_CFG_DS_ALLOW__DS16_MASK 0x00010000L +//PCTL_SLICE0_CFG_DS_ALLOW_IB +#define PCTL_SLICE0_CFG_DS_ALLOW_IB__DS0__SHIFT 0x0 +#define PCTL_SLICE0_CFG_DS_ALLOW_IB__DS1__SHIFT 0x1 +#define PCTL_SLICE0_CFG_DS_ALLOW_IB__DS2__SHIFT 0x2 +#define PCTL_SLICE0_CFG_DS_ALLOW_IB__DS3__SHIFT 0x3 +#define PCTL_SLICE0_CFG_DS_ALLOW_IB__DS4__SHIFT 0x4 +#define PCTL_SLICE0_CFG_DS_ALLOW_IB__DS5__SHIFT 0x5 +#define PCTL_SLICE0_CFG_DS_ALLOW_IB__DS6__SHIFT 0x6 +#define PCTL_SLICE0_CFG_DS_ALLOW_IB__DS7__SHIFT 0x7 +#define PCTL_SLICE0_CFG_DS_ALLOW_IB__DS8__SHIFT 0x8 +#define PCTL_SLICE0_CFG_DS_ALLOW_IB__DS9__SHIFT 0x9 +#define PCTL_SLICE0_CFG_DS_ALLOW_IB__DS10__SHIFT 0xa +#define PCTL_SLICE0_CFG_DS_ALLOW_IB__DS11__SHIFT 0xb +#define PCTL_SLICE0_CFG_DS_ALLOW_IB__DS12__SHIFT 0xc +#define PCTL_SLICE0_CFG_DS_ALLOW_IB__DS13__SHIFT 0xd +#define PCTL_SLICE0_CFG_DS_ALLOW_IB__DS14__SHIFT 0xe +#define PCTL_SLICE0_CFG_DS_ALLOW_IB__DS15__SHIFT 0xf +#define PCTL_SLICE0_CFG_DS_ALLOW_IB__DS16__SHIFT 0x10 +#define PCTL_SLICE0_CFG_DS_ALLOW_IB__DS0_MASK 0x00000001L +#define PCTL_SLICE0_CFG_DS_ALLOW_IB__DS1_MASK 0x00000002L +#define PCTL_SLICE0_CFG_DS_ALLOW_IB__DS2_MASK 0x00000004L +#define PCTL_SLICE0_CFG_DS_ALLOW_IB__DS3_MASK 0x00000008L +#define PCTL_SLICE0_CFG_DS_ALLOW_IB__DS4_MASK 0x00000010L +#define PCTL_SLICE0_CFG_DS_ALLOW_IB__DS5_MASK 0x00000020L +#define PCTL_SLICE0_CFG_DS_ALLOW_IB__DS6_MASK 0x00000040L +#define PCTL_SLICE0_CFG_DS_ALLOW_IB__DS7_MASK 0x00000080L +#define PCTL_SLICE0_CFG_DS_ALLOW_IB__DS8_MASK 0x00000100L +#define PCTL_SLICE0_CFG_DS_ALLOW_IB__DS9_MASK 0x00000200L +#define PCTL_SLICE0_CFG_DS_ALLOW_IB__DS10_MASK 0x00000400L +#define PCTL_SLICE0_CFG_DS_ALLOW_IB__DS11_MASK 0x00000800L +#define PCTL_SLICE0_CFG_DS_ALLOW_IB__DS12_MASK 0x00001000L +#define PCTL_SLICE0_CFG_DS_ALLOW_IB__DS13_MASK 0x00002000L +#define PCTL_SLICE0_CFG_DS_ALLOW_IB__DS14_MASK 0x00004000L +#define PCTL_SLICE0_CFG_DS_ALLOW_IB__DS15_MASK 0x00008000L +#define PCTL_SLICE0_CFG_DS_ALLOW_IB__DS16_MASK 0x00010000L +//PCTL_SLICE0_MISC +#define PCTL_SLICE0_MISC__RENG_EXECUTE_NONSECURE_START_PTR__SHIFT 0x0 +#define PCTL_SLICE0_MISC__CRITICAL_REGS_LOCK__SHIFT 0xa +#define PCTL_SLICE0_MISC__TILE_IDLE_THRESHOLD__SHIFT 0xb +#define PCTL_SLICE0_MISC__RENG_MEM_LS_ENABLE__SHIFT 0xe +#define PCTL_SLICE0_MISC__STCTRL_FORCE_PGFSM_CMD_DONE__SHIFT 0xf +#define PCTL_SLICE0_MISC__DEEPSLEEP_DISCSDP__SHIFT 0x10 +#define PCTL_SLICE0_MISC__RENG_EXECUTE_ON_REG_UPDATE__SHIFT 0x11 +#define PCTL_SLICE0_MISC__RD_TIMER_ENABLE__SHIFT 0x12 +#define PCTL_SLICE0_MISC__RENG_MEM_DS_ENABLE__SHIFT 0x13 +#define PCTL_SLICE0_MISC__RENG_MEM_LS_TIMER__SHIFT 0x14 +#define PCTL_SLICE0_MISC__RENG_MEM_SLEEP_TIMER__SHIFT 0x1a +#define PCTL_SLICE0_MISC__OVR_EA_SDP0_PARTACK__SHIFT 0x1e +#define PCTL_SLICE0_MISC__OVR_EA_SDP0_FULLACK__SHIFT 0x1f +#define PCTL_SLICE0_MISC__RENG_EXECUTE_NONSECURE_START_PTR_MASK 0x000003FFL +#define PCTL_SLICE0_MISC__CRITICAL_REGS_LOCK_MASK 0x00000400L +#define PCTL_SLICE0_MISC__TILE_IDLE_THRESHOLD_MASK 0x00003800L +#define PCTL_SLICE0_MISC__RENG_MEM_LS_ENABLE_MASK 0x00004000L +#define PCTL_SLICE0_MISC__STCTRL_FORCE_PGFSM_CMD_DONE_MASK 0x00008000L +#define PCTL_SLICE0_MISC__DEEPSLEEP_DISCSDP_MASK 0x00010000L +#define PCTL_SLICE0_MISC__RENG_EXECUTE_ON_REG_UPDATE_MASK 0x00020000L +#define PCTL_SLICE0_MISC__RD_TIMER_ENABLE_MASK 0x00040000L +#define PCTL_SLICE0_MISC__RENG_MEM_DS_ENABLE_MASK 0x00080000L +#define PCTL_SLICE0_MISC__RENG_MEM_LS_TIMER_MASK 0x03F00000L +#define PCTL_SLICE0_MISC__RENG_MEM_SLEEP_TIMER_MASK 0x3C000000L +#define PCTL_SLICE0_MISC__OVR_EA_SDP0_PARTACK_MASK 0x40000000L +#define PCTL_SLICE0_MISC__OVR_EA_SDP0_FULLACK_MASK 0x80000000L +//PCTL_SLICE1_CFG_DAGB_WRBUSY +#define PCTL_SLICE1_CFG_DAGB_WRBUSY__DB_LNCFG__SHIFT 0x0 +#define PCTL_SLICE1_CFG_DAGB_WRBUSY__DB_LNCFG_MASK 0xFFFFFFFFL +//PCTL_SLICE1_CFG_DAGB_RDBUSY +#define PCTL_SLICE1_CFG_DAGB_RDBUSY__DB_LNCFG__SHIFT 0x0 +#define PCTL_SLICE1_CFG_DAGB_RDBUSY__DB_LNCFG_MASK 0xFFFFFFFFL +//PCTL_SLICE1_CFG_DS_ALLOW +#define PCTL_SLICE1_CFG_DS_ALLOW__DS0__SHIFT 0x0 +#define PCTL_SLICE1_CFG_DS_ALLOW__DS1__SHIFT 0x1 +#define PCTL_SLICE1_CFG_DS_ALLOW__DS2__SHIFT 0x2 +#define PCTL_SLICE1_CFG_DS_ALLOW__DS3__SHIFT 0x3 +#define PCTL_SLICE1_CFG_DS_ALLOW__DS4__SHIFT 0x4 +#define PCTL_SLICE1_CFG_DS_ALLOW__DS5__SHIFT 0x5 +#define PCTL_SLICE1_CFG_DS_ALLOW__DS6__SHIFT 0x6 +#define PCTL_SLICE1_CFG_DS_ALLOW__DS7__SHIFT 0x7 +#define PCTL_SLICE1_CFG_DS_ALLOW__DS8__SHIFT 0x8 +#define PCTL_SLICE1_CFG_DS_ALLOW__DS9__SHIFT 0x9 +#define PCTL_SLICE1_CFG_DS_ALLOW__DS10__SHIFT 0xa +#define PCTL_SLICE1_CFG_DS_ALLOW__DS11__SHIFT 0xb +#define PCTL_SLICE1_CFG_DS_ALLOW__DS12__SHIFT 0xc +#define PCTL_SLICE1_CFG_DS_ALLOW__DS13__SHIFT 0xd +#define PCTL_SLICE1_CFG_DS_ALLOW__DS14__SHIFT 0xe +#define PCTL_SLICE1_CFG_DS_ALLOW__DS15__SHIFT 0xf +#define PCTL_SLICE1_CFG_DS_ALLOW__DS16__SHIFT 0x10 +#define PCTL_SLICE1_CFG_DS_ALLOW__DS0_MASK 0x00000001L +#define PCTL_SLICE1_CFG_DS_ALLOW__DS1_MASK 0x00000002L +#define PCTL_SLICE1_CFG_DS_ALLOW__DS2_MASK 0x00000004L +#define PCTL_SLICE1_CFG_DS_ALLOW__DS3_MASK 0x00000008L +#define PCTL_SLICE1_CFG_DS_ALLOW__DS4_MASK 0x00000010L +#define PCTL_SLICE1_CFG_DS_ALLOW__DS5_MASK 0x00000020L +#define PCTL_SLICE1_CFG_DS_ALLOW__DS6_MASK 0x00000040L +#define PCTL_SLICE1_CFG_DS_ALLOW__DS7_MASK 0x00000080L +#define PCTL_SLICE1_CFG_DS_ALLOW__DS8_MASK 0x00000100L +#define PCTL_SLICE1_CFG_DS_ALLOW__DS9_MASK 0x00000200L +#define PCTL_SLICE1_CFG_DS_ALLOW__DS10_MASK 0x00000400L +#define PCTL_SLICE1_CFG_DS_ALLOW__DS11_MASK 0x00000800L +#define PCTL_SLICE1_CFG_DS_ALLOW__DS12_MASK 0x00001000L +#define PCTL_SLICE1_CFG_DS_ALLOW__DS13_MASK 0x00002000L +#define PCTL_SLICE1_CFG_DS_ALLOW__DS14_MASK 0x00004000L +#define PCTL_SLICE1_CFG_DS_ALLOW__DS15_MASK 0x00008000L +#define PCTL_SLICE1_CFG_DS_ALLOW__DS16_MASK 0x00010000L +//PCTL_SLICE1_CFG_DS_ALLOW_IB +#define PCTL_SLICE1_CFG_DS_ALLOW_IB__DS0__SHIFT 0x0 +#define PCTL_SLICE1_CFG_DS_ALLOW_IB__DS1__SHIFT 0x1 +#define PCTL_SLICE1_CFG_DS_ALLOW_IB__DS2__SHIFT 0x2 +#define PCTL_SLICE1_CFG_DS_ALLOW_IB__DS3__SHIFT 0x3 +#define PCTL_SLICE1_CFG_DS_ALLOW_IB__DS4__SHIFT 0x4 +#define PCTL_SLICE1_CFG_DS_ALLOW_IB__DS5__SHIFT 0x5 +#define PCTL_SLICE1_CFG_DS_ALLOW_IB__DS6__SHIFT 0x6 +#define PCTL_SLICE1_CFG_DS_ALLOW_IB__DS7__SHIFT 0x7 +#define PCTL_SLICE1_CFG_DS_ALLOW_IB__DS8__SHIFT 0x8 +#define PCTL_SLICE1_CFG_DS_ALLOW_IB__DS9__SHIFT 0x9 +#define PCTL_SLICE1_CFG_DS_ALLOW_IB__DS10__SHIFT 0xa +#define PCTL_SLICE1_CFG_DS_ALLOW_IB__DS11__SHIFT 0xb +#define PCTL_SLICE1_CFG_DS_ALLOW_IB__DS12__SHIFT 0xc +#define PCTL_SLICE1_CFG_DS_ALLOW_IB__DS13__SHIFT 0xd +#define PCTL_SLICE1_CFG_DS_ALLOW_IB__DS14__SHIFT 0xe +#define PCTL_SLICE1_CFG_DS_ALLOW_IB__DS15__SHIFT 0xf +#define PCTL_SLICE1_CFG_DS_ALLOW_IB__DS16__SHIFT 0x10 +#define PCTL_SLICE1_CFG_DS_ALLOW_IB__DS0_MASK 0x00000001L +#define PCTL_SLICE1_CFG_DS_ALLOW_IB__DS1_MASK 0x00000002L +#define PCTL_SLICE1_CFG_DS_ALLOW_IB__DS2_MASK 0x00000004L +#define PCTL_SLICE1_CFG_DS_ALLOW_IB__DS3_MASK 0x00000008L +#define PCTL_SLICE1_CFG_DS_ALLOW_IB__DS4_MASK 0x00000010L +#define PCTL_SLICE1_CFG_DS_ALLOW_IB__DS5_MASK 0x00000020L +#define PCTL_SLICE1_CFG_DS_ALLOW_IB__DS6_MASK 0x00000040L +#define PCTL_SLICE1_CFG_DS_ALLOW_IB__DS7_MASK 0x00000080L +#define PCTL_SLICE1_CFG_DS_ALLOW_IB__DS8_MASK 0x00000100L +#define PCTL_SLICE1_CFG_DS_ALLOW_IB__DS9_MASK 0x00000200L +#define PCTL_SLICE1_CFG_DS_ALLOW_IB__DS10_MASK 0x00000400L +#define PCTL_SLICE1_CFG_DS_ALLOW_IB__DS11_MASK 0x00000800L +#define PCTL_SLICE1_CFG_DS_ALLOW_IB__DS12_MASK 0x00001000L +#define PCTL_SLICE1_CFG_DS_ALLOW_IB__DS13_MASK 0x00002000L +#define PCTL_SLICE1_CFG_DS_ALLOW_IB__DS14_MASK 0x00004000L +#define PCTL_SLICE1_CFG_DS_ALLOW_IB__DS15_MASK 0x00008000L +#define PCTL_SLICE1_CFG_DS_ALLOW_IB__DS16_MASK 0x00010000L +//PCTL_SLICE1_MISC +#define PCTL_SLICE1_MISC__RENG_EXECUTE_NONSECURE_START_PTR__SHIFT 0x0 +#define PCTL_SLICE1_MISC__CRITICAL_REGS_LOCK__SHIFT 0xa +#define PCTL_SLICE1_MISC__TILE_IDLE_THRESHOLD__SHIFT 0xb +#define PCTL_SLICE1_MISC__RENG_MEM_LS_ENABLE__SHIFT 0xe +#define PCTL_SLICE1_MISC__STCTRL_FORCE_PGFSM_CMD_DONE__SHIFT 0xf +#define PCTL_SLICE1_MISC__DEEPSLEEP_DISCSDP__SHIFT 0x10 +#define PCTL_SLICE1_MISC__RENG_EXECUTE_ON_REG_UPDATE__SHIFT 0x11 +#define PCTL_SLICE1_MISC__RD_TIMER_ENABLE__SHIFT 0x12 +#define PCTL_SLICE1_MISC__RENG_MEM_DS_ENABLE__SHIFT 0x13 +#define PCTL_SLICE1_MISC__RENG_MEM_LS_TIMER__SHIFT 0x14 +#define PCTL_SLICE1_MISC__RENG_MEM_SLEEP_TIMER__SHIFT 0x1a +#define PCTL_SLICE1_MISC__OVR_EA_SDP1_PARTACK__SHIFT 0x1e +#define PCTL_SLICE1_MISC__OVR_EA_SDP1_FULLACK__SHIFT 0x1f +#define PCTL_SLICE1_MISC__RENG_EXECUTE_NONSECURE_START_PTR_MASK 0x000003FFL +#define PCTL_SLICE1_MISC__CRITICAL_REGS_LOCK_MASK 0x00000400L +#define PCTL_SLICE1_MISC__TILE_IDLE_THRESHOLD_MASK 0x00003800L +#define PCTL_SLICE1_MISC__RENG_MEM_LS_ENABLE_MASK 0x00004000L +#define PCTL_SLICE1_MISC__STCTRL_FORCE_PGFSM_CMD_DONE_MASK 0x00008000L +#define PCTL_SLICE1_MISC__DEEPSLEEP_DISCSDP_MASK 0x00010000L +#define PCTL_SLICE1_MISC__RENG_EXECUTE_ON_REG_UPDATE_MASK 0x00020000L +#define PCTL_SLICE1_MISC__RD_TIMER_ENABLE_MASK 0x00040000L +#define PCTL_SLICE1_MISC__RENG_MEM_DS_ENABLE_MASK 0x00080000L +#define PCTL_SLICE1_MISC__RENG_MEM_LS_TIMER_MASK 0x03F00000L +#define PCTL_SLICE1_MISC__RENG_MEM_SLEEP_TIMER_MASK 0x3C000000L +#define PCTL_SLICE1_MISC__OVR_EA_SDP1_PARTACK_MASK 0x40000000L +#define PCTL_SLICE1_MISC__OVR_EA_SDP1_FULLACK_MASK 0x80000000L +//PCTL_RENG_CTRL +#define PCTL_RENG_CTRL__RENG_EXECUTE_NOW__SHIFT 0x0 +#define PCTL_RENG_CTRL__RENG_EXECUTE_NOW_MODE__SHIFT 0x1 +#define PCTL_RENG_CTRL__RENG_EXECUTE_NOW_MASK 0x00000001L +#define PCTL_RENG_CTRL__RENG_EXECUTE_NOW_MODE_MASK 0x00000002L +//PCTL_UTCL2_RENG_EXECUTE +#define PCTL_UTCL2_RENG_EXECUTE__RENG_EXECUTE_NOW__SHIFT 0x0 +#define PCTL_UTCL2_RENG_EXECUTE__RENG_EXECUTE_NOW_MODE__SHIFT 0x1 +#define PCTL_UTCL2_RENG_EXECUTE__RENG_EXECUTE_NOW_START_PTR__SHIFT 0x2 +#define PCTL_UTCL2_RENG_EXECUTE__RENG_EXECUTE_END_PTR__SHIFT 0xd +#define PCTL_UTCL2_RENG_EXECUTE__RENG_EXECUTE_NOW_MASK 0x00000001L +#define PCTL_UTCL2_RENG_EXECUTE__RENG_EXECUTE_NOW_MODE_MASK 0x00000002L +#define PCTL_UTCL2_RENG_EXECUTE__RENG_EXECUTE_NOW_START_PTR_MASK 0x00001FFCL +#define PCTL_UTCL2_RENG_EXECUTE__RENG_EXECUTE_END_PTR_MASK 0x00FFE000L +//PCTL_UTCL2_RENG_RAM_INDEX +#define PCTL_UTCL2_RENG_RAM_INDEX__RENG_RAM_INDEX__SHIFT 0x0 +#define PCTL_UTCL2_RENG_RAM_INDEX__RENG_RAM_INDEX_MASK 0x000007FFL +//PCTL_UTCL2_RENG_RAM_DATA +#define PCTL_UTCL2_RENG_RAM_DATA__RENG_RAM_DATA__SHIFT 0x0 +#define PCTL_UTCL2_RENG_RAM_DATA__RENG_RAM_DATA_MASK 0xFFFFFFFFL +//PCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE0 +#define PCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_BASE__SHIFT 0x0 +#define PCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_LIMIT__SHIFT 0x10 +#define PCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_BASE_MASK 0x0000FFFFL +#define PCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_LIMIT_MASK 0xFFFF0000L +//PCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE1 +#define PCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_BASE__SHIFT 0x0 +#define PCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_LIMIT__SHIFT 0x10 +#define PCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_BASE_MASK 0x0000FFFFL +#define PCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_LIMIT_MASK 0xFFFF0000L +//PCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE2 +#define PCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_BASE__SHIFT 0x0 +#define PCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_LIMIT__SHIFT 0x10 +#define PCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_BASE_MASK 0x0000FFFFL +#define PCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_LIMIT_MASK 0xFFFF0000L +//PCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE3 +#define PCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_BASE__SHIFT 0x0 +#define PCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_LIMIT__SHIFT 0x10 +#define PCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_BASE_MASK 0x0000FFFFL +#define PCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_LIMIT_MASK 0xFFFF0000L +//PCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE4 +#define PCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_BASE__SHIFT 0x0 +#define PCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_LIMIT__SHIFT 0x10 +#define PCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_BASE_MASK 0x0000FFFFL +#define PCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_LIMIT_MASK 0xFFFF0000L +//PCTL_UTCL2_STCTRL_REGISTER_SAVE_EXCL_SET0 +#define PCTL_UTCL2_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL0__SHIFT 0x0 +#define PCTL_UTCL2_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL1__SHIFT 0x10 +#define PCTL_UTCL2_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL0_MASK 0x0000FFFFL +#define PCTL_UTCL2_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL1_MASK 0xFFFF0000L +//PCTL_UTCL2_STCTRL_REGISTER_SAVE_EXCL_SET1 +#define PCTL_UTCL2_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL2__SHIFT 0x0 +#define PCTL_UTCL2_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL3__SHIFT 0x10 +#define PCTL_UTCL2_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL2_MASK 0x0000FFFFL +#define PCTL_UTCL2_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL3_MASK 0xFFFF0000L +//PCTL_SLICE0_RENG_EXECUTE +#define PCTL_SLICE0_RENG_EXECUTE__RENG_EXECUTE_NOW__SHIFT 0x0 +#define PCTL_SLICE0_RENG_EXECUTE__RENG_EXECUTE_NOW_MODE__SHIFT 0x1 +#define PCTL_SLICE0_RENG_EXECUTE__RENG_EXECUTE_NOW_START_PTR__SHIFT 0x2 +#define PCTL_SLICE0_RENG_EXECUTE__RENG_EXECUTE_END_PTR__SHIFT 0xc +#define PCTL_SLICE0_RENG_EXECUTE__RENG_EXECUTE_NOW_MASK 0x00000001L +#define PCTL_SLICE0_RENG_EXECUTE__RENG_EXECUTE_NOW_MODE_MASK 0x00000002L +#define PCTL_SLICE0_RENG_EXECUTE__RENG_EXECUTE_NOW_START_PTR_MASK 0x00000FFCL +#define PCTL_SLICE0_RENG_EXECUTE__RENG_EXECUTE_END_PTR_MASK 0x003FF000L +//PCTL_SLICE0_RENG_RAM_INDEX +#define PCTL_SLICE0_RENG_RAM_INDEX__RENG_RAM_INDEX__SHIFT 0x0 +#define PCTL_SLICE0_RENG_RAM_INDEX__RENG_RAM_INDEX_MASK 0x000003FFL +//PCTL_SLICE0_RENG_RAM_DATA +#define PCTL_SLICE0_RENG_RAM_DATA__RENG_RAM_DATA__SHIFT 0x0 +#define PCTL_SLICE0_RENG_RAM_DATA__RENG_RAM_DATA_MASK 0xFFFFFFFFL +//PCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE0 +#define PCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_BASE__SHIFT 0x0 +#define PCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_LIMIT__SHIFT 0x10 +#define PCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_BASE_MASK 0x0000FFFFL +#define PCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_LIMIT_MASK 0xFFFF0000L +//PCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE1 +#define PCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_BASE__SHIFT 0x0 +#define PCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_LIMIT__SHIFT 0x10 +#define PCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_BASE_MASK 0x0000FFFFL +#define PCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_LIMIT_MASK 0xFFFF0000L +//PCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE2 +#define PCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_BASE__SHIFT 0x0 +#define PCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_LIMIT__SHIFT 0x10 +#define PCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_BASE_MASK 0x0000FFFFL +#define PCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_LIMIT_MASK 0xFFFF0000L +//PCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE3 +#define PCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_BASE__SHIFT 0x0 +#define PCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_LIMIT__SHIFT 0x10 +#define PCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_BASE_MASK 0x0000FFFFL +#define PCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_LIMIT_MASK 0xFFFF0000L +//PCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE4 +#define PCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_BASE__SHIFT 0x0 +#define PCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_LIMIT__SHIFT 0x10 +#define PCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_BASE_MASK 0x0000FFFFL +#define PCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_LIMIT_MASK 0xFFFF0000L +//PCTL_SLICE0_STCTRL_REGISTER_SAVE_EXCL_SET0 +#define PCTL_SLICE0_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL0__SHIFT 0x0 +#define PCTL_SLICE0_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL1__SHIFT 0x10 +#define PCTL_SLICE0_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL0_MASK 0x0000FFFFL +#define PCTL_SLICE0_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL1_MASK 0xFFFF0000L +//PCTL_SLICE0_STCTRL_REGISTER_SAVE_EXCL_SET1 +#define PCTL_SLICE0_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL2__SHIFT 0x0 +#define PCTL_SLICE0_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL3__SHIFT 0x10 +#define PCTL_SLICE0_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL2_MASK 0x0000FFFFL +#define PCTL_SLICE0_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL3_MASK 0xFFFF0000L +//PCTL_SLICE1_RENG_EXECUTE +#define PCTL_SLICE1_RENG_EXECUTE__RENG_EXECUTE_NOW__SHIFT 0x0 +#define PCTL_SLICE1_RENG_EXECUTE__RENG_EXECUTE_NOW_MODE__SHIFT 0x1 +#define PCTL_SLICE1_RENG_EXECUTE__RENG_EXECUTE_NOW_START_PTR__SHIFT 0x2 +#define PCTL_SLICE1_RENG_EXECUTE__RENG_EXECUTE_END_PTR__SHIFT 0xc +#define PCTL_SLICE1_RENG_EXECUTE__RENG_EXECUTE_NOW_MASK 0x00000001L +#define PCTL_SLICE1_RENG_EXECUTE__RENG_EXECUTE_NOW_MODE_MASK 0x00000002L +#define PCTL_SLICE1_RENG_EXECUTE__RENG_EXECUTE_NOW_START_PTR_MASK 0x00000FFCL +#define PCTL_SLICE1_RENG_EXECUTE__RENG_EXECUTE_END_PTR_MASK 0x003FF000L +//PCTL_SLICE1_RENG_RAM_INDEX +#define PCTL_SLICE1_RENG_RAM_INDEX__RENG_RAM_INDEX__SHIFT 0x0 +#define PCTL_SLICE1_RENG_RAM_INDEX__RENG_RAM_INDEX_MASK 0x000003FFL +//PCTL_SLICE1_RENG_RAM_DATA +#define PCTL_SLICE1_RENG_RAM_DATA__RENG_RAM_DATA__SHIFT 0x0 +#define PCTL_SLICE1_RENG_RAM_DATA__RENG_RAM_DATA_MASK 0xFFFFFFFFL +//PCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE0 +#define PCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_BASE__SHIFT 0x0 +#define PCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_LIMIT__SHIFT 0x10 +#define PCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_BASE_MASK 0x0000FFFFL +#define PCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_LIMIT_MASK 0xFFFF0000L +//PCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE1 +#define PCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_BASE__SHIFT 0x0 +#define PCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_LIMIT__SHIFT 0x10 +#define PCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_BASE_MASK 0x0000FFFFL +#define PCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_LIMIT_MASK 0xFFFF0000L +//PCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE2 +#define PCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_BASE__SHIFT 0x0 +#define PCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_LIMIT__SHIFT 0x10 +#define PCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_BASE_MASK 0x0000FFFFL +#define PCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_LIMIT_MASK 0xFFFF0000L +//PCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE3 +#define PCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_BASE__SHIFT 0x0 +#define PCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_LIMIT__SHIFT 0x10 +#define PCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_BASE_MASK 0x0000FFFFL +#define PCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_LIMIT_MASK 0xFFFF0000L +//PCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE4 +#define PCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_BASE__SHIFT 0x0 +#define PCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_LIMIT__SHIFT 0x10 +#define PCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_BASE_MASK 0x0000FFFFL +#define PCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_LIMIT_MASK 0xFFFF0000L +//PCTL_SLICE1_STCTRL_REGISTER_SAVE_EXCL_SET0 +#define PCTL_SLICE1_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL0__SHIFT 0x0 +#define PCTL_SLICE1_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL1__SHIFT 0x10 +#define PCTL_SLICE1_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL0_MASK 0x0000FFFFL +#define PCTL_SLICE1_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL1_MASK 0xFFFF0000L +//PCTL_SLICE1_STCTRL_REGISTER_SAVE_EXCL_SET1 +#define PCTL_SLICE1_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL2__SHIFT 0x0 +#define PCTL_SLICE1_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL3__SHIFT 0x10 +#define PCTL_SLICE1_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL2_MASK 0x0000FFFFL +#define PCTL_SLICE1_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL3_MASK 0xFFFF0000L +//PCTL_STATUS +#define PCTL_STATUS__MMHUB_INTERLOCK_AUTO_ACK__SHIFT 0x0 +#define PCTL_STATUS__MMHUB_INTERLOCK_ENABLE__SHIFT 0x1 +#define PCTL_STATUS__MMHUB_FENCE_REQ__SHIFT 0x2 +#define PCTL_STATUS__MMHUB_FENCE_ACK__SHIFT 0x3 +#define PCTL_STATUS__MMHUB_IDLE__SHIFT 0x4 +#define PCTL_STATUS__PGFSM_CMD_STATUS__SHIFT 0x5 +#define PCTL_STATUS__RSMU_RDTIMEOUT_CNT__SHIFT 0x7 +#define PCTL_STATUS__RSMU_RDTIMEOUT_CLEAR__SHIFT 0xf +#define PCTL_STATUS__MMHUB_POWER__SHIFT 0x10 +#define PCTL_STATUS__RENG_RAM_STALE__SHIFT 0x11 +#define PCTL_STATUS__UTCL2_RENG_RAM_STALE__SHIFT 0x12 +#define PCTL_STATUS__SLICE0_RENG_RAM_STALE__SHIFT 0x13 +#define PCTL_STATUS__SLICE1_RENG_RAM_STALE__SHIFT 0x14 +#define PCTL_STATUS__MMHUB_CONFIG_DONE__SHIFT 0x15 +#define PCTL_STATUS__NO_HALT__SHIFT 0x16 +#define PCTL_STATUS__FREE_REG_ACCESS__SHIFT 0x17 +#define PCTL_STATUS__MMHUB_INTERLOCK_AUTO_ACK_MASK 0x00000001L +#define PCTL_STATUS__MMHUB_INTERLOCK_ENABLE_MASK 0x00000002L +#define PCTL_STATUS__MMHUB_FENCE_REQ_MASK 0x00000004L +#define PCTL_STATUS__MMHUB_FENCE_ACK_MASK 0x00000008L +#define PCTL_STATUS__MMHUB_IDLE_MASK 0x00000010L +#define PCTL_STATUS__PGFSM_CMD_STATUS_MASK 0x00000060L +#define PCTL_STATUS__RSMU_RDTIMEOUT_CNT_MASK 0x00007F80L +#define PCTL_STATUS__RSMU_RDTIMEOUT_CLEAR_MASK 0x00008000L +#define PCTL_STATUS__MMHUB_POWER_MASK 0x00010000L +#define PCTL_STATUS__RENG_RAM_STALE_MASK 0x00020000L +#define PCTL_STATUS__UTCL2_RENG_RAM_STALE_MASK 0x00040000L +#define PCTL_STATUS__SLICE0_RENG_RAM_STALE_MASK 0x00080000L +#define PCTL_STATUS__SLICE1_RENG_RAM_STALE_MASK 0x00100000L +#define PCTL_STATUS__MMHUB_CONFIG_DONE_MASK 0x00200000L +#define PCTL_STATUS__NO_HALT_MASK 0x00400000L +#define PCTL_STATUS__FREE_REG_ACCESS_MASK 0x00800000L +//PCTL_PERFCOUNTER_LO +#define PCTL_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0 +#define PCTL_PERFCOUNTER_LO__COUNTER_LO_MASK 0xFFFFFFFFL +//PCTL_PERFCOUNTER_HI +#define PCTL_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0 +#define PCTL_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10 +#define PCTL_PERFCOUNTER_HI__COUNTER_HI_MASK 0x0000FFFFL +#define PCTL_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xFFFF0000L +//PCTL_PERFCOUNTER0_CFG +#define PCTL_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0 +#define PCTL_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8 +#define PCTL_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18 +#define PCTL_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c +#define PCTL_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d +#define PCTL_PERFCOUNTER0_CFG__PERF_SEL_MASK 0x000000FFL +#define PCTL_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0x0000FF00L +#define PCTL_PERFCOUNTER0_CFG__PERF_MODE_MASK 0x0F000000L +#define PCTL_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000L +#define PCTL_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000L +//PCTL_PERFCOUNTER1_CFG +#define PCTL_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0 +#define PCTL_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8 +#define PCTL_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18 +#define PCTL_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c +#define PCTL_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d +#define PCTL_PERFCOUNTER1_CFG__PERF_SEL_MASK 0x000000FFL +#define PCTL_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0x0000FF00L +#define PCTL_PERFCOUNTER1_CFG__PERF_MODE_MASK 0x0F000000L +#define PCTL_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000L +#define PCTL_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000L +//PCTL_PERFCOUNTER_RSLT_CNTL +#define PCTL_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0 +#define PCTL_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8 +#define PCTL_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10 +#define PCTL_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18 +#define PCTL_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19 +#define PCTL_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a +#define PCTL_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0x0000000FL +#define PCTL_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0x0000FF00L +#define PCTL_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0x00FF0000L +#define PCTL_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x01000000L +#define PCTL_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x02000000L +#define PCTL_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x04000000L +//PCTL_RESERVED_0 +#define PCTL_RESERVED_0__WORD__SHIFT 0x0 +#define PCTL_RESERVED_0__BYTE__SHIFT 0x10 +#define PCTL_RESERVED_0__BIT7__SHIFT 0x18 +#define PCTL_RESERVED_0__BIT6__SHIFT 0x19 +#define PCTL_RESERVED_0__BIT5__SHIFT 0x1a +#define PCTL_RESERVED_0__BIT4__SHIFT 0x1b +#define PCTL_RESERVED_0__BIT3__SHIFT 0x1c +#define PCTL_RESERVED_0__BIT2__SHIFT 0x1d +#define PCTL_RESERVED_0__BIT1__SHIFT 0x1e +#define PCTL_RESERVED_0__BIT0__SHIFT 0x1f +#define PCTL_RESERVED_0__WORD_MASK 0x0000FFFFL +#define PCTL_RESERVED_0__BYTE_MASK 0x00FF0000L +#define PCTL_RESERVED_0__BIT7_MASK 0x01000000L +#define PCTL_RESERVED_0__BIT6_MASK 0x02000000L +#define PCTL_RESERVED_0__BIT5_MASK 0x04000000L +#define PCTL_RESERVED_0__BIT4_MASK 0x08000000L +#define PCTL_RESERVED_0__BIT3_MASK 0x10000000L +#define PCTL_RESERVED_0__BIT2_MASK 0x20000000L +#define PCTL_RESERVED_0__BIT1_MASK 0x40000000L +#define PCTL_RESERVED_0__BIT0_MASK 0x80000000L +//PCTL_RESERVED_1 +#define PCTL_RESERVED_1__WORD__SHIFT 0x0 +#define PCTL_RESERVED_1__BYTE__SHIFT 0x10 +#define PCTL_RESERVED_1__BIT7__SHIFT 0x18 +#define PCTL_RESERVED_1__BIT6__SHIFT 0x19 +#define PCTL_RESERVED_1__BIT5__SHIFT 0x1a +#define PCTL_RESERVED_1__BIT4__SHIFT 0x1b +#define PCTL_RESERVED_1__BIT3__SHIFT 0x1c +#define PCTL_RESERVED_1__BIT2__SHIFT 0x1d +#define PCTL_RESERVED_1__BIT1__SHIFT 0x1e +#define PCTL_RESERVED_1__BIT0__SHIFT 0x1f +#define PCTL_RESERVED_1__WORD_MASK 0x0000FFFFL +#define PCTL_RESERVED_1__BYTE_MASK 0x00FF0000L +#define PCTL_RESERVED_1__BIT7_MASK 0x01000000L +#define PCTL_RESERVED_1__BIT6_MASK 0x02000000L +#define PCTL_RESERVED_1__BIT5_MASK 0x04000000L +#define PCTL_RESERVED_1__BIT4_MASK 0x08000000L +#define PCTL_RESERVED_1__BIT3_MASK 0x10000000L +#define PCTL_RESERVED_1__BIT2_MASK 0x20000000L +#define PCTL_RESERVED_1__BIT1_MASK 0x40000000L +#define PCTL_RESERVED_1__BIT0_MASK 0x80000000L +//PCTL_RESERVED_2 +#define PCTL_RESERVED_2__WORD__SHIFT 0x0 +#define PCTL_RESERVED_2__BYTE__SHIFT 0x10 +#define PCTL_RESERVED_2__BIT7__SHIFT 0x18 +#define PCTL_RESERVED_2__BIT6__SHIFT 0x19 +#define PCTL_RESERVED_2__BIT5__SHIFT 0x1a +#define PCTL_RESERVED_2__BIT4__SHIFT 0x1b +#define PCTL_RESERVED_2__BIT3__SHIFT 0x1c +#define PCTL_RESERVED_2__BIT2__SHIFT 0x1d +#define PCTL_RESERVED_2__BIT1__SHIFT 0x1e +#define PCTL_RESERVED_2__BIT0__SHIFT 0x1f +#define PCTL_RESERVED_2__WORD_MASK 0x0000FFFFL +#define PCTL_RESERVED_2__BYTE_MASK 0x00FF0000L +#define PCTL_RESERVED_2__BIT7_MASK 0x01000000L +#define PCTL_RESERVED_2__BIT6_MASK 0x02000000L +#define PCTL_RESERVED_2__BIT5_MASK 0x04000000L +#define PCTL_RESERVED_2__BIT4_MASK 0x08000000L +#define PCTL_RESERVED_2__BIT3_MASK 0x10000000L +#define PCTL_RESERVED_2__BIT2_MASK 0x20000000L +#define PCTL_RESERVED_2__BIT1_MASK 0x40000000L +#define PCTL_RESERVED_2__BIT0_MASK 0x80000000L +//PCTL_RESERVED_3 +#define PCTL_RESERVED_3__WORD__SHIFT 0x0 +#define PCTL_RESERVED_3__BYTE__SHIFT 0x10 +#define PCTL_RESERVED_3__BIT7__SHIFT 0x18 +#define PCTL_RESERVED_3__BIT6__SHIFT 0x19 +#define PCTL_RESERVED_3__BIT5__SHIFT 0x1a +#define PCTL_RESERVED_3__BIT4__SHIFT 0x1b +#define PCTL_RESERVED_3__BIT3__SHIFT 0x1c +#define PCTL_RESERVED_3__BIT2__SHIFT 0x1d +#define PCTL_RESERVED_3__BIT1__SHIFT 0x1e +#define PCTL_RESERVED_3__BIT0__SHIFT 0x1f +#define PCTL_RESERVED_3__WORD_MASK 0x0000FFFFL +#define PCTL_RESERVED_3__BYTE_MASK 0x00FF0000L +#define PCTL_RESERVED_3__BIT7_MASK 0x01000000L +#define PCTL_RESERVED_3__BIT6_MASK 0x02000000L +#define PCTL_RESERVED_3__BIT5_MASK 0x04000000L +#define PCTL_RESERVED_3__BIT4_MASK 0x08000000L +#define PCTL_RESERVED_3__BIT3_MASK 0x10000000L +#define PCTL_RESERVED_3__BIT2_MASK 0x20000000L +#define PCTL_RESERVED_3__BIT1_MASK 0x40000000L +#define PCTL_RESERVED_3__BIT0_MASK 0x80000000L + + +// addressBlock: mmhub_mmutcl2_mmvmsharedpfdec +//MMMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB +#define MMMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB__PHYSICAL_PAGE_NUMBER_LSB__SHIFT 0x0 +#define MMMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB__PHYSICAL_PAGE_NUMBER_LSB_MASK 0xFFFFFFFFL +//MMMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB +#define MMMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB__PHYSICAL_PAGE_NUMBER_MSB__SHIFT 0x0 +#define MMMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB__PHYSICAL_PAGE_NUMBER_MSB_MASK 0x0000000FL +//MMUTCL2_CGTT_CLK_CTRL +#define MMUTCL2_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 +#define MMUTCL2_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x5 +#define MMUTCL2_CGTT_CLK_CTRL__LS_ASSERT_HYSTERESIS__SHIFT 0xd +#define MMUTCL2_CGTT_CLK_CTRL__MIN_MGLS__SHIFT 0x1a +#define MMUTCL2_CGTT_CLK_CTRL__CGLS_DISABLE__SHIFT 0x1d +#define MMUTCL2_CGTT_CLK_CTRL__LS_DISABLE__SHIFT 0x1e +#define MMUTCL2_CGTT_CLK_CTRL__BUSY_OVERRIDE__SHIFT 0x1f +#define MMUTCL2_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000001FL +#define MMUTCL2_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00001FE0L +#define MMUTCL2_CGTT_CLK_CTRL__LS_ASSERT_HYSTERESIS_MASK 0x03FFE000L +#define MMUTCL2_CGTT_CLK_CTRL__MIN_MGLS_MASK 0x1C000000L +#define MMUTCL2_CGTT_CLK_CTRL__CGLS_DISABLE_MASK 0x20000000L +#define MMUTCL2_CGTT_CLK_CTRL__LS_DISABLE_MASK 0x40000000L +#define MMUTCL2_CGTT_CLK_CTRL__BUSY_OVERRIDE_MASK 0x80000000L +//MMMC_SHARED_ACTIVE_FCN_ID +#define MMMC_SHARED_ACTIVE_FCN_ID__VFID__SHIFT 0x0 +#define MMMC_SHARED_ACTIVE_FCN_ID__VF__SHIFT 0x1f +#define MMMC_SHARED_ACTIVE_FCN_ID__VFID_MASK 0x0000001FL +#define MMMC_SHARED_ACTIVE_FCN_ID__VF_MASK 0x80000000L +//MMUTCL2_CGTT_BUSY_CTRL +#define MMUTCL2_CGTT_BUSY_CTRL__READ_DELAY__SHIFT 0x0 +#define MMUTCL2_CGTT_BUSY_CTRL__ALWAYS_BUSY__SHIFT 0x5 +#define MMUTCL2_CGTT_BUSY_CTRL__READ_DELAY_MASK 0x0000001FL +#define MMUTCL2_CGTT_BUSY_CTRL__ALWAYS_BUSY_MASK 0x00000020L +//MMUTCL2_GROUP_RET_FAULT_STATUS +#define MMUTCL2_GROUP_RET_FAULT_STATUS__FAULT_GROUPS__SHIFT 0x0 +#define MMUTCL2_GROUP_RET_FAULT_STATUS__FAULT_GROUPS_MASK 0xFFFFFFFFL + + +// addressBlock: mmhub_mmutcl2_mmvml2pfdec +//MMVM_L2_CNTL +#define MMVM_L2_CNTL__ENABLE_L2_CACHE__SHIFT 0x0 +#define MMVM_L2_CNTL__ENABLE_L2_FRAGMENT_PROCESSING__SHIFT 0x1 +#define MMVM_L2_CNTL__L2_CACHE_PTE_ENDIAN_SWAP_MODE__SHIFT 0x2 +#define MMVM_L2_CNTL__L2_CACHE_PDE_ENDIAN_SWAP_MODE__SHIFT 0x4 +#define MMVM_L2_CNTL__L2_PDE0_CACHE_TAG_GENERATION_MODE__SHIFT 0x8 +#define MMVM_L2_CNTL__ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE__SHIFT 0x9 +#define MMVM_L2_CNTL__ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE__SHIFT 0xa +#define MMVM_L2_CNTL__ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY__SHIFT 0xb +#define MMVM_L2_CNTL__L2_PDE0_CACHE_SPLIT_MODE__SHIFT 0xc +#define MMVM_L2_CNTL__EFFECTIVE_L2_QUEUE_SIZE__SHIFT 0xf +#define MMVM_L2_CNTL__PDE_FAULT_CLASSIFICATION__SHIFT 0x12 +#define MMVM_L2_CNTL__CONTEXT1_IDENTITY_ACCESS_MODE__SHIFT 0x13 +#define MMVM_L2_CNTL__IDENTITY_MODE_FRAGMENT_SIZE__SHIFT 0x15 +#define MMVM_L2_CNTL__L2_PTE_CACHE_ADDR_MODE__SHIFT 0x1a +#define MMVM_L2_CNTL__ENABLE_L2_CACHE_MASK 0x00000001L +#define MMVM_L2_CNTL__ENABLE_L2_FRAGMENT_PROCESSING_MASK 0x00000002L +#define MMVM_L2_CNTL__L2_CACHE_PTE_ENDIAN_SWAP_MODE_MASK 0x0000000CL +#define MMVM_L2_CNTL__L2_CACHE_PDE_ENDIAN_SWAP_MODE_MASK 0x00000030L +#define MMVM_L2_CNTL__L2_PDE0_CACHE_TAG_GENERATION_MODE_MASK 0x00000100L +#define MMVM_L2_CNTL__ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE_MASK 0x00000200L +#define MMVM_L2_CNTL__ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE_MASK 0x00000400L +#define MMVM_L2_CNTL__ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY_MASK 0x00000800L +#define MMVM_L2_CNTL__L2_PDE0_CACHE_SPLIT_MODE_MASK 0x00007000L +#define MMVM_L2_CNTL__EFFECTIVE_L2_QUEUE_SIZE_MASK 0x00038000L +#define MMVM_L2_CNTL__PDE_FAULT_CLASSIFICATION_MASK 0x00040000L +#define MMVM_L2_CNTL__CONTEXT1_IDENTITY_ACCESS_MODE_MASK 0x00180000L +#define MMVM_L2_CNTL__IDENTITY_MODE_FRAGMENT_SIZE_MASK 0x03E00000L +#define MMVM_L2_CNTL__L2_PTE_CACHE_ADDR_MODE_MASK 0x0C000000L +//MMVM_L2_CNTL2 +#define MMVM_L2_CNTL2__INVALIDATE_ALL_L1_TLBS__SHIFT 0x0 +#define MMVM_L2_CNTL2__INVALIDATE_L2_CACHE__SHIFT 0x1 +#define MMVM_L2_CNTL2__DISABLE_INVALIDATE_PER_DOMAIN__SHIFT 0x15 +#define MMVM_L2_CNTL2__DISABLE_BIGK_CACHE_OPTIMIZATION__SHIFT 0x16 +#define MMVM_L2_CNTL2__L2_PTE_CACHE_VMID_MODE__SHIFT 0x17 +#define MMVM_L2_CNTL2__INVALIDATE_CACHE_MODE__SHIFT 0x1a +#define MMVM_L2_CNTL2__PDE_CACHE_EFFECTIVE_SIZE__SHIFT 0x1c +#define MMVM_L2_CNTL2__INVALIDATE_ALL_L1_TLBS_MASK 0x00000001L +#define MMVM_L2_CNTL2__INVALIDATE_L2_CACHE_MASK 0x00000002L +#define MMVM_L2_CNTL2__DISABLE_INVALIDATE_PER_DOMAIN_MASK 0x00200000L +#define MMVM_L2_CNTL2__DISABLE_BIGK_CACHE_OPTIMIZATION_MASK 0x00400000L +#define MMVM_L2_CNTL2__L2_PTE_CACHE_VMID_MODE_MASK 0x03800000L +#define MMVM_L2_CNTL2__INVALIDATE_CACHE_MODE_MASK 0x0C000000L +#define MMVM_L2_CNTL2__PDE_CACHE_EFFECTIVE_SIZE_MASK 0x70000000L +//MMVM_L2_CNTL3 +#define MMVM_L2_CNTL3__BANK_SELECT__SHIFT 0x0 +#define MMVM_L2_CNTL3__L2_CACHE_UPDATE_MODE__SHIFT 0x6 +#define MMVM_L2_CNTL3__L2_CACHE_UPDATE_WILDCARD_REFERENCE_VALUE__SHIFT 0x8 +#define MMVM_L2_CNTL3__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT 0xf +#define MMVM_L2_CNTL3__L2_CACHE_BIGK_ASSOCIATIVITY__SHIFT 0x14 +#define MMVM_L2_CNTL3__L2_CACHE_4K_EFFECTIVE_SIZE__SHIFT 0x15 +#define MMVM_L2_CNTL3__L2_CACHE_BIGK_EFFECTIVE_SIZE__SHIFT 0x18 +#define MMVM_L2_CNTL3__L2_CACHE_4K_FORCE_MISS__SHIFT 0x1c +#define MMVM_L2_CNTL3__L2_CACHE_BIGK_FORCE_MISS__SHIFT 0x1d +#define MMVM_L2_CNTL3__PDE_CACHE_FORCE_MISS__SHIFT 0x1e +#define MMVM_L2_CNTL3__L2_CACHE_4K_ASSOCIATIVITY__SHIFT 0x1f +#define MMVM_L2_CNTL3__BANK_SELECT_MASK 0x0000003FL +#define MMVM_L2_CNTL3__L2_CACHE_UPDATE_MODE_MASK 0x000000C0L +#define MMVM_L2_CNTL3__L2_CACHE_UPDATE_WILDCARD_REFERENCE_VALUE_MASK 0x00001F00L +#define MMVM_L2_CNTL3__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK 0x000F8000L +#define MMVM_L2_CNTL3__L2_CACHE_BIGK_ASSOCIATIVITY_MASK 0x00100000L +#define MMVM_L2_CNTL3__L2_CACHE_4K_EFFECTIVE_SIZE_MASK 0x00E00000L +#define MMVM_L2_CNTL3__L2_CACHE_BIGK_EFFECTIVE_SIZE_MASK 0x0F000000L +#define MMVM_L2_CNTL3__L2_CACHE_4K_FORCE_MISS_MASK 0x10000000L +#define MMVM_L2_CNTL3__L2_CACHE_BIGK_FORCE_MISS_MASK 0x20000000L +#define MMVM_L2_CNTL3__PDE_CACHE_FORCE_MISS_MASK 0x40000000L +#define MMVM_L2_CNTL3__L2_CACHE_4K_ASSOCIATIVITY_MASK 0x80000000L +//MMVM_L2_STATUS +#define MMVM_L2_STATUS__L2_BUSY__SHIFT 0x0 +#define MMVM_L2_STATUS__CONTEXT_DOMAIN_BUSY__SHIFT 0x1 +#define MMVM_L2_STATUS__FOUND_4K_PTE_CACHE_PARITY_ERRORS__SHIFT 0x11 +#define MMVM_L2_STATUS__FOUND_BIGK_PTE_CACHE_PARITY_ERRORS__SHIFT 0x12 +#define MMVM_L2_STATUS__FOUND_PDE0_CACHE_PARITY_ERRORS__SHIFT 0x13 +#define MMVM_L2_STATUS__FOUND_PDE1_CACHE_PARITY_ERRORS__SHIFT 0x14 +#define MMVM_L2_STATUS__FOUND_PDE2_CACHE_PARITY_ERRORS__SHIFT 0x15 +#define MMVM_L2_STATUS__L2_BUSY_MASK 0x00000001L +#define MMVM_L2_STATUS__CONTEXT_DOMAIN_BUSY_MASK 0x0001FFFEL +#define MMVM_L2_STATUS__FOUND_4K_PTE_CACHE_PARITY_ERRORS_MASK 0x00020000L +#define MMVM_L2_STATUS__FOUND_BIGK_PTE_CACHE_PARITY_ERRORS_MASK 0x00040000L +#define MMVM_L2_STATUS__FOUND_PDE0_CACHE_PARITY_ERRORS_MASK 0x00080000L +#define MMVM_L2_STATUS__FOUND_PDE1_CACHE_PARITY_ERRORS_MASK 0x00100000L +#define MMVM_L2_STATUS__FOUND_PDE2_CACHE_PARITY_ERRORS_MASK 0x00200000L +//MMVM_DUMMY_PAGE_FAULT_CNTL +#define MMVM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_FAULT_ENABLE__SHIFT 0x0 +#define MMVM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_ADDRESS_LOGICAL__SHIFT 0x1 +#define MMVM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_COMPARE_MSBS__SHIFT 0x2 +#define MMVM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_FAULT_ENABLE_MASK 0x00000001L +#define MMVM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_ADDRESS_LOGICAL_MASK 0x00000002L +#define MMVM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_COMPARE_MSBS_MASK 0x000000FCL +//MMVM_DUMMY_PAGE_FAULT_ADDR_LO32 +#define MMVM_DUMMY_PAGE_FAULT_ADDR_LO32__DUMMY_PAGE_ADDR_LO32__SHIFT 0x0 +#define MMVM_DUMMY_PAGE_FAULT_ADDR_LO32__DUMMY_PAGE_ADDR_LO32_MASK 0xFFFFFFFFL +//MMVM_DUMMY_PAGE_FAULT_ADDR_HI32 +#define MMVM_DUMMY_PAGE_FAULT_ADDR_HI32__DUMMY_PAGE_ADDR_HI4__SHIFT 0x0 +#define MMVM_DUMMY_PAGE_FAULT_ADDR_HI32__DUMMY_PAGE_ADDR_HI4_MASK 0x0000000FL +//MMVM_INVALIDATE_CNTL +#define MMVM_INVALIDATE_CNTL__PRI_REG_ALTERNATING__SHIFT 0x0 +#define MMVM_INVALIDATE_CNTL__MAX_REG_OUTSTANDING__SHIFT 0x8 +#define MMVM_INVALIDATE_CNTL__PRI_REG_ALTERNATING_MASK 0x000000FFL +#define MMVM_INVALIDATE_CNTL__MAX_REG_OUTSTANDING_MASK 0x0000FF00L +//MMVM_L2_PROTECTION_FAULT_CNTL_LO32 +#define MMVM_L2_PROTECTION_FAULT_CNTL_LO32__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x0 +#define MMVM_L2_PROTECTION_FAULT_CNTL_LO32__ALLOW_SUBSEQUENT_PROTECTION_FAULT_STATUS_ADDR_UPDATES__SHIFT 0x1 +#define MMVM_L2_PROTECTION_FAULT_CNTL_LO32__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x2 +#define MMVM_L2_PROTECTION_FAULT_CNTL_LO32__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x3 +#define MMVM_L2_PROTECTION_FAULT_CNTL_LO32__PDE1_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x4 +#define MMVM_L2_PROTECTION_FAULT_CNTL_LO32__PDE2_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x5 +#define MMVM_L2_PROTECTION_FAULT_CNTL_LO32__PDE3_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x6 +#define MMVM_L2_PROTECTION_FAULT_CNTL_LO32__TRANSLATE_FURTHER_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x7 +#define MMVM_L2_PROTECTION_FAULT_CNTL_LO32__NACK_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x8 +#define MMVM_L2_PROTECTION_FAULT_CNTL_LO32__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x9 +#define MMVM_L2_PROTECTION_FAULT_CNTL_LO32__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa +#define MMVM_L2_PROTECTION_FAULT_CNTL_LO32__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xb +#define MMVM_L2_PROTECTION_FAULT_CNTL_LO32__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc +#define MMVM_L2_PROTECTION_FAULT_CNTL_LO32__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xd +#define MMVM_L2_PROTECTION_FAULT_CNTL_LO32__CLIENT_ID_NO_RETRY_FAULT_INTERRUPT__SHIFT 0xe +#define MMVM_L2_PROTECTION_FAULT_CNTL_LO32__OTHER_CLIENT_ID_NO_RETRY_FAULT_INTERRUPT__SHIFT 0x1e +#define MMVM_L2_PROTECTION_FAULT_CNTL_LO32__CRASH_ON_NO_RETRY_FAULT__SHIFT 0x1f +#define MMVM_L2_PROTECTION_FAULT_CNTL_LO32__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00000001L +#define MMVM_L2_PROTECTION_FAULT_CNTL_LO32__ALLOW_SUBSEQUENT_PROTECTION_FAULT_STATUS_ADDR_UPDATES_MASK 0x00000002L +#define MMVM_L2_PROTECTION_FAULT_CNTL_LO32__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000004L +#define MMVM_L2_PROTECTION_FAULT_CNTL_LO32__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000008L +#define MMVM_L2_PROTECTION_FAULT_CNTL_LO32__PDE1_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000010L +#define MMVM_L2_PROTECTION_FAULT_CNTL_LO32__PDE2_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000020L +#define MMVM_L2_PROTECTION_FAULT_CNTL_LO32__PDE3_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000040L +#define MMVM_L2_PROTECTION_FAULT_CNTL_LO32__TRANSLATE_FURTHER_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000080L +#define MMVM_L2_PROTECTION_FAULT_CNTL_LO32__NACK_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000100L +#define MMVM_L2_PROTECTION_FAULT_CNTL_LO32__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000200L +#define MMVM_L2_PROTECTION_FAULT_CNTL_LO32__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L +#define MMVM_L2_PROTECTION_FAULT_CNTL_LO32__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000800L +#define MMVM_L2_PROTECTION_FAULT_CNTL_LO32__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L +#define MMVM_L2_PROTECTION_FAULT_CNTL_LO32__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00002000L +#define MMVM_L2_PROTECTION_FAULT_CNTL_LO32__CLIENT_ID_NO_RETRY_FAULT_INTERRUPT_MASK 0x3FFFC000L +#define MMVM_L2_PROTECTION_FAULT_CNTL_LO32__OTHER_CLIENT_ID_NO_RETRY_FAULT_INTERRUPT_MASK 0x40000000L +#define MMVM_L2_PROTECTION_FAULT_CNTL_LO32__CRASH_ON_NO_RETRY_FAULT_MASK 0x80000000L +//MMVM_L2_PROTECTION_FAULT_CNTL_HI32 +#define MMVM_L2_PROTECTION_FAULT_CNTL_HI32__CRASH_ON_RETRY_FAULT__SHIFT 0x0 +#define MMVM_L2_PROTECTION_FAULT_CNTL_HI32__CRASH_ON_RETRY_FAULT_MASK 0x00000001L +//MMVM_L2_PROTECTION_FAULT_CNTL2 +#define MMVM_L2_PROTECTION_FAULT_CNTL2__CLIENT_ID_PRT_FAULT_INTERRUPT__SHIFT 0x0 +#define MMVM_L2_PROTECTION_FAULT_CNTL2__OTHER_CLIENT_ID_PRT_FAULT_INTERRUPT__SHIFT 0x10 +#define MMVM_L2_PROTECTION_FAULT_CNTL2__ACTIVE_PAGE_MIGRATION_PTE__SHIFT 0x11 +#define MMVM_L2_PROTECTION_FAULT_CNTL2__ACTIVE_PAGE_MIGRATION_PTE_READ_RETRY__SHIFT 0x12 +#define MMVM_L2_PROTECTION_FAULT_CNTL2__ENABLE_RETRY_FAULT_INTERRUPT__SHIFT 0x13 +#define MMVM_L2_PROTECTION_FAULT_CNTL2__CLIENT_ID_PRT_FAULT_INTERRUPT_MASK 0x0000FFFFL +#define MMVM_L2_PROTECTION_FAULT_CNTL2__OTHER_CLIENT_ID_PRT_FAULT_INTERRUPT_MASK 0x00010000L +#define MMVM_L2_PROTECTION_FAULT_CNTL2__ACTIVE_PAGE_MIGRATION_PTE_MASK 0x00020000L +#define MMVM_L2_PROTECTION_FAULT_CNTL2__ACTIVE_PAGE_MIGRATION_PTE_READ_RETRY_MASK 0x00040000L +#define MMVM_L2_PROTECTION_FAULT_CNTL2__ENABLE_RETRY_FAULT_INTERRUPT_MASK 0x00080000L +//MMVM_L2_PROTECTION_FAULT_STATUS_LO32 +#define MMVM_L2_PROTECTION_FAULT_STATUS_LO32__MORE_FAULTS__SHIFT 0x0 +#define MMVM_L2_PROTECTION_FAULT_STATUS_LO32__WALKER_ERROR__SHIFT 0x1 +#define MMVM_L2_PROTECTION_FAULT_STATUS_LO32__PERMISSION_FAULTS__SHIFT 0x5 +#define MMVM_L2_PROTECTION_FAULT_STATUS_LO32__MAPPING_ERROR__SHIFT 0xa +#define MMVM_L2_PROTECTION_FAULT_STATUS_LO32__CID__SHIFT 0xb +#define MMVM_L2_PROTECTION_FAULT_STATUS_LO32__RW__SHIFT 0x14 +#define MMVM_L2_PROTECTION_FAULT_STATUS_LO32__ATOMIC__SHIFT 0x15 +#define MMVM_L2_PROTECTION_FAULT_STATUS_LO32__VMID__SHIFT 0x16 +#define MMVM_L2_PROTECTION_FAULT_STATUS_LO32__VF__SHIFT 0x1a +#define MMVM_L2_PROTECTION_FAULT_STATUS_LO32__VFID__SHIFT 0x1b +#define MMVM_L2_PROTECTION_FAULT_STATUS_LO32__MORE_FAULTS_MASK 0x00000001L +#define MMVM_L2_PROTECTION_FAULT_STATUS_LO32__WALKER_ERROR_MASK 0x0000001EL +#define MMVM_L2_PROTECTION_FAULT_STATUS_LO32__PERMISSION_FAULTS_MASK 0x000003E0L +#define MMVM_L2_PROTECTION_FAULT_STATUS_LO32__MAPPING_ERROR_MASK 0x00000400L +#define MMVM_L2_PROTECTION_FAULT_STATUS_LO32__CID_MASK 0x000FF800L +#define MMVM_L2_PROTECTION_FAULT_STATUS_LO32__RW_MASK 0x00100000L +#define MMVM_L2_PROTECTION_FAULT_STATUS_LO32__ATOMIC_MASK 0x00200000L +#define MMVM_L2_PROTECTION_FAULT_STATUS_LO32__VMID_MASK 0x03C00000L +#define MMVM_L2_PROTECTION_FAULT_STATUS_LO32__VF_MASK 0x04000000L +#define MMVM_L2_PROTECTION_FAULT_STATUS_LO32__VFID_MASK 0xF8000000L +//MMVM_L2_PROTECTION_FAULT_STATUS_HI32 +#define MMVM_L2_PROTECTION_FAULT_STATUS_HI32__PRT__SHIFT 0x0 +#define MMVM_L2_PROTECTION_FAULT_STATUS_HI32__FED__SHIFT 0x2 +#define MMVM_L2_PROTECTION_FAULT_STATUS_HI32__PRT_MASK 0x00000001L +#define MMVM_L2_PROTECTION_FAULT_STATUS_HI32__FED_MASK 0x00000004L +//MMVM_L2_PROTECTION_FAULT_ADDR_LO32 +#define MMVM_L2_PROTECTION_FAULT_ADDR_LO32__LOGICAL_PAGE_ADDR_LO32__SHIFT 0x0 +#define MMVM_L2_PROTECTION_FAULT_ADDR_LO32__LOGICAL_PAGE_ADDR_LO32_MASK 0xFFFFFFFFL +//MMVM_L2_PROTECTION_FAULT_ADDR_HI32 +#define MMVM_L2_PROTECTION_FAULT_ADDR_HI32__LOGICAL_PAGE_ADDR_HI4__SHIFT 0x0 +#define MMVM_L2_PROTECTION_FAULT_ADDR_HI32__LOGICAL_PAGE_ADDR_HI4_MASK 0x0000000FL +//MMVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32 +#define MMVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32__PHYSICAL_PAGE_ADDR_LO32__SHIFT 0x0 +#define MMVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32__PHYSICAL_PAGE_ADDR_LO32_MASK 0xFFFFFFFFL +//MMVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32 +#define MMVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32__PHYSICAL_PAGE_ADDR_HI4__SHIFT 0x0 +#define MMVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32__PHYSICAL_PAGE_ADDR_HI4_MASK 0x0000000FL +//MMVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32 +#define MMVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define MMVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//MMVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32 +#define MMVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define MMVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//MMVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32 +#define MMVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define MMVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//MMVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32 +#define MMVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define MMVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//MMVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32 +#define MMVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32__PHYSICAL_PAGE_OFFSET_LO32__SHIFT 0x0 +#define MMVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32__PHYSICAL_PAGE_OFFSET_LO32_MASK 0xFFFFFFFFL +//MMVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32 +#define MMVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32__PHYSICAL_PAGE_OFFSET_HI4__SHIFT 0x0 +#define MMVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32__PHYSICAL_PAGE_OFFSET_HI4_MASK 0x0000000FL +//MMVM_L2_CNTL4 +#define MMVM_L2_CNTL4__L2_CACHE_4K_PARTITION_COUNT__SHIFT 0x0 +#define MMVM_L2_CNTL4__VMC_TAP_PDE_REQUEST_PHYSICAL__SHIFT 0x6 +#define MMVM_L2_CNTL4__VMC_TAP_PTE_REQUEST_PHYSICAL__SHIFT 0x7 +#define MMVM_L2_CNTL4__MM_NONRT_IFIFO_ACTIVE_TRANSACTION_LIMIT__SHIFT 0x8 +#define MMVM_L2_CNTL4__MM_SOFTRT_IFIFO_ACTIVE_TRANSACTION_LIMIT__SHIFT 0x12 +#define MMVM_L2_CNTL4__BPM_CGCGLS_OVERRIDE__SHIFT 0x1c +#define MMVM_L2_CNTL4__GC_CH_FGCG_OFF__SHIFT 0x1d +#define MMVM_L2_CNTL4__VFIFO_HEAD_OF_QUEUE__SHIFT 0x1e +#define MMVM_L2_CNTL4__VFIFO_VISIBLE_BANK_SILOS__SHIFT 0x1f +#define MMVM_L2_CNTL4__L2_CACHE_4K_PARTITION_COUNT_MASK 0x0000003FL +#define MMVM_L2_CNTL4__VMC_TAP_PDE_REQUEST_PHYSICAL_MASK 0x00000040L +#define MMVM_L2_CNTL4__VMC_TAP_PTE_REQUEST_PHYSICAL_MASK 0x00000080L +#define MMVM_L2_CNTL4__MM_NONRT_IFIFO_ACTIVE_TRANSACTION_LIMIT_MASK 0x0003FF00L +#define MMVM_L2_CNTL4__MM_SOFTRT_IFIFO_ACTIVE_TRANSACTION_LIMIT_MASK 0x0FFC0000L +#define MMVM_L2_CNTL4__BPM_CGCGLS_OVERRIDE_MASK 0x10000000L +#define MMVM_L2_CNTL4__GC_CH_FGCG_OFF_MASK 0x20000000L +#define MMVM_L2_CNTL4__VFIFO_HEAD_OF_QUEUE_MASK 0x40000000L +#define MMVM_L2_CNTL4__VFIFO_VISIBLE_BANK_SILOS_MASK 0x80000000L +//MMVM_L2_MM_GROUP_RT_CLASSES +#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_0_RT_CLASS__SHIFT 0x0 +#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_1_RT_CLASS__SHIFT 0x1 +#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_2_RT_CLASS__SHIFT 0x2 +#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_3_RT_CLASS__SHIFT 0x3 +#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_4_RT_CLASS__SHIFT 0x4 +#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_5_RT_CLASS__SHIFT 0x5 +#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_6_RT_CLASS__SHIFT 0x6 +#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_7_RT_CLASS__SHIFT 0x7 +#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_8_RT_CLASS__SHIFT 0x8 +#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_9_RT_CLASS__SHIFT 0x9 +#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_10_RT_CLASS__SHIFT 0xa +#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_11_RT_CLASS__SHIFT 0xb +#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_12_RT_CLASS__SHIFT 0xc +#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_13_RT_CLASS__SHIFT 0xd +#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_14_RT_CLASS__SHIFT 0xe +#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_15_RT_CLASS__SHIFT 0xf +#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_16_RT_CLASS__SHIFT 0x10 +#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_17_RT_CLASS__SHIFT 0x11 +#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_18_RT_CLASS__SHIFT 0x12 +#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_19_RT_CLASS__SHIFT 0x13 +#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_20_RT_CLASS__SHIFT 0x14 +#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_21_RT_CLASS__SHIFT 0x15 +#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_22_RT_CLASS__SHIFT 0x16 +#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_23_RT_CLASS__SHIFT 0x17 +#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_24_RT_CLASS__SHIFT 0x18 +#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_25_RT_CLASS__SHIFT 0x19 +#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_26_RT_CLASS__SHIFT 0x1a +#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_27_RT_CLASS__SHIFT 0x1b +#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_28_RT_CLASS__SHIFT 0x1c +#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_29_RT_CLASS__SHIFT 0x1d +#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_30_RT_CLASS__SHIFT 0x1e +#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_31_RT_CLASS__SHIFT 0x1f +#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_0_RT_CLASS_MASK 0x00000001L +#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_1_RT_CLASS_MASK 0x00000002L +#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_2_RT_CLASS_MASK 0x00000004L +#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_3_RT_CLASS_MASK 0x00000008L +#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_4_RT_CLASS_MASK 0x00000010L +#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_5_RT_CLASS_MASK 0x00000020L +#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_6_RT_CLASS_MASK 0x00000040L +#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_7_RT_CLASS_MASK 0x00000080L +#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_8_RT_CLASS_MASK 0x00000100L +#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_9_RT_CLASS_MASK 0x00000200L +#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_10_RT_CLASS_MASK 0x00000400L +#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_11_RT_CLASS_MASK 0x00000800L +#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_12_RT_CLASS_MASK 0x00001000L +#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_13_RT_CLASS_MASK 0x00002000L +#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_14_RT_CLASS_MASK 0x00004000L +#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_15_RT_CLASS_MASK 0x00008000L +#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_16_RT_CLASS_MASK 0x00010000L +#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_17_RT_CLASS_MASK 0x00020000L +#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_18_RT_CLASS_MASK 0x00040000L +#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_19_RT_CLASS_MASK 0x00080000L +#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_20_RT_CLASS_MASK 0x00100000L +#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_21_RT_CLASS_MASK 0x00200000L +#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_22_RT_CLASS_MASK 0x00400000L +#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_23_RT_CLASS_MASK 0x00800000L +#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_24_RT_CLASS_MASK 0x01000000L +#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_25_RT_CLASS_MASK 0x02000000L +#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_26_RT_CLASS_MASK 0x04000000L +#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_27_RT_CLASS_MASK 0x08000000L +#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_28_RT_CLASS_MASK 0x10000000L +#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_29_RT_CLASS_MASK 0x20000000L +#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_30_RT_CLASS_MASK 0x40000000L +#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_31_RT_CLASS_MASK 0x80000000L +//MMVM_L2_BANK_SELECT_RESERVED_CID +#define MMVM_L2_BANK_SELECT_RESERVED_CID__RESERVED_READ_CLIENT_ID__SHIFT 0x0 +#define MMVM_L2_BANK_SELECT_RESERVED_CID__RESERVED_WRITE_CLIENT_ID__SHIFT 0xa +#define MMVM_L2_BANK_SELECT_RESERVED_CID__ENABLE__SHIFT 0x14 +#define MMVM_L2_BANK_SELECT_RESERVED_CID__RESERVED_CACHE_INVALIDATION_MODE__SHIFT 0x18 +#define MMVM_L2_BANK_SELECT_RESERVED_CID__RESERVED_CACHE_PRIVATE_INVALIDATION__SHIFT 0x19 +#define MMVM_L2_BANK_SELECT_RESERVED_CID__RESERVED_CACHE_FRAGMENT_SIZE__SHIFT 0x1a +#define MMVM_L2_BANK_SELECT_RESERVED_CID__RESERVED_READ_CLIENT_ID_MASK 0x000001FFL +#define MMVM_L2_BANK_SELECT_RESERVED_CID__RESERVED_WRITE_CLIENT_ID_MASK 0x0007FC00L +#define MMVM_L2_BANK_SELECT_RESERVED_CID__ENABLE_MASK 0x00100000L +#define MMVM_L2_BANK_SELECT_RESERVED_CID__RESERVED_CACHE_INVALIDATION_MODE_MASK 0x01000000L +#define MMVM_L2_BANK_SELECT_RESERVED_CID__RESERVED_CACHE_PRIVATE_INVALIDATION_MASK 0x02000000L +#define MMVM_L2_BANK_SELECT_RESERVED_CID__RESERVED_CACHE_FRAGMENT_SIZE_MASK 0x7C000000L +//MMVM_L2_BANK_SELECT_RESERVED_CID2 +#define MMVM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_READ_CLIENT_ID__SHIFT 0x0 +#define MMVM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_WRITE_CLIENT_ID__SHIFT 0xa +#define MMVM_L2_BANK_SELECT_RESERVED_CID2__ENABLE__SHIFT 0x14 +#define MMVM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_CACHE_INVALIDATION_MODE__SHIFT 0x18 +#define MMVM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_CACHE_PRIVATE_INVALIDATION__SHIFT 0x19 +#define MMVM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_CACHE_FRAGMENT_SIZE__SHIFT 0x1a +#define MMVM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_READ_CLIENT_ID_MASK 0x000001FFL +#define MMVM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_WRITE_CLIENT_ID_MASK 0x0007FC00L +#define MMVM_L2_BANK_SELECT_RESERVED_CID2__ENABLE_MASK 0x00100000L +#define MMVM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_CACHE_INVALIDATION_MODE_MASK 0x01000000L +#define MMVM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_CACHE_PRIVATE_INVALIDATION_MASK 0x02000000L +#define MMVM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_CACHE_FRAGMENT_SIZE_MASK 0x7C000000L +//MMVM_L2_CACHE_PARITY_CNTL +#define MMVM_L2_CACHE_PARITY_CNTL__ENABLE_PARITY_CHECKS_IN_4K_PTE_CACHES__SHIFT 0x0 +#define MMVM_L2_CACHE_PARITY_CNTL__ENABLE_PARITY_CHECKS_IN_BIGK_PTE_CACHES__SHIFT 0x1 +#define MMVM_L2_CACHE_PARITY_CNTL__ENABLE_PARITY_CHECKS_IN_PDE_CACHES__SHIFT 0x2 +#define MMVM_L2_CACHE_PARITY_CNTL__FORCE_PARITY_MISMATCH_IN_4K_PTE_CACHE__SHIFT 0x3 +#define MMVM_L2_CACHE_PARITY_CNTL__FORCE_PARITY_MISMATCH_IN_BIGK_PTE_CACHE__SHIFT 0x4 +#define MMVM_L2_CACHE_PARITY_CNTL__FORCE_PARITY_MISMATCH_IN_PDE_CACHE__SHIFT 0x5 +#define MMVM_L2_CACHE_PARITY_CNTL__FORCE_CACHE_BANK__SHIFT 0x6 +#define MMVM_L2_CACHE_PARITY_CNTL__FORCE_CACHE_NUMBER__SHIFT 0x9 +#define MMVM_L2_CACHE_PARITY_CNTL__FORCE_CACHE_ASSOC__SHIFT 0xc +#define MMVM_L2_CACHE_PARITY_CNTL__ENABLE_PARITY_CHECKS_IN_4K_PTE_CACHES_MASK 0x00000001L +#define MMVM_L2_CACHE_PARITY_CNTL__ENABLE_PARITY_CHECKS_IN_BIGK_PTE_CACHES_MASK 0x00000002L +#define MMVM_L2_CACHE_PARITY_CNTL__ENABLE_PARITY_CHECKS_IN_PDE_CACHES_MASK 0x00000004L +#define MMVM_L2_CACHE_PARITY_CNTL__FORCE_PARITY_MISMATCH_IN_4K_PTE_CACHE_MASK 0x00000008L +#define MMVM_L2_CACHE_PARITY_CNTL__FORCE_PARITY_MISMATCH_IN_BIGK_PTE_CACHE_MASK 0x00000010L +#define MMVM_L2_CACHE_PARITY_CNTL__FORCE_PARITY_MISMATCH_IN_PDE_CACHE_MASK 0x00000020L +#define MMVM_L2_CACHE_PARITY_CNTL__FORCE_CACHE_BANK_MASK 0x000001C0L +#define MMVM_L2_CACHE_PARITY_CNTL__FORCE_CACHE_NUMBER_MASK 0x00000E00L +#define MMVM_L2_CACHE_PARITY_CNTL__FORCE_CACHE_ASSOC_MASK 0x0000F000L +//MMVM_L2_CGTT_CLK_CTRL +#define MMVM_L2_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 +#define MMVM_L2_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x5 +#define MMVM_L2_CGTT_CLK_CTRL__LS_ASSERT_HYSTERESIS__SHIFT 0xd +#define MMVM_L2_CGTT_CLK_CTRL__MIN_MGLS__SHIFT 0x1a +#define MMVM_L2_CGTT_CLK_CTRL__CGLS_DISABLE__SHIFT 0x1d +#define MMVM_L2_CGTT_CLK_CTRL__LS_DISABLE__SHIFT 0x1e +#define MMVM_L2_CGTT_CLK_CTRL__BUSY_OVERRIDE__SHIFT 0x1f +#define MMVM_L2_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000001FL +#define MMVM_L2_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00001FE0L +#define MMVM_L2_CGTT_CLK_CTRL__LS_ASSERT_HYSTERESIS_MASK 0x03FFE000L +#define MMVM_L2_CGTT_CLK_CTRL__MIN_MGLS_MASK 0x1C000000L +#define MMVM_L2_CGTT_CLK_CTRL__CGLS_DISABLE_MASK 0x20000000L +#define MMVM_L2_CGTT_CLK_CTRL__LS_DISABLE_MASK 0x40000000L +#define MMVM_L2_CGTT_CLK_CTRL__BUSY_OVERRIDE_MASK 0x80000000L +//MMVM_L2_CNTL5 +#define MMVM_L2_CNTL5__L2_CACHE_SMALLK_FRAGMENT_SIZE__SHIFT 0x0 +#define MMVM_L2_CNTL5__WALKER_PRIORITY_CLIENT_ID__SHIFT 0x5 +#define MMVM_L2_CNTL5__WALKER_FETCH_PDE_REUSE_ENABLE__SHIFT 0xe +#define MMVM_L2_CNTL5__MM_CLIENT_RET_FGCG_OFF__SHIFT 0xf +#define MMVM_L2_CNTL5__UTCL2_ATC_REQ_FGCG_OFF__SHIFT 0x10 +#define MMVM_L2_CNTL5__UTCL2_ONE_OUTSTANDING_ATC_INVREQ__SHIFT 0x12 +#define MMVM_L2_CNTL5__L2_CACHE_SMALLK_FRAGMENT_SIZE_MASK 0x0000001FL +#define MMVM_L2_CNTL5__WALKER_PRIORITY_CLIENT_ID_MASK 0x00003FE0L +#define MMVM_L2_CNTL5__WALKER_FETCH_PDE_REUSE_ENABLE_MASK 0x00004000L +#define MMVM_L2_CNTL5__MM_CLIENT_RET_FGCG_OFF_MASK 0x00008000L +#define MMVM_L2_CNTL5__UTCL2_ATC_REQ_FGCG_OFF_MASK 0x00010000L +#define MMVM_L2_CNTL5__UTCL2_ONE_OUTSTANDING_ATC_INVREQ_MASK 0x00040000L +//MMVM_L2_GCR_CNTL +#define MMVM_L2_GCR_CNTL__GCR_ENABLE__SHIFT 0x0 +#define MMVM_L2_GCR_CNTL__GCR_CLIENT_ID__SHIFT 0x1 +#define MMVM_L2_GCR_CNTL__GCR_ENABLE_MASK 0x00000001L +#define MMVM_L2_GCR_CNTL__GCR_CLIENT_ID_MASK 0x000003FEL +//MMVM_L2_CGTT_BUSY_CTRL +#define MMVM_L2_CGTT_BUSY_CTRL__READ_DELAY__SHIFT 0x0 +#define MMVM_L2_CGTT_BUSY_CTRL__ALWAYS_BUSY__SHIFT 0x5 +#define MMVM_L2_CGTT_BUSY_CTRL__READ_DELAY_MASK 0x0000001FL +#define MMVM_L2_CGTT_BUSY_CTRL__ALWAYS_BUSY_MASK 0x00000020L +//MMVM_L2_PTE_CACHE_DUMP_CNTL +#define MMVM_L2_PTE_CACHE_DUMP_CNTL__ENABLE__SHIFT 0x0 +#define MMVM_L2_PTE_CACHE_DUMP_CNTL__READY__SHIFT 0x1 +#define MMVM_L2_PTE_CACHE_DUMP_CNTL__BANK__SHIFT 0x4 +#define MMVM_L2_PTE_CACHE_DUMP_CNTL__CACHE__SHIFT 0x8 +#define MMVM_L2_PTE_CACHE_DUMP_CNTL__ASSOC__SHIFT 0xc +#define MMVM_L2_PTE_CACHE_DUMP_CNTL__INDEX__SHIFT 0x10 +#define MMVM_L2_PTE_CACHE_DUMP_CNTL__ENABLE_MASK 0x00000001L +#define MMVM_L2_PTE_CACHE_DUMP_CNTL__READY_MASK 0x00000002L +#define MMVM_L2_PTE_CACHE_DUMP_CNTL__BANK_MASK 0x000000F0L +#define MMVM_L2_PTE_CACHE_DUMP_CNTL__CACHE_MASK 0x00000F00L +#define MMVM_L2_PTE_CACHE_DUMP_CNTL__ASSOC_MASK 0x0000F000L +#define MMVM_L2_PTE_CACHE_DUMP_CNTL__INDEX_MASK 0xFFFF0000L +//MMVM_L2_PTE_CACHE_DUMP_READ +#define MMVM_L2_PTE_CACHE_DUMP_READ__DATA__SHIFT 0x0 +#define MMVM_L2_PTE_CACHE_DUMP_READ__DATA_MASK 0xFFFFFFFFL +//MMVM_L2_BANK_SELECT_MASKS +#define MMVM_L2_BANK_SELECT_MASKS__MASK0__SHIFT 0x0 +#define MMVM_L2_BANK_SELECT_MASKS__MASK1__SHIFT 0x4 +#define MMVM_L2_BANK_SELECT_MASKS__MASK2__SHIFT 0x8 +#define MMVM_L2_BANK_SELECT_MASKS__MASK3__SHIFT 0xc +#define MMVM_L2_BANK_SELECT_MASKS__MASK0_MASK 0x0000000FL +#define MMVM_L2_BANK_SELECT_MASKS__MASK1_MASK 0x000000F0L +#define MMVM_L2_BANK_SELECT_MASKS__MASK2_MASK 0x00000F00L +#define MMVM_L2_BANK_SELECT_MASKS__MASK3_MASK 0x0000F000L +//MMUTCL2_CREDIT_SAFETY_GROUP_RET_CDC +#define MMUTCL2_CREDIT_SAFETY_GROUP_RET_CDC__CREDITS__SHIFT 0x0 +#define MMUTCL2_CREDIT_SAFETY_GROUP_RET_CDC__UPDATE__SHIFT 0xa +#define MMUTCL2_CREDIT_SAFETY_GROUP_RET_CDC__CREDITS_MASK 0x000003FFL +#define MMUTCL2_CREDIT_SAFETY_GROUP_RET_CDC__UPDATE_MASK 0x00000400L +//MMUTCL2_CREDIT_SAFETY_GROUP_CLIENTS_INVREQ_CDC +#define MMUTCL2_CREDIT_SAFETY_GROUP_CLIENTS_INVREQ_CDC__CREDITS__SHIFT 0x0 +#define MMUTCL2_CREDIT_SAFETY_GROUP_CLIENTS_INVREQ_CDC__UPDATE__SHIFT 0xa +#define MMUTCL2_CREDIT_SAFETY_GROUP_CLIENTS_INVREQ_CDC__CREDITS_MASK 0x000003FFL +#define MMUTCL2_CREDIT_SAFETY_GROUP_CLIENTS_INVREQ_CDC__UPDATE_MASK 0x00000400L +//MMUTCL2_CREDIT_SAFETY_GROUP_CLIENTS_INVREQ_NOCDC +#define MMUTCL2_CREDIT_SAFETY_GROUP_CLIENTS_INVREQ_NOCDC__CREDITS__SHIFT 0x0 +#define MMUTCL2_CREDIT_SAFETY_GROUP_CLIENTS_INVREQ_NOCDC__UPDATE__SHIFT 0xa +#define MMUTCL2_CREDIT_SAFETY_GROUP_CLIENTS_INVREQ_NOCDC__CREDITS_MASK 0x000003FFL +#define MMUTCL2_CREDIT_SAFETY_GROUP_CLIENTS_INVREQ_NOCDC__UPDATE_MASK 0x00000400L +//MMVML2_CREDIT_SAFETY_IH_FAULT_INTERRUPT +#define MMVML2_CREDIT_SAFETY_IH_FAULT_INTERRUPT__CREDITS__SHIFT 0x0 +#define MMVML2_CREDIT_SAFETY_IH_FAULT_INTERRUPT__UPDATE__SHIFT 0xa +#define MMVML2_CREDIT_SAFETY_IH_FAULT_INTERRUPT__CREDITS_MASK 0x000003FFL +#define MMVML2_CREDIT_SAFETY_IH_FAULT_INTERRUPT__UPDATE_MASK 0x00000400L +//MMVML2_WALKER_CREDIT_SAFETY_FETCH_RDREQ +#define MMVML2_WALKER_CREDIT_SAFETY_FETCH_RDREQ__CREDITS__SHIFT 0x0 +#define MMVML2_WALKER_CREDIT_SAFETY_FETCH_RDREQ__UPDATE__SHIFT 0xa +#define MMVML2_WALKER_CREDIT_SAFETY_FETCH_RDREQ__CREDITS_MASK 0x000003FFL +#define MMVML2_WALKER_CREDIT_SAFETY_FETCH_RDREQ__UPDATE_MASK 0x00000400L + + +// addressBlock: mmhub_mmutcl2_mmvml2prdec +//MMMC_VM_L2_PERFCOUNTER_LO +#define MMMC_VM_L2_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0 +#define MMMC_VM_L2_PERFCOUNTER_LO__COUNTER_LO_MASK 0xFFFFFFFFL +//MMMC_VM_L2_PERFCOUNTER_HI +#define MMMC_VM_L2_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0 +#define MMMC_VM_L2_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10 +#define MMMC_VM_L2_PERFCOUNTER_HI__COUNTER_HI_MASK 0x0000FFFFL +#define MMMC_VM_L2_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xFFFF0000L +//MMUTCL2_PERFCOUNTER_LO +#define MMUTCL2_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0 +#define MMUTCL2_PERFCOUNTER_LO__COUNTER_LO_MASK 0xFFFFFFFFL +//MMUTCL2_PERFCOUNTER_HI +#define MMUTCL2_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0 +#define MMUTCL2_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10 +#define MMUTCL2_PERFCOUNTER_HI__COUNTER_HI_MASK 0x0000FFFFL +#define MMUTCL2_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xFFFF0000L + + +// addressBlock: mmhub_mmutcl2_mmatcl2prdec +//MM_ATC_L2_PERFCOUNTER_LO +#define MM_ATC_L2_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0 +#define MM_ATC_L2_PERFCOUNTER_LO__COUNTER_LO_MASK 0xFFFFFFFFL +//MM_ATC_L2_PERFCOUNTER_HI +#define MM_ATC_L2_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0 +#define MM_ATC_L2_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10 +#define MM_ATC_L2_PERFCOUNTER_HI__COUNTER_HI_MASK 0x0000FFFFL +#define MM_ATC_L2_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xFFFF0000L + + +// addressBlock: mmhub_mmutcl2_mmvml2pldec +//MMMC_VM_L2_PERFCOUNTER0_CFG +#define MMMC_VM_L2_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0 +#define MMMC_VM_L2_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8 +#define MMMC_VM_L2_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18 +#define MMMC_VM_L2_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c +#define MMMC_VM_L2_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d +#define MMMC_VM_L2_PERFCOUNTER0_CFG__PERF_SEL_MASK 0x000000FFL +#define MMMC_VM_L2_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0x0000FF00L +#define MMMC_VM_L2_PERFCOUNTER0_CFG__PERF_MODE_MASK 0x0F000000L +#define MMMC_VM_L2_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000L +#define MMMC_VM_L2_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000L +//MMMC_VM_L2_PERFCOUNTER1_CFG +#define MMMC_VM_L2_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0 +#define MMMC_VM_L2_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8 +#define MMMC_VM_L2_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18 +#define MMMC_VM_L2_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c +#define MMMC_VM_L2_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d +#define MMMC_VM_L2_PERFCOUNTER1_CFG__PERF_SEL_MASK 0x000000FFL +#define MMMC_VM_L2_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0x0000FF00L +#define MMMC_VM_L2_PERFCOUNTER1_CFG__PERF_MODE_MASK 0x0F000000L +#define MMMC_VM_L2_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000L +#define MMMC_VM_L2_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000L +//MMMC_VM_L2_PERFCOUNTER2_CFG +#define MMMC_VM_L2_PERFCOUNTER2_CFG__PERF_SEL__SHIFT 0x0 +#define MMMC_VM_L2_PERFCOUNTER2_CFG__PERF_SEL_END__SHIFT 0x8 +#define MMMC_VM_L2_PERFCOUNTER2_CFG__PERF_MODE__SHIFT 0x18 +#define MMMC_VM_L2_PERFCOUNTER2_CFG__ENABLE__SHIFT 0x1c +#define MMMC_VM_L2_PERFCOUNTER2_CFG__CLEAR__SHIFT 0x1d +#define MMMC_VM_L2_PERFCOUNTER2_CFG__PERF_SEL_MASK 0x000000FFL +#define MMMC_VM_L2_PERFCOUNTER2_CFG__PERF_SEL_END_MASK 0x0000FF00L +#define MMMC_VM_L2_PERFCOUNTER2_CFG__PERF_MODE_MASK 0x0F000000L +#define MMMC_VM_L2_PERFCOUNTER2_CFG__ENABLE_MASK 0x10000000L +#define MMMC_VM_L2_PERFCOUNTER2_CFG__CLEAR_MASK 0x20000000L +//MMMC_VM_L2_PERFCOUNTER3_CFG +#define MMMC_VM_L2_PERFCOUNTER3_CFG__PERF_SEL__SHIFT 0x0 +#define MMMC_VM_L2_PERFCOUNTER3_CFG__PERF_SEL_END__SHIFT 0x8 +#define MMMC_VM_L2_PERFCOUNTER3_CFG__PERF_MODE__SHIFT 0x18 +#define MMMC_VM_L2_PERFCOUNTER3_CFG__ENABLE__SHIFT 0x1c +#define MMMC_VM_L2_PERFCOUNTER3_CFG__CLEAR__SHIFT 0x1d +#define MMMC_VM_L2_PERFCOUNTER3_CFG__PERF_SEL_MASK 0x000000FFL +#define MMMC_VM_L2_PERFCOUNTER3_CFG__PERF_SEL_END_MASK 0x0000FF00L +#define MMMC_VM_L2_PERFCOUNTER3_CFG__PERF_MODE_MASK 0x0F000000L +#define MMMC_VM_L2_PERFCOUNTER3_CFG__ENABLE_MASK 0x10000000L +#define MMMC_VM_L2_PERFCOUNTER3_CFG__CLEAR_MASK 0x20000000L +//MMMC_VM_L2_PERFCOUNTER4_CFG +#define MMMC_VM_L2_PERFCOUNTER4_CFG__PERF_SEL__SHIFT 0x0 +#define MMMC_VM_L2_PERFCOUNTER4_CFG__PERF_SEL_END__SHIFT 0x8 +#define MMMC_VM_L2_PERFCOUNTER4_CFG__PERF_MODE__SHIFT 0x18 +#define MMMC_VM_L2_PERFCOUNTER4_CFG__ENABLE__SHIFT 0x1c +#define MMMC_VM_L2_PERFCOUNTER4_CFG__CLEAR__SHIFT 0x1d +#define MMMC_VM_L2_PERFCOUNTER4_CFG__PERF_SEL_MASK 0x000000FFL +#define MMMC_VM_L2_PERFCOUNTER4_CFG__PERF_SEL_END_MASK 0x0000FF00L +#define MMMC_VM_L2_PERFCOUNTER4_CFG__PERF_MODE_MASK 0x0F000000L +#define MMMC_VM_L2_PERFCOUNTER4_CFG__ENABLE_MASK 0x10000000L +#define MMMC_VM_L2_PERFCOUNTER4_CFG__CLEAR_MASK 0x20000000L +//MMMC_VM_L2_PERFCOUNTER5_CFG +#define MMMC_VM_L2_PERFCOUNTER5_CFG__PERF_SEL__SHIFT 0x0 +#define MMMC_VM_L2_PERFCOUNTER5_CFG__PERF_SEL_END__SHIFT 0x8 +#define MMMC_VM_L2_PERFCOUNTER5_CFG__PERF_MODE__SHIFT 0x18 +#define MMMC_VM_L2_PERFCOUNTER5_CFG__ENABLE__SHIFT 0x1c +#define MMMC_VM_L2_PERFCOUNTER5_CFG__CLEAR__SHIFT 0x1d +#define MMMC_VM_L2_PERFCOUNTER5_CFG__PERF_SEL_MASK 0x000000FFL +#define MMMC_VM_L2_PERFCOUNTER5_CFG__PERF_SEL_END_MASK 0x0000FF00L +#define MMMC_VM_L2_PERFCOUNTER5_CFG__PERF_MODE_MASK 0x0F000000L +#define MMMC_VM_L2_PERFCOUNTER5_CFG__ENABLE_MASK 0x10000000L +#define MMMC_VM_L2_PERFCOUNTER5_CFG__CLEAR_MASK 0x20000000L +//MMMC_VM_L2_PERFCOUNTER6_CFG +#define MMMC_VM_L2_PERFCOUNTER6_CFG__PERF_SEL__SHIFT 0x0 +#define MMMC_VM_L2_PERFCOUNTER6_CFG__PERF_SEL_END__SHIFT 0x8 +#define MMMC_VM_L2_PERFCOUNTER6_CFG__PERF_MODE__SHIFT 0x18 +#define MMMC_VM_L2_PERFCOUNTER6_CFG__ENABLE__SHIFT 0x1c +#define MMMC_VM_L2_PERFCOUNTER6_CFG__CLEAR__SHIFT 0x1d +#define MMMC_VM_L2_PERFCOUNTER6_CFG__PERF_SEL_MASK 0x000000FFL +#define MMMC_VM_L2_PERFCOUNTER6_CFG__PERF_SEL_END_MASK 0x0000FF00L +#define MMMC_VM_L2_PERFCOUNTER6_CFG__PERF_MODE_MASK 0x0F000000L +#define MMMC_VM_L2_PERFCOUNTER6_CFG__ENABLE_MASK 0x10000000L +#define MMMC_VM_L2_PERFCOUNTER6_CFG__CLEAR_MASK 0x20000000L +//MMMC_VM_L2_PERFCOUNTER7_CFG +#define MMMC_VM_L2_PERFCOUNTER7_CFG__PERF_SEL__SHIFT 0x0 +#define MMMC_VM_L2_PERFCOUNTER7_CFG__PERF_SEL_END__SHIFT 0x8 +#define MMMC_VM_L2_PERFCOUNTER7_CFG__PERF_MODE__SHIFT 0x18 +#define MMMC_VM_L2_PERFCOUNTER7_CFG__ENABLE__SHIFT 0x1c +#define MMMC_VM_L2_PERFCOUNTER7_CFG__CLEAR__SHIFT 0x1d +#define MMMC_VM_L2_PERFCOUNTER7_CFG__PERF_SEL_MASK 0x000000FFL +#define MMMC_VM_L2_PERFCOUNTER7_CFG__PERF_SEL_END_MASK 0x0000FF00L +#define MMMC_VM_L2_PERFCOUNTER7_CFG__PERF_MODE_MASK 0x0F000000L +#define MMMC_VM_L2_PERFCOUNTER7_CFG__ENABLE_MASK 0x10000000L +#define MMMC_VM_L2_PERFCOUNTER7_CFG__CLEAR_MASK 0x20000000L +//MMMC_VM_L2_PERFCOUNTER_RSLT_CNTL +#define MMMC_VM_L2_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0 +#define MMMC_VM_L2_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8 +#define MMMC_VM_L2_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10 +#define MMMC_VM_L2_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18 +#define MMMC_VM_L2_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19 +#define MMMC_VM_L2_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a +#define MMMC_VM_L2_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0x0000000FL +#define MMMC_VM_L2_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0x0000FF00L +#define MMMC_VM_L2_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0x00FF0000L +#define MMMC_VM_L2_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x01000000L +#define MMMC_VM_L2_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x02000000L +#define MMMC_VM_L2_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x04000000L +//MMUTCL2_PERFCOUNTER0_CFG +#define MMUTCL2_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0 +#define MMUTCL2_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8 +#define MMUTCL2_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18 +#define MMUTCL2_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c +#define MMUTCL2_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d +#define MMUTCL2_PERFCOUNTER0_CFG__PERF_SEL_MASK 0x000000FFL +#define MMUTCL2_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0x0000FF00L +#define MMUTCL2_PERFCOUNTER0_CFG__PERF_MODE_MASK 0x0F000000L +#define MMUTCL2_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000L +#define MMUTCL2_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000L +//MMUTCL2_PERFCOUNTER1_CFG +#define MMUTCL2_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0 +#define MMUTCL2_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8 +#define MMUTCL2_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18 +#define MMUTCL2_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c +#define MMUTCL2_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d +#define MMUTCL2_PERFCOUNTER1_CFG__PERF_SEL_MASK 0x000000FFL +#define MMUTCL2_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0x0000FF00L +#define MMUTCL2_PERFCOUNTER1_CFG__PERF_MODE_MASK 0x0F000000L +#define MMUTCL2_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000L +#define MMUTCL2_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000L +//MMUTCL2_PERFCOUNTER2_CFG +#define MMUTCL2_PERFCOUNTER2_CFG__PERF_SEL__SHIFT 0x0 +#define MMUTCL2_PERFCOUNTER2_CFG__PERF_SEL_END__SHIFT 0x8 +#define MMUTCL2_PERFCOUNTER2_CFG__PERF_MODE__SHIFT 0x18 +#define MMUTCL2_PERFCOUNTER2_CFG__ENABLE__SHIFT 0x1c +#define MMUTCL2_PERFCOUNTER2_CFG__CLEAR__SHIFT 0x1d +#define MMUTCL2_PERFCOUNTER2_CFG__PERF_SEL_MASK 0x000000FFL +#define MMUTCL2_PERFCOUNTER2_CFG__PERF_SEL_END_MASK 0x0000FF00L +#define MMUTCL2_PERFCOUNTER2_CFG__PERF_MODE_MASK 0x0F000000L +#define MMUTCL2_PERFCOUNTER2_CFG__ENABLE_MASK 0x10000000L +#define MMUTCL2_PERFCOUNTER2_CFG__CLEAR_MASK 0x20000000L +//MMUTCL2_PERFCOUNTER3_CFG +#define MMUTCL2_PERFCOUNTER3_CFG__PERF_SEL__SHIFT 0x0 +#define MMUTCL2_PERFCOUNTER3_CFG__PERF_SEL_END__SHIFT 0x8 +#define MMUTCL2_PERFCOUNTER3_CFG__PERF_MODE__SHIFT 0x18 +#define MMUTCL2_PERFCOUNTER3_CFG__ENABLE__SHIFT 0x1c +#define MMUTCL2_PERFCOUNTER3_CFG__CLEAR__SHIFT 0x1d +#define MMUTCL2_PERFCOUNTER3_CFG__PERF_SEL_MASK 0x000000FFL +#define MMUTCL2_PERFCOUNTER3_CFG__PERF_SEL_END_MASK 0x0000FF00L +#define MMUTCL2_PERFCOUNTER3_CFG__PERF_MODE_MASK 0x0F000000L +#define MMUTCL2_PERFCOUNTER3_CFG__ENABLE_MASK 0x10000000L +#define MMUTCL2_PERFCOUNTER3_CFG__CLEAR_MASK 0x20000000L +//MMUTCL2_PERFCOUNTER_RSLT_CNTL +#define MMUTCL2_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0 +#define MMUTCL2_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8 +#define MMUTCL2_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10 +#define MMUTCL2_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18 +#define MMUTCL2_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19 +#define MMUTCL2_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a +#define MMUTCL2_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0x0000000FL +#define MMUTCL2_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0x0000FF00L +#define MMUTCL2_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0x00FF0000L +#define MMUTCL2_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x01000000L +#define MMUTCL2_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x02000000L +#define MMUTCL2_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x04000000L + + +// addressBlock: mmhub_mmutcl2_mmatcl2pldec +//MM_ATC_L2_PERFCOUNTER0_CFG +#define MM_ATC_L2_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0 +#define MM_ATC_L2_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8 +#define MM_ATC_L2_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18 +#define MM_ATC_L2_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c +#define MM_ATC_L2_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d +#define MM_ATC_L2_PERFCOUNTER0_CFG__PERF_SEL_MASK 0x000000FFL +#define MM_ATC_L2_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0x0000FF00L +#define MM_ATC_L2_PERFCOUNTER0_CFG__PERF_MODE_MASK 0x0F000000L +#define MM_ATC_L2_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000L +#define MM_ATC_L2_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000L +//MM_ATC_L2_PERFCOUNTER1_CFG +#define MM_ATC_L2_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0 +#define MM_ATC_L2_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8 +#define MM_ATC_L2_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18 +#define MM_ATC_L2_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c +#define MM_ATC_L2_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d +#define MM_ATC_L2_PERFCOUNTER1_CFG__PERF_SEL_MASK 0x000000FFL +#define MM_ATC_L2_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0x0000FF00L +#define MM_ATC_L2_PERFCOUNTER1_CFG__PERF_MODE_MASK 0x0F000000L +#define MM_ATC_L2_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000L +#define MM_ATC_L2_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000L +//MM_ATC_L2_PERFCOUNTER_RSLT_CNTL +#define MM_ATC_L2_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0 +#define MM_ATC_L2_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8 +#define MM_ATC_L2_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10 +#define MM_ATC_L2_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18 +#define MM_ATC_L2_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19 +#define MM_ATC_L2_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a +#define MM_ATC_L2_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0x0000000FL +#define MM_ATC_L2_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0x0000FF00L +#define MM_ATC_L2_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0x00FF0000L +#define MM_ATC_L2_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x01000000L +#define MM_ATC_L2_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x02000000L +#define MM_ATC_L2_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x04000000L + + +// addressBlock: mmhub_mmutcl2_mmvmsharedvcdec //MMMC_VM_FB_LOCATION_BASE #define MMMC_VM_FB_LOCATION_BASE__FB_BASE__SHIFT 0x0 #define MMMC_VM_FB_LOCATION_BASE__FB_BASE_MASK 0x00FFFFFFL +//MMMC_VM_FB_LOCATION_TOP +#define MMMC_VM_FB_LOCATION_TOP__FB_TOP__SHIFT 0x0 +#define MMMC_VM_FB_LOCATION_TOP__FB_TOP_MASK 0x00FFFFFFL +//MMMC_VM_AGP_TOP +#define MMMC_VM_AGP_TOP__AGP_TOP__SHIFT 0x0 +#define MMMC_VM_AGP_TOP__AGP_TOP_MASK 0x00FFFFFFL +//MMMC_VM_AGP_BOT +#define MMMC_VM_AGP_BOT__AGP_BOT__SHIFT 0x0 +#define MMMC_VM_AGP_BOT__AGP_BOT_MASK 0x00FFFFFFL +//MMMC_VM_AGP_BASE +#define MMMC_VM_AGP_BASE__AGP_BASE__SHIFT 0x0 +#define MMMC_VM_AGP_BASE__AGP_BASE_MASK 0x00FFFFFFL +//MMMC_VM_SYSTEM_APERTURE_LOW_ADDR +#define MMMC_VM_SYSTEM_APERTURE_LOW_ADDR__LOGICAL_ADDR__SHIFT 0x0 +#define MMMC_VM_SYSTEM_APERTURE_LOW_ADDR__LOGICAL_ADDR_MASK 0x3FFFFFFFL +//MMMC_VM_SYSTEM_APERTURE_HIGH_ADDR +#define MMMC_VM_SYSTEM_APERTURE_HIGH_ADDR__LOGICAL_ADDR__SHIFT 0x0 +#define MMMC_VM_SYSTEM_APERTURE_HIGH_ADDR__LOGICAL_ADDR_MASK 0x3FFFFFFFL +//MMMC_VM_MX_L1_TLB_CNTL +#define MMMC_VM_MX_L1_TLB_CNTL__ENABLE_L1_TLB__SHIFT 0x0 +#define MMMC_VM_MX_L1_TLB_CNTL__SYSTEM_ACCESS_MODE__SHIFT 0x3 +#define MMMC_VM_MX_L1_TLB_CNTL__SYSTEM_APERTURE_UNMAPPED_ACCESS__SHIFT 0x5 +#define MMMC_VM_MX_L1_TLB_CNTL__ENABLE_ADVANCED_DRIVER_MODEL__SHIFT 0x6 +#define MMMC_VM_MX_L1_TLB_CNTL__ECO_BITS__SHIFT 0x7 +#define MMMC_VM_MX_L1_TLB_CNTL__MTYPE__SHIFT 0xb +#define MMMC_VM_MX_L1_TLB_CNTL__ENABLE_L1_TLB_MASK 0x00000001L +#define MMMC_VM_MX_L1_TLB_CNTL__SYSTEM_ACCESS_MODE_MASK 0x00000018L +#define MMMC_VM_MX_L1_TLB_CNTL__SYSTEM_APERTURE_UNMAPPED_ACCESS_MASK 0x00000020L +#define MMMC_VM_MX_L1_TLB_CNTL__ENABLE_ADVANCED_DRIVER_MODEL_MASK 0x00000040L +#define MMMC_VM_MX_L1_TLB_CNTL__ECO_BITS_MASK 0x00000780L +#define MMMC_VM_MX_L1_TLB_CNTL__MTYPE_MASK 0x00001800L + + +// addressBlock: mmhub_mmutcl2_mmvml2vcdec +//MMVM_CONTEXT0_CNTL +#define MMVM_CONTEXT0_CNTL__ENABLE_CONTEXT__SHIFT 0x0 +#define MMVM_CONTEXT0_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 +#define MMVM_CONTEXT0_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x4 +#define MMVM_CONTEXT0_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x8 +#define MMVM_CONTEXT0_CNTL__RETRY_OTHER_FAULT__SHIFT 0x9 +#define MMVM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xa +#define MMVM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xb +#define MMVM_CONTEXT0_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xc +#define MMVM_CONTEXT0_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xd +#define MMVM_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xe +#define MMVM_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xf +#define MMVM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x10 +#define MMVM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x11 +#define MMVM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x12 +#define MMVM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x13 +#define MMVM_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x14 +#define MMVM_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x15 +#define MMVM_CONTEXT0_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x16 +#define MMVM_CONTEXT0_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x17 +#define MMVM_CONTEXT0_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x18 +#define MMVM_CONTEXT0_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x19 +#define MMVM_CONTEXT0_CNTL__ENABLE_CONTEXT_MASK 0x00000001L +#define MMVM_CONTEXT0_CNTL__PAGE_TABLE_DEPTH_MASK 0x0000000EL +#define MMVM_CONTEXT0_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x000000F0L +#define MMVM_CONTEXT0_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000100L +#define MMVM_CONTEXT0_CNTL__RETRY_OTHER_FAULT_MASK 0x00000200L +#define MMVM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000400L +#define MMVM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000800L +#define MMVM_CONTEXT0_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00001000L +#define MMVM_CONTEXT0_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00002000L +#define MMVM_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00004000L +#define MMVM_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00008000L +#define MMVM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00010000L +#define MMVM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00020000L +#define MMVM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00040000L +#define MMVM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00080000L +#define MMVM_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00100000L +#define MMVM_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00200000L +#define MMVM_CONTEXT0_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00400000L +#define MMVM_CONTEXT0_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00800000L +#define MMVM_CONTEXT0_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x01000000L +#define MMVM_CONTEXT0_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x02000000L +//MMVM_CONTEXT1_CNTL +#define MMVM_CONTEXT1_CNTL__ENABLE_CONTEXT__SHIFT 0x0 +#define MMVM_CONTEXT1_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 +#define MMVM_CONTEXT1_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x4 +#define MMVM_CONTEXT1_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x8 +#define MMVM_CONTEXT1_CNTL__RETRY_OTHER_FAULT__SHIFT 0x9 +#define MMVM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xa +#define MMVM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xb +#define MMVM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xc +#define MMVM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xd +#define MMVM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xe +#define MMVM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xf +#define MMVM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x10 +#define MMVM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x11 +#define MMVM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x12 +#define MMVM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x13 +#define MMVM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x14 +#define MMVM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x15 +#define MMVM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x16 +#define MMVM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x17 +#define MMVM_CONTEXT1_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x18 +#define MMVM_CONTEXT1_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x19 +#define MMVM_CONTEXT1_CNTL__ENABLE_CONTEXT_MASK 0x00000001L +#define MMVM_CONTEXT1_CNTL__PAGE_TABLE_DEPTH_MASK 0x0000000EL +#define MMVM_CONTEXT1_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x000000F0L +#define MMVM_CONTEXT1_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000100L +#define MMVM_CONTEXT1_CNTL__RETRY_OTHER_FAULT_MASK 0x00000200L +#define MMVM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000400L +#define MMVM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000800L +#define MMVM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00001000L +#define MMVM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00002000L +#define MMVM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00004000L +#define MMVM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00008000L +#define MMVM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00010000L +#define MMVM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00020000L +#define MMVM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00040000L +#define MMVM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00080000L +#define MMVM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00100000L +#define MMVM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00200000L +#define MMVM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00400000L +#define MMVM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00800000L +#define MMVM_CONTEXT1_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x01000000L +#define MMVM_CONTEXT1_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x02000000L +//MMVM_CONTEXT2_CNTL +#define MMVM_CONTEXT2_CNTL__ENABLE_CONTEXT__SHIFT 0x0 +#define MMVM_CONTEXT2_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 +#define MMVM_CONTEXT2_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x4 +#define MMVM_CONTEXT2_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x8 +#define MMVM_CONTEXT2_CNTL__RETRY_OTHER_FAULT__SHIFT 0x9 +#define MMVM_CONTEXT2_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xa +#define MMVM_CONTEXT2_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xb +#define MMVM_CONTEXT2_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xc +#define MMVM_CONTEXT2_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xd +#define MMVM_CONTEXT2_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xe +#define MMVM_CONTEXT2_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xf +#define MMVM_CONTEXT2_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x10 +#define MMVM_CONTEXT2_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x11 +#define MMVM_CONTEXT2_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x12 +#define MMVM_CONTEXT2_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x13 +#define MMVM_CONTEXT2_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x14 +#define MMVM_CONTEXT2_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x15 +#define MMVM_CONTEXT2_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x16 +#define MMVM_CONTEXT2_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x17 +#define MMVM_CONTEXT2_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x18 +#define MMVM_CONTEXT2_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x19 +#define MMVM_CONTEXT2_CNTL__ENABLE_CONTEXT_MASK 0x00000001L +#define MMVM_CONTEXT2_CNTL__PAGE_TABLE_DEPTH_MASK 0x0000000EL +#define MMVM_CONTEXT2_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x000000F0L +#define MMVM_CONTEXT2_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000100L +#define MMVM_CONTEXT2_CNTL__RETRY_OTHER_FAULT_MASK 0x00000200L +#define MMVM_CONTEXT2_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000400L +#define MMVM_CONTEXT2_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000800L +#define MMVM_CONTEXT2_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00001000L +#define MMVM_CONTEXT2_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00002000L +#define MMVM_CONTEXT2_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00004000L +#define MMVM_CONTEXT2_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00008000L +#define MMVM_CONTEXT2_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00010000L +#define MMVM_CONTEXT2_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00020000L +#define MMVM_CONTEXT2_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00040000L +#define MMVM_CONTEXT2_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00080000L +#define MMVM_CONTEXT2_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00100000L +#define MMVM_CONTEXT2_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00200000L +#define MMVM_CONTEXT2_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00400000L +#define MMVM_CONTEXT2_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00800000L +#define MMVM_CONTEXT2_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x01000000L +#define MMVM_CONTEXT2_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x02000000L +//MMVM_CONTEXT3_CNTL +#define MMVM_CONTEXT3_CNTL__ENABLE_CONTEXT__SHIFT 0x0 +#define MMVM_CONTEXT3_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 +#define MMVM_CONTEXT3_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x4 +#define MMVM_CONTEXT3_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x8 +#define MMVM_CONTEXT3_CNTL__RETRY_OTHER_FAULT__SHIFT 0x9 +#define MMVM_CONTEXT3_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xa +#define MMVM_CONTEXT3_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xb +#define MMVM_CONTEXT3_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xc +#define MMVM_CONTEXT3_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xd +#define MMVM_CONTEXT3_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xe +#define MMVM_CONTEXT3_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xf +#define MMVM_CONTEXT3_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x10 +#define MMVM_CONTEXT3_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x11 +#define MMVM_CONTEXT3_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x12 +#define MMVM_CONTEXT3_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x13 +#define MMVM_CONTEXT3_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x14 +#define MMVM_CONTEXT3_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x15 +#define MMVM_CONTEXT3_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x16 +#define MMVM_CONTEXT3_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x17 +#define MMVM_CONTEXT3_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x18 +#define MMVM_CONTEXT3_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x19 +#define MMVM_CONTEXT3_CNTL__ENABLE_CONTEXT_MASK 0x00000001L +#define MMVM_CONTEXT3_CNTL__PAGE_TABLE_DEPTH_MASK 0x0000000EL +#define MMVM_CONTEXT3_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x000000F0L +#define MMVM_CONTEXT3_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000100L +#define MMVM_CONTEXT3_CNTL__RETRY_OTHER_FAULT_MASK 0x00000200L +#define MMVM_CONTEXT3_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000400L +#define MMVM_CONTEXT3_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000800L +#define MMVM_CONTEXT3_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00001000L +#define MMVM_CONTEXT3_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00002000L +#define MMVM_CONTEXT3_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00004000L +#define MMVM_CONTEXT3_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00008000L +#define MMVM_CONTEXT3_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00010000L +#define MMVM_CONTEXT3_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00020000L +#define MMVM_CONTEXT3_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00040000L +#define MMVM_CONTEXT3_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00080000L +#define MMVM_CONTEXT3_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00100000L +#define MMVM_CONTEXT3_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00200000L +#define MMVM_CONTEXT3_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00400000L +#define MMVM_CONTEXT3_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00800000L +#define MMVM_CONTEXT3_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x01000000L +#define MMVM_CONTEXT3_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x02000000L +//MMVM_CONTEXT4_CNTL +#define MMVM_CONTEXT4_CNTL__ENABLE_CONTEXT__SHIFT 0x0 +#define MMVM_CONTEXT4_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 +#define MMVM_CONTEXT4_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x4 +#define MMVM_CONTEXT4_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x8 +#define MMVM_CONTEXT4_CNTL__RETRY_OTHER_FAULT__SHIFT 0x9 +#define MMVM_CONTEXT4_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xa +#define MMVM_CONTEXT4_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xb +#define MMVM_CONTEXT4_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xc +#define MMVM_CONTEXT4_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xd +#define MMVM_CONTEXT4_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xe +#define MMVM_CONTEXT4_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xf +#define MMVM_CONTEXT4_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x10 +#define MMVM_CONTEXT4_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x11 +#define MMVM_CONTEXT4_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x12 +#define MMVM_CONTEXT4_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x13 +#define MMVM_CONTEXT4_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x14 +#define MMVM_CONTEXT4_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x15 +#define MMVM_CONTEXT4_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x16 +#define MMVM_CONTEXT4_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x17 +#define MMVM_CONTEXT4_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x18 +#define MMVM_CONTEXT4_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x19 +#define MMVM_CONTEXT4_CNTL__ENABLE_CONTEXT_MASK 0x00000001L +#define MMVM_CONTEXT4_CNTL__PAGE_TABLE_DEPTH_MASK 0x0000000EL +#define MMVM_CONTEXT4_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x000000F0L +#define MMVM_CONTEXT4_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000100L +#define MMVM_CONTEXT4_CNTL__RETRY_OTHER_FAULT_MASK 0x00000200L +#define MMVM_CONTEXT4_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000400L +#define MMVM_CONTEXT4_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000800L +#define MMVM_CONTEXT4_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00001000L +#define MMVM_CONTEXT4_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00002000L +#define MMVM_CONTEXT4_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00004000L +#define MMVM_CONTEXT4_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00008000L +#define MMVM_CONTEXT4_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00010000L +#define MMVM_CONTEXT4_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00020000L +#define MMVM_CONTEXT4_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00040000L +#define MMVM_CONTEXT4_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00080000L +#define MMVM_CONTEXT4_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00100000L +#define MMVM_CONTEXT4_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00200000L +#define MMVM_CONTEXT4_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00400000L +#define MMVM_CONTEXT4_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00800000L +#define MMVM_CONTEXT4_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x01000000L +#define MMVM_CONTEXT4_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x02000000L +//MMVM_CONTEXT5_CNTL +#define MMVM_CONTEXT5_CNTL__ENABLE_CONTEXT__SHIFT 0x0 +#define MMVM_CONTEXT5_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 +#define MMVM_CONTEXT5_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x4 +#define MMVM_CONTEXT5_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x8 +#define MMVM_CONTEXT5_CNTL__RETRY_OTHER_FAULT__SHIFT 0x9 +#define MMVM_CONTEXT5_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xa +#define MMVM_CONTEXT5_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xb +#define MMVM_CONTEXT5_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xc +#define MMVM_CONTEXT5_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xd +#define MMVM_CONTEXT5_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xe +#define MMVM_CONTEXT5_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xf +#define MMVM_CONTEXT5_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x10 +#define MMVM_CONTEXT5_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x11 +#define MMVM_CONTEXT5_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x12 +#define MMVM_CONTEXT5_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x13 +#define MMVM_CONTEXT5_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x14 +#define MMVM_CONTEXT5_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x15 +#define MMVM_CONTEXT5_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x16 +#define MMVM_CONTEXT5_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x17 +#define MMVM_CONTEXT5_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x18 +#define MMVM_CONTEXT5_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x19 +#define MMVM_CONTEXT5_CNTL__ENABLE_CONTEXT_MASK 0x00000001L +#define MMVM_CONTEXT5_CNTL__PAGE_TABLE_DEPTH_MASK 0x0000000EL +#define MMVM_CONTEXT5_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x000000F0L +#define MMVM_CONTEXT5_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000100L +#define MMVM_CONTEXT5_CNTL__RETRY_OTHER_FAULT_MASK 0x00000200L +#define MMVM_CONTEXT5_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000400L +#define MMVM_CONTEXT5_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000800L +#define MMVM_CONTEXT5_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00001000L +#define MMVM_CONTEXT5_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00002000L +#define MMVM_CONTEXT5_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00004000L +#define MMVM_CONTEXT5_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00008000L +#define MMVM_CONTEXT5_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00010000L +#define MMVM_CONTEXT5_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00020000L +#define MMVM_CONTEXT5_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00040000L +#define MMVM_CONTEXT5_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00080000L +#define MMVM_CONTEXT5_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00100000L +#define MMVM_CONTEXT5_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00200000L +#define MMVM_CONTEXT5_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00400000L +#define MMVM_CONTEXT5_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00800000L +#define MMVM_CONTEXT5_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x01000000L +#define MMVM_CONTEXT5_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x02000000L +//MMVM_CONTEXT6_CNTL +#define MMVM_CONTEXT6_CNTL__ENABLE_CONTEXT__SHIFT 0x0 +#define MMVM_CONTEXT6_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 +#define MMVM_CONTEXT6_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x4 +#define MMVM_CONTEXT6_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x8 +#define MMVM_CONTEXT6_CNTL__RETRY_OTHER_FAULT__SHIFT 0x9 +#define MMVM_CONTEXT6_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xa +#define MMVM_CONTEXT6_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xb +#define MMVM_CONTEXT6_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xc +#define MMVM_CONTEXT6_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xd +#define MMVM_CONTEXT6_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xe +#define MMVM_CONTEXT6_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xf +#define MMVM_CONTEXT6_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x10 +#define MMVM_CONTEXT6_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x11 +#define MMVM_CONTEXT6_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x12 +#define MMVM_CONTEXT6_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x13 +#define MMVM_CONTEXT6_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x14 +#define MMVM_CONTEXT6_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x15 +#define MMVM_CONTEXT6_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x16 +#define MMVM_CONTEXT6_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x17 +#define MMVM_CONTEXT6_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x18 +#define MMVM_CONTEXT6_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x19 +#define MMVM_CONTEXT6_CNTL__ENABLE_CONTEXT_MASK 0x00000001L +#define MMVM_CONTEXT6_CNTL__PAGE_TABLE_DEPTH_MASK 0x0000000EL +#define MMVM_CONTEXT6_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x000000F0L +#define MMVM_CONTEXT6_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000100L +#define MMVM_CONTEXT6_CNTL__RETRY_OTHER_FAULT_MASK 0x00000200L +#define MMVM_CONTEXT6_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000400L +#define MMVM_CONTEXT6_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000800L +#define MMVM_CONTEXT6_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00001000L +#define MMVM_CONTEXT6_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00002000L +#define MMVM_CONTEXT6_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00004000L +#define MMVM_CONTEXT6_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00008000L +#define MMVM_CONTEXT6_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00010000L +#define MMVM_CONTEXT6_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00020000L +#define MMVM_CONTEXT6_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00040000L +#define MMVM_CONTEXT6_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00080000L +#define MMVM_CONTEXT6_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00100000L +#define MMVM_CONTEXT6_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00200000L +#define MMVM_CONTEXT6_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00400000L +#define MMVM_CONTEXT6_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00800000L +#define MMVM_CONTEXT6_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x01000000L +#define MMVM_CONTEXT6_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x02000000L +//MMVM_CONTEXT7_CNTL +#define MMVM_CONTEXT7_CNTL__ENABLE_CONTEXT__SHIFT 0x0 +#define MMVM_CONTEXT7_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 +#define MMVM_CONTEXT7_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x4 +#define MMVM_CONTEXT7_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x8 +#define MMVM_CONTEXT7_CNTL__RETRY_OTHER_FAULT__SHIFT 0x9 +#define MMVM_CONTEXT7_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xa +#define MMVM_CONTEXT7_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xb +#define MMVM_CONTEXT7_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xc +#define MMVM_CONTEXT7_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xd +#define MMVM_CONTEXT7_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xe +#define MMVM_CONTEXT7_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xf +#define MMVM_CONTEXT7_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x10 +#define MMVM_CONTEXT7_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x11 +#define MMVM_CONTEXT7_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x12 +#define MMVM_CONTEXT7_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x13 +#define MMVM_CONTEXT7_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x14 +#define MMVM_CONTEXT7_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x15 +#define MMVM_CONTEXT7_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x16 +#define MMVM_CONTEXT7_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x17 +#define MMVM_CONTEXT7_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x18 +#define MMVM_CONTEXT7_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x19 +#define MMVM_CONTEXT7_CNTL__ENABLE_CONTEXT_MASK 0x00000001L +#define MMVM_CONTEXT7_CNTL__PAGE_TABLE_DEPTH_MASK 0x0000000EL +#define MMVM_CONTEXT7_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x000000F0L +#define MMVM_CONTEXT7_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000100L +#define MMVM_CONTEXT7_CNTL__RETRY_OTHER_FAULT_MASK 0x00000200L +#define MMVM_CONTEXT7_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000400L +#define MMVM_CONTEXT7_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000800L +#define MMVM_CONTEXT7_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00001000L +#define MMVM_CONTEXT7_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00002000L +#define MMVM_CONTEXT7_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00004000L +#define MMVM_CONTEXT7_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00008000L +#define MMVM_CONTEXT7_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00010000L +#define MMVM_CONTEXT7_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00020000L +#define MMVM_CONTEXT7_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00040000L +#define MMVM_CONTEXT7_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00080000L +#define MMVM_CONTEXT7_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00100000L +#define MMVM_CONTEXT7_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00200000L +#define MMVM_CONTEXT7_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00400000L +#define MMVM_CONTEXT7_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00800000L +#define MMVM_CONTEXT7_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x01000000L +#define MMVM_CONTEXT7_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x02000000L +//MMVM_CONTEXT8_CNTL +#define MMVM_CONTEXT8_CNTL__ENABLE_CONTEXT__SHIFT 0x0 +#define MMVM_CONTEXT8_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 +#define MMVM_CONTEXT8_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x4 +#define MMVM_CONTEXT8_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x8 +#define MMVM_CONTEXT8_CNTL__RETRY_OTHER_FAULT__SHIFT 0x9 +#define MMVM_CONTEXT8_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xa +#define MMVM_CONTEXT8_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xb +#define MMVM_CONTEXT8_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xc +#define MMVM_CONTEXT8_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xd +#define MMVM_CONTEXT8_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xe +#define MMVM_CONTEXT8_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xf +#define MMVM_CONTEXT8_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x10 +#define MMVM_CONTEXT8_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x11 +#define MMVM_CONTEXT8_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x12 +#define MMVM_CONTEXT8_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x13 +#define MMVM_CONTEXT8_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x14 +#define MMVM_CONTEXT8_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x15 +#define MMVM_CONTEXT8_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x16 +#define MMVM_CONTEXT8_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x17 +#define MMVM_CONTEXT8_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x18 +#define MMVM_CONTEXT8_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x19 +#define MMVM_CONTEXT8_CNTL__ENABLE_CONTEXT_MASK 0x00000001L +#define MMVM_CONTEXT8_CNTL__PAGE_TABLE_DEPTH_MASK 0x0000000EL +#define MMVM_CONTEXT8_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x000000F0L +#define MMVM_CONTEXT8_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000100L +#define MMVM_CONTEXT8_CNTL__RETRY_OTHER_FAULT_MASK 0x00000200L +#define MMVM_CONTEXT8_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000400L +#define MMVM_CONTEXT8_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000800L +#define MMVM_CONTEXT8_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00001000L +#define MMVM_CONTEXT8_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00002000L +#define MMVM_CONTEXT8_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00004000L +#define MMVM_CONTEXT8_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00008000L +#define MMVM_CONTEXT8_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00010000L +#define MMVM_CONTEXT8_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00020000L +#define MMVM_CONTEXT8_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00040000L +#define MMVM_CONTEXT8_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00080000L +#define MMVM_CONTEXT8_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00100000L +#define MMVM_CONTEXT8_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00200000L +#define MMVM_CONTEXT8_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00400000L +#define MMVM_CONTEXT8_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00800000L +#define MMVM_CONTEXT8_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x01000000L +#define MMVM_CONTEXT8_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x02000000L +//MMVM_CONTEXT9_CNTL +#define MMVM_CONTEXT9_CNTL__ENABLE_CONTEXT__SHIFT 0x0 +#define MMVM_CONTEXT9_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 +#define MMVM_CONTEXT9_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x4 +#define MMVM_CONTEXT9_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x8 +#define MMVM_CONTEXT9_CNTL__RETRY_OTHER_FAULT__SHIFT 0x9 +#define MMVM_CONTEXT9_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xa +#define MMVM_CONTEXT9_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xb +#define MMVM_CONTEXT9_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xc +#define MMVM_CONTEXT9_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xd +#define MMVM_CONTEXT9_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xe +#define MMVM_CONTEXT9_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xf +#define MMVM_CONTEXT9_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x10 +#define MMVM_CONTEXT9_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x11 +#define MMVM_CONTEXT9_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x12 +#define MMVM_CONTEXT9_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x13 +#define MMVM_CONTEXT9_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x14 +#define MMVM_CONTEXT9_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x15 +#define MMVM_CONTEXT9_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x16 +#define MMVM_CONTEXT9_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x17 +#define MMVM_CONTEXT9_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x18 +#define MMVM_CONTEXT9_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x19 +#define MMVM_CONTEXT9_CNTL__ENABLE_CONTEXT_MASK 0x00000001L +#define MMVM_CONTEXT9_CNTL__PAGE_TABLE_DEPTH_MASK 0x0000000EL +#define MMVM_CONTEXT9_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x000000F0L +#define MMVM_CONTEXT9_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000100L +#define MMVM_CONTEXT9_CNTL__RETRY_OTHER_FAULT_MASK 0x00000200L +#define MMVM_CONTEXT9_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000400L +#define MMVM_CONTEXT9_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000800L +#define MMVM_CONTEXT9_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00001000L +#define MMVM_CONTEXT9_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00002000L +#define MMVM_CONTEXT9_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00004000L +#define MMVM_CONTEXT9_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00008000L +#define MMVM_CONTEXT9_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00010000L +#define MMVM_CONTEXT9_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00020000L +#define MMVM_CONTEXT9_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00040000L +#define MMVM_CONTEXT9_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00080000L +#define MMVM_CONTEXT9_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00100000L +#define MMVM_CONTEXT9_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00200000L +#define MMVM_CONTEXT9_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00400000L +#define MMVM_CONTEXT9_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00800000L +#define MMVM_CONTEXT9_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x01000000L +#define MMVM_CONTEXT9_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x02000000L +//MMVM_CONTEXT10_CNTL +#define MMVM_CONTEXT10_CNTL__ENABLE_CONTEXT__SHIFT 0x0 +#define MMVM_CONTEXT10_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 +#define MMVM_CONTEXT10_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x4 +#define MMVM_CONTEXT10_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x8 +#define MMVM_CONTEXT10_CNTL__RETRY_OTHER_FAULT__SHIFT 0x9 +#define MMVM_CONTEXT10_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xa +#define MMVM_CONTEXT10_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xb +#define MMVM_CONTEXT10_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xc +#define MMVM_CONTEXT10_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xd +#define MMVM_CONTEXT10_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xe +#define MMVM_CONTEXT10_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xf +#define MMVM_CONTEXT10_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x10 +#define MMVM_CONTEXT10_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x11 +#define MMVM_CONTEXT10_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x12 +#define MMVM_CONTEXT10_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x13 +#define MMVM_CONTEXT10_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x14 +#define MMVM_CONTEXT10_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x15 +#define MMVM_CONTEXT10_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x16 +#define MMVM_CONTEXT10_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x17 +#define MMVM_CONTEXT10_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x18 +#define MMVM_CONTEXT10_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x19 +#define MMVM_CONTEXT10_CNTL__ENABLE_CONTEXT_MASK 0x00000001L +#define MMVM_CONTEXT10_CNTL__PAGE_TABLE_DEPTH_MASK 0x0000000EL +#define MMVM_CONTEXT10_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x000000F0L +#define MMVM_CONTEXT10_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000100L +#define MMVM_CONTEXT10_CNTL__RETRY_OTHER_FAULT_MASK 0x00000200L +#define MMVM_CONTEXT10_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000400L +#define MMVM_CONTEXT10_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000800L +#define MMVM_CONTEXT10_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00001000L +#define MMVM_CONTEXT10_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00002000L +#define MMVM_CONTEXT10_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00004000L +#define MMVM_CONTEXT10_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00008000L +#define MMVM_CONTEXT10_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00010000L +#define MMVM_CONTEXT10_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00020000L +#define MMVM_CONTEXT10_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00040000L +#define MMVM_CONTEXT10_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00080000L +#define MMVM_CONTEXT10_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00100000L +#define MMVM_CONTEXT10_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00200000L +#define MMVM_CONTEXT10_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00400000L +#define MMVM_CONTEXT10_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00800000L +#define MMVM_CONTEXT10_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x01000000L +#define MMVM_CONTEXT10_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x02000000L +//MMVM_CONTEXT11_CNTL +#define MMVM_CONTEXT11_CNTL__ENABLE_CONTEXT__SHIFT 0x0 +#define MMVM_CONTEXT11_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 +#define MMVM_CONTEXT11_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x4 +#define MMVM_CONTEXT11_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x8 +#define MMVM_CONTEXT11_CNTL__RETRY_OTHER_FAULT__SHIFT 0x9 +#define MMVM_CONTEXT11_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xa +#define MMVM_CONTEXT11_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xb +#define MMVM_CONTEXT11_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xc +#define MMVM_CONTEXT11_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xd +#define MMVM_CONTEXT11_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xe +#define MMVM_CONTEXT11_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xf +#define MMVM_CONTEXT11_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x10 +#define MMVM_CONTEXT11_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x11 +#define MMVM_CONTEXT11_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x12 +#define MMVM_CONTEXT11_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x13 +#define MMVM_CONTEXT11_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x14 +#define MMVM_CONTEXT11_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x15 +#define MMVM_CONTEXT11_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x16 +#define MMVM_CONTEXT11_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x17 +#define MMVM_CONTEXT11_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x18 +#define MMVM_CONTEXT11_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x19 +#define MMVM_CONTEXT11_CNTL__ENABLE_CONTEXT_MASK 0x00000001L +#define MMVM_CONTEXT11_CNTL__PAGE_TABLE_DEPTH_MASK 0x0000000EL +#define MMVM_CONTEXT11_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x000000F0L +#define MMVM_CONTEXT11_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000100L +#define MMVM_CONTEXT11_CNTL__RETRY_OTHER_FAULT_MASK 0x00000200L +#define MMVM_CONTEXT11_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000400L +#define MMVM_CONTEXT11_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000800L +#define MMVM_CONTEXT11_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00001000L +#define MMVM_CONTEXT11_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00002000L +#define MMVM_CONTEXT11_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00004000L +#define MMVM_CONTEXT11_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00008000L +#define MMVM_CONTEXT11_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00010000L +#define MMVM_CONTEXT11_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00020000L +#define MMVM_CONTEXT11_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00040000L +#define MMVM_CONTEXT11_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00080000L +#define MMVM_CONTEXT11_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00100000L +#define MMVM_CONTEXT11_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00200000L +#define MMVM_CONTEXT11_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00400000L +#define MMVM_CONTEXT11_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00800000L +#define MMVM_CONTEXT11_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x01000000L +#define MMVM_CONTEXT11_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x02000000L +//MMVM_CONTEXT12_CNTL +#define MMVM_CONTEXT12_CNTL__ENABLE_CONTEXT__SHIFT 0x0 +#define MMVM_CONTEXT12_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 +#define MMVM_CONTEXT12_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x4 +#define MMVM_CONTEXT12_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x8 +#define MMVM_CONTEXT12_CNTL__RETRY_OTHER_FAULT__SHIFT 0x9 +#define MMVM_CONTEXT12_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xa +#define MMVM_CONTEXT12_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xb +#define MMVM_CONTEXT12_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xc +#define MMVM_CONTEXT12_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xd +#define MMVM_CONTEXT12_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xe +#define MMVM_CONTEXT12_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xf +#define MMVM_CONTEXT12_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x10 +#define MMVM_CONTEXT12_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x11 +#define MMVM_CONTEXT12_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x12 +#define MMVM_CONTEXT12_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x13 +#define MMVM_CONTEXT12_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x14 +#define MMVM_CONTEXT12_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x15 +#define MMVM_CONTEXT12_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x16 +#define MMVM_CONTEXT12_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x17 +#define MMVM_CONTEXT12_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x18 +#define MMVM_CONTEXT12_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x19 +#define MMVM_CONTEXT12_CNTL__ENABLE_CONTEXT_MASK 0x00000001L +#define MMVM_CONTEXT12_CNTL__PAGE_TABLE_DEPTH_MASK 0x0000000EL +#define MMVM_CONTEXT12_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x000000F0L +#define MMVM_CONTEXT12_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000100L +#define MMVM_CONTEXT12_CNTL__RETRY_OTHER_FAULT_MASK 0x00000200L +#define MMVM_CONTEXT12_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000400L +#define MMVM_CONTEXT12_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000800L +#define MMVM_CONTEXT12_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00001000L +#define MMVM_CONTEXT12_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00002000L +#define MMVM_CONTEXT12_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00004000L +#define MMVM_CONTEXT12_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00008000L +#define MMVM_CONTEXT12_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00010000L +#define MMVM_CONTEXT12_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00020000L +#define MMVM_CONTEXT12_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00040000L +#define MMVM_CONTEXT12_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00080000L +#define MMVM_CONTEXT12_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00100000L +#define MMVM_CONTEXT12_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00200000L +#define MMVM_CONTEXT12_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00400000L +#define MMVM_CONTEXT12_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00800000L +#define MMVM_CONTEXT12_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x01000000L +#define MMVM_CONTEXT12_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x02000000L +//MMVM_CONTEXT13_CNTL +#define MMVM_CONTEXT13_CNTL__ENABLE_CONTEXT__SHIFT 0x0 +#define MMVM_CONTEXT13_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 +#define MMVM_CONTEXT13_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x4 +#define MMVM_CONTEXT13_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x8 +#define MMVM_CONTEXT13_CNTL__RETRY_OTHER_FAULT__SHIFT 0x9 +#define MMVM_CONTEXT13_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xa +#define MMVM_CONTEXT13_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xb +#define MMVM_CONTEXT13_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xc +#define MMVM_CONTEXT13_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xd +#define MMVM_CONTEXT13_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xe +#define MMVM_CONTEXT13_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xf +#define MMVM_CONTEXT13_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x10 +#define MMVM_CONTEXT13_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x11 +#define MMVM_CONTEXT13_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x12 +#define MMVM_CONTEXT13_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x13 +#define MMVM_CONTEXT13_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x14 +#define MMVM_CONTEXT13_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x15 +#define MMVM_CONTEXT13_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x16 +#define MMVM_CONTEXT13_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x17 +#define MMVM_CONTEXT13_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x18 +#define MMVM_CONTEXT13_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x19 +#define MMVM_CONTEXT13_CNTL__ENABLE_CONTEXT_MASK 0x00000001L +#define MMVM_CONTEXT13_CNTL__PAGE_TABLE_DEPTH_MASK 0x0000000EL +#define MMVM_CONTEXT13_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x000000F0L +#define MMVM_CONTEXT13_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000100L +#define MMVM_CONTEXT13_CNTL__RETRY_OTHER_FAULT_MASK 0x00000200L +#define MMVM_CONTEXT13_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000400L +#define MMVM_CONTEXT13_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000800L +#define MMVM_CONTEXT13_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00001000L +#define MMVM_CONTEXT13_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00002000L +#define MMVM_CONTEXT13_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00004000L +#define MMVM_CONTEXT13_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00008000L +#define MMVM_CONTEXT13_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00010000L +#define MMVM_CONTEXT13_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00020000L +#define MMVM_CONTEXT13_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00040000L +#define MMVM_CONTEXT13_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00080000L +#define MMVM_CONTEXT13_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00100000L +#define MMVM_CONTEXT13_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00200000L +#define MMVM_CONTEXT13_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00400000L +#define MMVM_CONTEXT13_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00800000L +#define MMVM_CONTEXT13_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x01000000L +#define MMVM_CONTEXT13_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x02000000L +//MMVM_CONTEXT14_CNTL +#define MMVM_CONTEXT14_CNTL__ENABLE_CONTEXT__SHIFT 0x0 +#define MMVM_CONTEXT14_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 +#define MMVM_CONTEXT14_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x4 +#define MMVM_CONTEXT14_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x8 +#define MMVM_CONTEXT14_CNTL__RETRY_OTHER_FAULT__SHIFT 0x9 +#define MMVM_CONTEXT14_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xa +#define MMVM_CONTEXT14_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xb +#define MMVM_CONTEXT14_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xc +#define MMVM_CONTEXT14_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xd +#define MMVM_CONTEXT14_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xe +#define MMVM_CONTEXT14_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xf +#define MMVM_CONTEXT14_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x10 +#define MMVM_CONTEXT14_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x11 +#define MMVM_CONTEXT14_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x12 +#define MMVM_CONTEXT14_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x13 +#define MMVM_CONTEXT14_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x14 +#define MMVM_CONTEXT14_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x15 +#define MMVM_CONTEXT14_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x16 +#define MMVM_CONTEXT14_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x17 +#define MMVM_CONTEXT14_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x18 +#define MMVM_CONTEXT14_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x19 +#define MMVM_CONTEXT14_CNTL__ENABLE_CONTEXT_MASK 0x00000001L +#define MMVM_CONTEXT14_CNTL__PAGE_TABLE_DEPTH_MASK 0x0000000EL +#define MMVM_CONTEXT14_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x000000F0L +#define MMVM_CONTEXT14_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000100L +#define MMVM_CONTEXT14_CNTL__RETRY_OTHER_FAULT_MASK 0x00000200L +#define MMVM_CONTEXT14_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000400L +#define MMVM_CONTEXT14_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000800L +#define MMVM_CONTEXT14_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00001000L +#define MMVM_CONTEXT14_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00002000L +#define MMVM_CONTEXT14_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00004000L +#define MMVM_CONTEXT14_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00008000L +#define MMVM_CONTEXT14_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00010000L +#define MMVM_CONTEXT14_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00020000L +#define MMVM_CONTEXT14_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00040000L +#define MMVM_CONTEXT14_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00080000L +#define MMVM_CONTEXT14_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00100000L +#define MMVM_CONTEXT14_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00200000L +#define MMVM_CONTEXT14_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00400000L +#define MMVM_CONTEXT14_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00800000L +#define MMVM_CONTEXT14_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x01000000L +#define MMVM_CONTEXT14_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x02000000L +//MMVM_CONTEXT15_CNTL +#define MMVM_CONTEXT15_CNTL__ENABLE_CONTEXT__SHIFT 0x0 +#define MMVM_CONTEXT15_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 +#define MMVM_CONTEXT15_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x4 +#define MMVM_CONTEXT15_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x8 +#define MMVM_CONTEXT15_CNTL__RETRY_OTHER_FAULT__SHIFT 0x9 +#define MMVM_CONTEXT15_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xa +#define MMVM_CONTEXT15_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xb +#define MMVM_CONTEXT15_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xc +#define MMVM_CONTEXT15_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xd +#define MMVM_CONTEXT15_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xe +#define MMVM_CONTEXT15_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xf +#define MMVM_CONTEXT15_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x10 +#define MMVM_CONTEXT15_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x11 +#define MMVM_CONTEXT15_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x12 +#define MMVM_CONTEXT15_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x13 +#define MMVM_CONTEXT15_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x14 +#define MMVM_CONTEXT15_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x15 +#define MMVM_CONTEXT15_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x16 +#define MMVM_CONTEXT15_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x17 +#define MMVM_CONTEXT15_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x18 +#define MMVM_CONTEXT15_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x19 +#define MMVM_CONTEXT15_CNTL__ENABLE_CONTEXT_MASK 0x00000001L +#define MMVM_CONTEXT15_CNTL__PAGE_TABLE_DEPTH_MASK 0x0000000EL +#define MMVM_CONTEXT15_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x000000F0L +#define MMVM_CONTEXT15_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000100L +#define MMVM_CONTEXT15_CNTL__RETRY_OTHER_FAULT_MASK 0x00000200L +#define MMVM_CONTEXT15_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000400L +#define MMVM_CONTEXT15_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000800L +#define MMVM_CONTEXT15_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00001000L +#define MMVM_CONTEXT15_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00002000L +#define MMVM_CONTEXT15_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00004000L +#define MMVM_CONTEXT15_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00008000L +#define MMVM_CONTEXT15_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00010000L +#define MMVM_CONTEXT15_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00020000L +#define MMVM_CONTEXT15_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00040000L +#define MMVM_CONTEXT15_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00080000L +#define MMVM_CONTEXT15_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00100000L +#define MMVM_CONTEXT15_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00200000L +#define MMVM_CONTEXT15_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00400000L +#define MMVM_CONTEXT15_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00800000L +#define MMVM_CONTEXT15_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x01000000L +#define MMVM_CONTEXT15_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x02000000L +//MMVM_CONTEXTS_DISABLE +#define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_0__SHIFT 0x0 +#define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_1__SHIFT 0x1 +#define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_2__SHIFT 0x2 +#define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_3__SHIFT 0x3 +#define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_4__SHIFT 0x4 +#define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_5__SHIFT 0x5 +#define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_6__SHIFT 0x6 +#define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_7__SHIFT 0x7 +#define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_8__SHIFT 0x8 +#define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_9__SHIFT 0x9 +#define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_10__SHIFT 0xa +#define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_11__SHIFT 0xb +#define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_12__SHIFT 0xc +#define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_13__SHIFT 0xd +#define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_14__SHIFT 0xe +#define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_15__SHIFT 0xf +#define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_0_MASK 0x00000001L +#define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_1_MASK 0x00000002L +#define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_2_MASK 0x00000004L +#define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_3_MASK 0x00000008L +#define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_4_MASK 0x00000010L +#define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_5_MASK 0x00000020L +#define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_6_MASK 0x00000040L +#define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_7_MASK 0x00000080L +#define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_8_MASK 0x00000100L +#define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_9_MASK 0x00000200L +#define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_10_MASK 0x00000400L +#define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_11_MASK 0x00000800L +#define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_12_MASK 0x00001000L +#define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_13_MASK 0x00002000L +#define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_14_MASK 0x00004000L +#define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_15_MASK 0x00008000L +//MMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32 +#define MMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 +#define MMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL +//MMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32 +#define MMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 +#define MMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL +//MMVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32 +#define MMVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 +#define MMVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL +//MMVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32 +#define MMVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 +#define MMVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL +//MMVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32 +#define MMVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 +#define MMVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL +//MMVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32 +#define MMVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 +#define MMVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL +//MMVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32 +#define MMVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 +#define MMVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL +//MMVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32 +#define MMVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 +#define MMVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL +//MMVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32 +#define MMVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 +#define MMVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL +//MMVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32 +#define MMVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 +#define MMVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL +//MMVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32 +#define MMVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 +#define MMVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL +//MMVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32 +#define MMVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 +#define MMVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL +//MMVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32 +#define MMVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 +#define MMVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL +//MMVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32 +#define MMVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 +#define MMVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL +//MMVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32 +#define MMVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 +#define MMVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL +//MMVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32 +#define MMVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 +#define MMVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL +//MMVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32 +#define MMVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 +#define MMVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL +//MMVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32 +#define MMVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 +#define MMVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL +//MMVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32 +#define MMVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 +#define MMVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL +//MMVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32 +#define MMVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 +#define MMVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL +//MMVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32 +#define MMVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 +#define MMVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL +//MMVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32 +#define MMVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 +#define MMVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL +//MMVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32 +#define MMVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 +#define MMVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL +//MMVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32 +#define MMVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 +#define MMVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL +//MMVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32 +#define MMVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 +#define MMVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL +//MMVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32 +#define MMVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 +#define MMVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL +//MMVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32 +#define MMVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 +#define MMVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL +//MMVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32 +#define MMVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 +#define MMVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL +//MMVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32 +#define MMVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 +#define MMVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL +//MMVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32 +#define MMVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 +#define MMVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL +//MMVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32 +#define MMVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 +#define MMVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL +//MMVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32 +#define MMVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 +#define MMVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL +//MMVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32 +#define MMVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define MMVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//MMVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32 +#define MMVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define MMVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//MMVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32 +#define MMVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define MMVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//MMVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32 +#define MMVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define MMVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//MMVM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32 +#define MMVM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define MMVM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//MMVM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32 +#define MMVM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define MMVM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//MMVM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32 +#define MMVM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define MMVM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//MMVM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32 +#define MMVM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define MMVM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//MMVM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32 +#define MMVM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define MMVM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//MMVM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32 +#define MMVM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define MMVM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//MMVM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32 +#define MMVM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define MMVM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//MMVM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32 +#define MMVM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define MMVM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//MMVM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32 +#define MMVM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define MMVM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//MMVM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32 +#define MMVM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define MMVM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//MMVM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32 +#define MMVM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define MMVM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//MMVM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32 +#define MMVM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define MMVM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//MMVM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32 +#define MMVM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define MMVM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//MMVM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32 +#define MMVM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define MMVM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//MMVM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32 +#define MMVM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define MMVM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//MMVM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32 +#define MMVM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define MMVM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//MMVM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32 +#define MMVM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define MMVM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//MMVM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32 +#define MMVM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define MMVM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//MMVM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32 +#define MMVM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define MMVM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//MMVM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32 +#define MMVM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define MMVM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//MMVM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32 +#define MMVM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define MMVM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//MMVM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32 +#define MMVM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define MMVM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//MMVM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32 +#define MMVM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define MMVM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//MMVM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32 +#define MMVM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define MMVM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//MMVM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32 +#define MMVM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define MMVM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//MMVM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32 +#define MMVM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define MMVM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//MMVM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32 +#define MMVM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define MMVM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//MMVM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32 +#define MMVM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define MMVM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//MMVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32 +#define MMVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define MMVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//MMVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32 +#define MMVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define MMVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//MMVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32 +#define MMVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define MMVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//MMVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32 +#define MMVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define MMVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//MMVM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32 +#define MMVM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define MMVM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//MMVM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32 +#define MMVM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define MMVM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//MMVM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32 +#define MMVM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define MMVM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//MMVM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32 +#define MMVM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define MMVM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//MMVM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32 +#define MMVM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define MMVM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//MMVM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32 +#define MMVM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define MMVM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//MMVM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32 +#define MMVM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define MMVM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//MMVM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32 +#define MMVM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define MMVM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//MMVM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32 +#define MMVM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define MMVM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//MMVM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32 +#define MMVM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define MMVM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//MMVM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32 +#define MMVM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define MMVM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//MMVM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32 +#define MMVM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define MMVM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//MMVM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32 +#define MMVM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define MMVM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//MMVM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32 +#define MMVM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define MMVM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//MMVM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32 +#define MMVM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define MMVM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//MMVM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32 +#define MMVM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define MMVM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//MMVM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32 +#define MMVM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define MMVM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//MMVM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32 +#define MMVM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define MMVM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//MMVM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32 +#define MMVM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define MMVM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//MMVM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32 +#define MMVM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define MMVM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//MMVM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32 +#define MMVM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define MMVM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//MMVM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32 +#define MMVM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define MMVM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//MMVM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32 +#define MMVM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define MMVM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//MMVM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32 +#define MMVM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define MMVM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//MMVM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32 +#define MMVM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define MMVM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//MMVM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32 +#define MMVM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define MMVM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//MMVM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32 +#define MMVM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define MMVM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//MMVM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32 +#define MMVM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define MMVM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//MMVM_L2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES +#define MMVM_L2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE__SHIFT 0x0 +#define MMVM_L2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT 0x5 +#define MMVM_L2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT__SHIFT 0xa +#define MMVM_L2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE_MASK 0x0000001FL +#define MMVM_L2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK 0x000003E0L +#define MMVM_L2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT_MASK 0x0000FC00L +//MMVM_L2_CONTEXT0_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES +#define MMVM_L2_CONTEXT0_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE__SHIFT 0x0 +#define MMVM_L2_CONTEXT0_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT 0x5 +#define MMVM_L2_CONTEXT0_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT__SHIFT 0xa +#define MMVM_L2_CONTEXT0_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE_MASK 0x0000001FL +#define MMVM_L2_CONTEXT0_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK 0x000003E0L +#define MMVM_L2_CONTEXT0_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT_MASK 0x0000FC00L +//MMVM_L2_CONTEXT1_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES +#define MMVM_L2_CONTEXT1_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE__SHIFT 0x0 +#define MMVM_L2_CONTEXT1_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT 0x5 +#define MMVM_L2_CONTEXT1_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT__SHIFT 0xa +#define MMVM_L2_CONTEXT1_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE_MASK 0x0000001FL +#define MMVM_L2_CONTEXT1_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK 0x000003E0L +#define MMVM_L2_CONTEXT1_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT_MASK 0x0000FC00L +//MMVM_L2_CONTEXT2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES +#define MMVM_L2_CONTEXT2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE__SHIFT 0x0 +#define MMVM_L2_CONTEXT2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT 0x5 +#define MMVM_L2_CONTEXT2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT__SHIFT 0xa +#define MMVM_L2_CONTEXT2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE_MASK 0x0000001FL +#define MMVM_L2_CONTEXT2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK 0x000003E0L +#define MMVM_L2_CONTEXT2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT_MASK 0x0000FC00L +//MMVM_L2_CONTEXT3_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES +#define MMVM_L2_CONTEXT3_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE__SHIFT 0x0 +#define MMVM_L2_CONTEXT3_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT 0x5 +#define MMVM_L2_CONTEXT3_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT__SHIFT 0xa +#define MMVM_L2_CONTEXT3_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE_MASK 0x0000001FL +#define MMVM_L2_CONTEXT3_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK 0x000003E0L +#define MMVM_L2_CONTEXT3_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT_MASK 0x0000FC00L +//MMVM_L2_CONTEXT4_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES +#define MMVM_L2_CONTEXT4_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE__SHIFT 0x0 +#define MMVM_L2_CONTEXT4_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT 0x5 +#define MMVM_L2_CONTEXT4_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT__SHIFT 0xa +#define MMVM_L2_CONTEXT4_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE_MASK 0x0000001FL +#define MMVM_L2_CONTEXT4_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK 0x000003E0L +#define MMVM_L2_CONTEXT4_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT_MASK 0x0000FC00L +//MMVM_L2_CONTEXT5_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES +#define MMVM_L2_CONTEXT5_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE__SHIFT 0x0 +#define MMVM_L2_CONTEXT5_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT 0x5 +#define MMVM_L2_CONTEXT5_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT__SHIFT 0xa +#define MMVM_L2_CONTEXT5_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE_MASK 0x0000001FL +#define MMVM_L2_CONTEXT5_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK 0x000003E0L +#define MMVM_L2_CONTEXT5_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT_MASK 0x0000FC00L +//MMVM_L2_CONTEXT6_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES +#define MMVM_L2_CONTEXT6_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE__SHIFT 0x0 +#define MMVM_L2_CONTEXT6_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT 0x5 +#define MMVM_L2_CONTEXT6_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT__SHIFT 0xa +#define MMVM_L2_CONTEXT6_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE_MASK 0x0000001FL +#define MMVM_L2_CONTEXT6_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK 0x000003E0L +#define MMVM_L2_CONTEXT6_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT_MASK 0x0000FC00L +//MMVM_L2_CONTEXT7_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES +#define MMVM_L2_CONTEXT7_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE__SHIFT 0x0 +#define MMVM_L2_CONTEXT7_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT 0x5 +#define MMVM_L2_CONTEXT7_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT__SHIFT 0xa +#define MMVM_L2_CONTEXT7_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE_MASK 0x0000001FL +#define MMVM_L2_CONTEXT7_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK 0x000003E0L +#define MMVM_L2_CONTEXT7_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT_MASK 0x0000FC00L +//MMVM_L2_CONTEXT8_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES +#define MMVM_L2_CONTEXT8_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE__SHIFT 0x0 +#define MMVM_L2_CONTEXT8_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT 0x5 +#define MMVM_L2_CONTEXT8_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT__SHIFT 0xa +#define MMVM_L2_CONTEXT8_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE_MASK 0x0000001FL +#define MMVM_L2_CONTEXT8_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK 0x000003E0L +#define MMVM_L2_CONTEXT8_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT_MASK 0x0000FC00L +//MMVM_L2_CONTEXT9_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES +#define MMVM_L2_CONTEXT9_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE__SHIFT 0x0 +#define MMVM_L2_CONTEXT9_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT 0x5 +#define MMVM_L2_CONTEXT9_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT__SHIFT 0xa +#define MMVM_L2_CONTEXT9_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE_MASK 0x0000001FL +#define MMVM_L2_CONTEXT9_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK 0x000003E0L +#define MMVM_L2_CONTEXT9_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT_MASK 0x0000FC00L +//MMVM_L2_CONTEXT10_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES +#define MMVM_L2_CONTEXT10_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE__SHIFT 0x0 +#define MMVM_L2_CONTEXT10_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT 0x5 +#define MMVM_L2_CONTEXT10_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT__SHIFT 0xa +#define MMVM_L2_CONTEXT10_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE_MASK 0x0000001FL +#define MMVM_L2_CONTEXT10_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK 0x000003E0L +#define MMVM_L2_CONTEXT10_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT_MASK 0x0000FC00L +//MMVM_L2_CONTEXT11_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES +#define MMVM_L2_CONTEXT11_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE__SHIFT 0x0 +#define MMVM_L2_CONTEXT11_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT 0x5 +#define MMVM_L2_CONTEXT11_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT__SHIFT 0xa +#define MMVM_L2_CONTEXT11_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE_MASK 0x0000001FL +#define MMVM_L2_CONTEXT11_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK 0x000003E0L +#define MMVM_L2_CONTEXT11_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT_MASK 0x0000FC00L +//MMVM_L2_CONTEXT12_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES +#define MMVM_L2_CONTEXT12_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE__SHIFT 0x0 +#define MMVM_L2_CONTEXT12_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT 0x5 +#define MMVM_L2_CONTEXT12_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT__SHIFT 0xa +#define MMVM_L2_CONTEXT12_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE_MASK 0x0000001FL +#define MMVM_L2_CONTEXT12_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK 0x000003E0L +#define MMVM_L2_CONTEXT12_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT_MASK 0x0000FC00L +//MMVM_L2_CONTEXT13_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES +#define MMVM_L2_CONTEXT13_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE__SHIFT 0x0 +#define MMVM_L2_CONTEXT13_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT 0x5 +#define MMVM_L2_CONTEXT13_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT__SHIFT 0xa +#define MMVM_L2_CONTEXT13_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE_MASK 0x0000001FL +#define MMVM_L2_CONTEXT13_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK 0x000003E0L +#define MMVM_L2_CONTEXT13_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT_MASK 0x0000FC00L +//MMVM_L2_CONTEXT14_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES +#define MMVM_L2_CONTEXT14_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE__SHIFT 0x0 +#define MMVM_L2_CONTEXT14_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT 0x5 +#define MMVM_L2_CONTEXT14_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT__SHIFT 0xa +#define MMVM_L2_CONTEXT14_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE_MASK 0x0000001FL +#define MMVM_L2_CONTEXT14_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK 0x000003E0L +#define MMVM_L2_CONTEXT14_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT_MASK 0x0000FC00L +//MMVM_L2_CONTEXT15_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES +#define MMVM_L2_CONTEXT15_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE__SHIFT 0x0 +#define MMVM_L2_CONTEXT15_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT 0x5 +#define MMVM_L2_CONTEXT15_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT__SHIFT 0xa +#define MMVM_L2_CONTEXT15_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE_MASK 0x0000001FL +#define MMVM_L2_CONTEXT15_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK 0x000003E0L +#define MMVM_L2_CONTEXT15_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT_MASK 0x0000FC00L + + +// addressBlock: mmhub_mmutcl2_mmvml2indec +//MMVM_INVALIDATE_ENG0_SEM +#define MMVM_INVALIDATE_ENG0_SEM__SEMAPHORE__SHIFT 0x0 +#define MMVM_INVALIDATE_ENG0_SEM__SEMAPHORE_MASK 0x00000001L +//MMVM_INVALIDATE_ENG0_REQ +#define MMVM_INVALIDATE_ENG0_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 +#define MMVM_INVALIDATE_ENG0_REQ__FLUSH_TYPE__SHIFT 0x10 +#define MMVM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PTES__SHIFT 0x13 +#define MMVM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PDE0__SHIFT 0x14 +#define MMVM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PDE1__SHIFT 0x15 +#define MMVM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PDE2__SHIFT 0x16 +#define MMVM_INVALIDATE_ENG0_REQ__INVALIDATE_L1_PTES__SHIFT 0x17 +#define MMVM_INVALIDATE_ENG0_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x18 +#define MMVM_INVALIDATE_ENG0_REQ__LOG_REQUEST__SHIFT 0x19 +#define MMVM_INVALIDATE_ENG0_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT 0x1a +#define MMVM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PDE3__SHIFT 0x1b +#define MMVM_INVALIDATE_ENG0_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL +#define MMVM_INVALIDATE_ENG0_REQ__FLUSH_TYPE_MASK 0x00070000L +#define MMVM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PTES_MASK 0x00080000L +#define MMVM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PDE0_MASK 0x00100000L +#define MMVM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PDE1_MASK 0x00200000L +#define MMVM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PDE2_MASK 0x00400000L +#define MMVM_INVALIDATE_ENG0_REQ__INVALIDATE_L1_PTES_MASK 0x00800000L +#define MMVM_INVALIDATE_ENG0_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x01000000L +#define MMVM_INVALIDATE_ENG0_REQ__LOG_REQUEST_MASK 0x02000000L +#define MMVM_INVALIDATE_ENG0_REQ__INVALIDATE_4K_PAGES_ONLY_MASK 0x04000000L +#define MMVM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PDE3_MASK 0x08000000L +//MMVM_INVALIDATE_ENG0_ACK +#define MMVM_INVALIDATE_ENG0_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 +#define MMVM_INVALIDATE_ENG0_ACK__SEMAPHORE__SHIFT 0x10 +#define MMVM_INVALIDATE_ENG0_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL +#define MMVM_INVALIDATE_ENG0_ACK__SEMAPHORE_MASK 0x00010000L +//MMVM_INVALIDATE_ENG0_ADDR_RANGE_LO32 +#define MMVM_INVALIDATE_ENG0_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 +#define MMVM_INVALIDATE_ENG0_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 +#define MMVM_INVALIDATE_ENG0_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L +#define MMVM_INVALIDATE_ENG0_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL +//MMVM_INVALIDATE_ENG0_ADDR_RANGE_HI32 +#define MMVM_INVALIDATE_ENG0_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 +#define MMVM_INVALIDATE_ENG0_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL +//MMVM_INVALIDATE_ENG1_SEM +#define MMVM_INVALIDATE_ENG1_SEM__SEMAPHORE__SHIFT 0x0 +#define MMVM_INVALIDATE_ENG1_SEM__SEMAPHORE_MASK 0x00000001L +//MMVM_INVALIDATE_ENG1_REQ +#define MMVM_INVALIDATE_ENG1_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 +#define MMVM_INVALIDATE_ENG1_REQ__FLUSH_TYPE__SHIFT 0x10 +#define MMVM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PTES__SHIFT 0x13 +#define MMVM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PDE0__SHIFT 0x14 +#define MMVM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PDE1__SHIFT 0x15 +#define MMVM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PDE2__SHIFT 0x16 +#define MMVM_INVALIDATE_ENG1_REQ__INVALIDATE_L1_PTES__SHIFT 0x17 +#define MMVM_INVALIDATE_ENG1_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x18 +#define MMVM_INVALIDATE_ENG1_REQ__LOG_REQUEST__SHIFT 0x19 +#define MMVM_INVALIDATE_ENG1_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT 0x1a +#define MMVM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PDE3__SHIFT 0x1b +#define MMVM_INVALIDATE_ENG1_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL +#define MMVM_INVALIDATE_ENG1_REQ__FLUSH_TYPE_MASK 0x00070000L +#define MMVM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PTES_MASK 0x00080000L +#define MMVM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PDE0_MASK 0x00100000L +#define MMVM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PDE1_MASK 0x00200000L +#define MMVM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PDE2_MASK 0x00400000L +#define MMVM_INVALIDATE_ENG1_REQ__INVALIDATE_L1_PTES_MASK 0x00800000L +#define MMVM_INVALIDATE_ENG1_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x01000000L +#define MMVM_INVALIDATE_ENG1_REQ__LOG_REQUEST_MASK 0x02000000L +#define MMVM_INVALIDATE_ENG1_REQ__INVALIDATE_4K_PAGES_ONLY_MASK 0x04000000L +#define MMVM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PDE3_MASK 0x08000000L +//MMVM_INVALIDATE_ENG1_ACK +#define MMVM_INVALIDATE_ENG1_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 +#define MMVM_INVALIDATE_ENG1_ACK__SEMAPHORE__SHIFT 0x10 +#define MMVM_INVALIDATE_ENG1_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL +#define MMVM_INVALIDATE_ENG1_ACK__SEMAPHORE_MASK 0x00010000L +//MMVM_INVALIDATE_ENG1_ADDR_RANGE_LO32 +#define MMVM_INVALIDATE_ENG1_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 +#define MMVM_INVALIDATE_ENG1_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 +#define MMVM_INVALIDATE_ENG1_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L +#define MMVM_INVALIDATE_ENG1_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL +//MMVM_INVALIDATE_ENG1_ADDR_RANGE_HI32 +#define MMVM_INVALIDATE_ENG1_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 +#define MMVM_INVALIDATE_ENG1_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL +//MMVM_INVALIDATE_ENG2_SEM +#define MMVM_INVALIDATE_ENG2_SEM__SEMAPHORE__SHIFT 0x0 +#define MMVM_INVALIDATE_ENG2_SEM__SEMAPHORE_MASK 0x00000001L +//MMVM_INVALIDATE_ENG2_REQ +#define MMVM_INVALIDATE_ENG2_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 +#define MMVM_INVALIDATE_ENG2_REQ__FLUSH_TYPE__SHIFT 0x10 +#define MMVM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PTES__SHIFT 0x13 +#define MMVM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PDE0__SHIFT 0x14 +#define MMVM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PDE1__SHIFT 0x15 +#define MMVM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PDE2__SHIFT 0x16 +#define MMVM_INVALIDATE_ENG2_REQ__INVALIDATE_L1_PTES__SHIFT 0x17 +#define MMVM_INVALIDATE_ENG2_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x18 +#define MMVM_INVALIDATE_ENG2_REQ__LOG_REQUEST__SHIFT 0x19 +#define MMVM_INVALIDATE_ENG2_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT 0x1a +#define MMVM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PDE3__SHIFT 0x1b +#define MMVM_INVALIDATE_ENG2_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL +#define MMVM_INVALIDATE_ENG2_REQ__FLUSH_TYPE_MASK 0x00070000L +#define MMVM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PTES_MASK 0x00080000L +#define MMVM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PDE0_MASK 0x00100000L +#define MMVM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PDE1_MASK 0x00200000L +#define MMVM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PDE2_MASK 0x00400000L +#define MMVM_INVALIDATE_ENG2_REQ__INVALIDATE_L1_PTES_MASK 0x00800000L +#define MMVM_INVALIDATE_ENG2_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x01000000L +#define MMVM_INVALIDATE_ENG2_REQ__LOG_REQUEST_MASK 0x02000000L +#define MMVM_INVALIDATE_ENG2_REQ__INVALIDATE_4K_PAGES_ONLY_MASK 0x04000000L +#define MMVM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PDE3_MASK 0x08000000L +//MMVM_INVALIDATE_ENG2_ACK +#define MMVM_INVALIDATE_ENG2_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 +#define MMVM_INVALIDATE_ENG2_ACK__SEMAPHORE__SHIFT 0x10 +#define MMVM_INVALIDATE_ENG2_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL +#define MMVM_INVALIDATE_ENG2_ACK__SEMAPHORE_MASK 0x00010000L +//MMVM_INVALIDATE_ENG2_ADDR_RANGE_LO32 +#define MMVM_INVALIDATE_ENG2_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 +#define MMVM_INVALIDATE_ENG2_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 +#define MMVM_INVALIDATE_ENG2_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L +#define MMVM_INVALIDATE_ENG2_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL +//MMVM_INVALIDATE_ENG2_ADDR_RANGE_HI32 +#define MMVM_INVALIDATE_ENG2_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 +#define MMVM_INVALIDATE_ENG2_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL +//MMVM_INVALIDATE_ENG3_SEM +#define MMVM_INVALIDATE_ENG3_SEM__SEMAPHORE__SHIFT 0x0 +#define MMVM_INVALIDATE_ENG3_SEM__SEMAPHORE_MASK 0x00000001L +//MMVM_INVALIDATE_ENG3_REQ +#define MMVM_INVALIDATE_ENG3_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 +#define MMVM_INVALIDATE_ENG3_REQ__FLUSH_TYPE__SHIFT 0x10 +#define MMVM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PTES__SHIFT 0x13 +#define MMVM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PDE0__SHIFT 0x14 +#define MMVM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PDE1__SHIFT 0x15 +#define MMVM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PDE2__SHIFT 0x16 +#define MMVM_INVALIDATE_ENG3_REQ__INVALIDATE_L1_PTES__SHIFT 0x17 +#define MMVM_INVALIDATE_ENG3_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x18 +#define MMVM_INVALIDATE_ENG3_REQ__LOG_REQUEST__SHIFT 0x19 +#define MMVM_INVALIDATE_ENG3_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT 0x1a +#define MMVM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PDE3__SHIFT 0x1b +#define MMVM_INVALIDATE_ENG3_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL +#define MMVM_INVALIDATE_ENG3_REQ__FLUSH_TYPE_MASK 0x00070000L +#define MMVM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PTES_MASK 0x00080000L +#define MMVM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PDE0_MASK 0x00100000L +#define MMVM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PDE1_MASK 0x00200000L +#define MMVM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PDE2_MASK 0x00400000L +#define MMVM_INVALIDATE_ENG3_REQ__INVALIDATE_L1_PTES_MASK 0x00800000L +#define MMVM_INVALIDATE_ENG3_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x01000000L +#define MMVM_INVALIDATE_ENG3_REQ__LOG_REQUEST_MASK 0x02000000L +#define MMVM_INVALIDATE_ENG3_REQ__INVALIDATE_4K_PAGES_ONLY_MASK 0x04000000L +#define MMVM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PDE3_MASK 0x08000000L +//MMVM_INVALIDATE_ENG3_ACK +#define MMVM_INVALIDATE_ENG3_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 +#define MMVM_INVALIDATE_ENG3_ACK__SEMAPHORE__SHIFT 0x10 +#define MMVM_INVALIDATE_ENG3_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL +#define MMVM_INVALIDATE_ENG3_ACK__SEMAPHORE_MASK 0x00010000L +//MMVM_INVALIDATE_ENG3_ADDR_RANGE_LO32 +#define MMVM_INVALIDATE_ENG3_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 +#define MMVM_INVALIDATE_ENG3_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 +#define MMVM_INVALIDATE_ENG3_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L +#define MMVM_INVALIDATE_ENG3_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL +//MMVM_INVALIDATE_ENG3_ADDR_RANGE_HI32 +#define MMVM_INVALIDATE_ENG3_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 +#define MMVM_INVALIDATE_ENG3_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL +//MMVM_INVALIDATE_ENG4_SEM +#define MMVM_INVALIDATE_ENG4_SEM__SEMAPHORE__SHIFT 0x0 +#define MMVM_INVALIDATE_ENG4_SEM__SEMAPHORE_MASK 0x00000001L +//MMVM_INVALIDATE_ENG4_REQ +#define MMVM_INVALIDATE_ENG4_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 +#define MMVM_INVALIDATE_ENG4_REQ__FLUSH_TYPE__SHIFT 0x10 +#define MMVM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PTES__SHIFT 0x13 +#define MMVM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PDE0__SHIFT 0x14 +#define MMVM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PDE1__SHIFT 0x15 +#define MMVM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PDE2__SHIFT 0x16 +#define MMVM_INVALIDATE_ENG4_REQ__INVALIDATE_L1_PTES__SHIFT 0x17 +#define MMVM_INVALIDATE_ENG4_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x18 +#define MMVM_INVALIDATE_ENG4_REQ__LOG_REQUEST__SHIFT 0x19 +#define MMVM_INVALIDATE_ENG4_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT 0x1a +#define MMVM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PDE3__SHIFT 0x1b +#define MMVM_INVALIDATE_ENG4_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL +#define MMVM_INVALIDATE_ENG4_REQ__FLUSH_TYPE_MASK 0x00070000L +#define MMVM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PTES_MASK 0x00080000L +#define MMVM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PDE0_MASK 0x00100000L +#define MMVM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PDE1_MASK 0x00200000L +#define MMVM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PDE2_MASK 0x00400000L +#define MMVM_INVALIDATE_ENG4_REQ__INVALIDATE_L1_PTES_MASK 0x00800000L +#define MMVM_INVALIDATE_ENG4_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x01000000L +#define MMVM_INVALIDATE_ENG4_REQ__LOG_REQUEST_MASK 0x02000000L +#define MMVM_INVALIDATE_ENG4_REQ__INVALIDATE_4K_PAGES_ONLY_MASK 0x04000000L +#define MMVM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PDE3_MASK 0x08000000L +//MMVM_INVALIDATE_ENG4_ACK +#define MMVM_INVALIDATE_ENG4_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 +#define MMVM_INVALIDATE_ENG4_ACK__SEMAPHORE__SHIFT 0x10 +#define MMVM_INVALIDATE_ENG4_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL +#define MMVM_INVALIDATE_ENG4_ACK__SEMAPHORE_MASK 0x00010000L +//MMVM_INVALIDATE_ENG4_ADDR_RANGE_LO32 +#define MMVM_INVALIDATE_ENG4_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 +#define MMVM_INVALIDATE_ENG4_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 +#define MMVM_INVALIDATE_ENG4_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L +#define MMVM_INVALIDATE_ENG4_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL +//MMVM_INVALIDATE_ENG4_ADDR_RANGE_HI32 +#define MMVM_INVALIDATE_ENG4_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 +#define MMVM_INVALIDATE_ENG4_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL +//MMVM_INVALIDATE_ENG5_SEM +#define MMVM_INVALIDATE_ENG5_SEM__SEMAPHORE__SHIFT 0x0 +#define MMVM_INVALIDATE_ENG5_SEM__SEMAPHORE_MASK 0x00000001L +//MMVM_INVALIDATE_ENG5_REQ +#define MMVM_INVALIDATE_ENG5_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 +#define MMVM_INVALIDATE_ENG5_REQ__FLUSH_TYPE__SHIFT 0x10 +#define MMVM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PTES__SHIFT 0x13 +#define MMVM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PDE0__SHIFT 0x14 +#define MMVM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PDE1__SHIFT 0x15 +#define MMVM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PDE2__SHIFT 0x16 +#define MMVM_INVALIDATE_ENG5_REQ__INVALIDATE_L1_PTES__SHIFT 0x17 +#define MMVM_INVALIDATE_ENG5_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x18 +#define MMVM_INVALIDATE_ENG5_REQ__LOG_REQUEST__SHIFT 0x19 +#define MMVM_INVALIDATE_ENG5_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT 0x1a +#define MMVM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PDE3__SHIFT 0x1b +#define MMVM_INVALIDATE_ENG5_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL +#define MMVM_INVALIDATE_ENG5_REQ__FLUSH_TYPE_MASK 0x00070000L +#define MMVM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PTES_MASK 0x00080000L +#define MMVM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PDE0_MASK 0x00100000L +#define MMVM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PDE1_MASK 0x00200000L +#define MMVM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PDE2_MASK 0x00400000L +#define MMVM_INVALIDATE_ENG5_REQ__INVALIDATE_L1_PTES_MASK 0x00800000L +#define MMVM_INVALIDATE_ENG5_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x01000000L +#define MMVM_INVALIDATE_ENG5_REQ__LOG_REQUEST_MASK 0x02000000L +#define MMVM_INVALIDATE_ENG5_REQ__INVALIDATE_4K_PAGES_ONLY_MASK 0x04000000L +#define MMVM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PDE3_MASK 0x08000000L +//MMVM_INVALIDATE_ENG5_ACK +#define MMVM_INVALIDATE_ENG5_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 +#define MMVM_INVALIDATE_ENG5_ACK__SEMAPHORE__SHIFT 0x10 +#define MMVM_INVALIDATE_ENG5_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL +#define MMVM_INVALIDATE_ENG5_ACK__SEMAPHORE_MASK 0x00010000L +//MMVM_INVALIDATE_ENG5_ADDR_RANGE_LO32 +#define MMVM_INVALIDATE_ENG5_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 +#define MMVM_INVALIDATE_ENG5_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 +#define MMVM_INVALIDATE_ENG5_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L +#define MMVM_INVALIDATE_ENG5_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL +//MMVM_INVALIDATE_ENG5_ADDR_RANGE_HI32 +#define MMVM_INVALIDATE_ENG5_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 +#define MMVM_INVALIDATE_ENG5_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL +//MMVM_INVALIDATE_ENG6_SEM +#define MMVM_INVALIDATE_ENG6_SEM__SEMAPHORE__SHIFT 0x0 +#define MMVM_INVALIDATE_ENG6_SEM__SEMAPHORE_MASK 0x00000001L +//MMVM_INVALIDATE_ENG6_REQ +#define MMVM_INVALIDATE_ENG6_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 +#define MMVM_INVALIDATE_ENG6_REQ__FLUSH_TYPE__SHIFT 0x10 +#define MMVM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PTES__SHIFT 0x13 +#define MMVM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PDE0__SHIFT 0x14 +#define MMVM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PDE1__SHIFT 0x15 +#define MMVM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PDE2__SHIFT 0x16 +#define MMVM_INVALIDATE_ENG6_REQ__INVALIDATE_L1_PTES__SHIFT 0x17 +#define MMVM_INVALIDATE_ENG6_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x18 +#define MMVM_INVALIDATE_ENG6_REQ__LOG_REQUEST__SHIFT 0x19 +#define MMVM_INVALIDATE_ENG6_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT 0x1a +#define MMVM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PDE3__SHIFT 0x1b +#define MMVM_INVALIDATE_ENG6_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL +#define MMVM_INVALIDATE_ENG6_REQ__FLUSH_TYPE_MASK 0x00070000L +#define MMVM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PTES_MASK 0x00080000L +#define MMVM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PDE0_MASK 0x00100000L +#define MMVM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PDE1_MASK 0x00200000L +#define MMVM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PDE2_MASK 0x00400000L +#define MMVM_INVALIDATE_ENG6_REQ__INVALIDATE_L1_PTES_MASK 0x00800000L +#define MMVM_INVALIDATE_ENG6_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x01000000L +#define MMVM_INVALIDATE_ENG6_REQ__LOG_REQUEST_MASK 0x02000000L +#define MMVM_INVALIDATE_ENG6_REQ__INVALIDATE_4K_PAGES_ONLY_MASK 0x04000000L +#define MMVM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PDE3_MASK 0x08000000L +//MMVM_INVALIDATE_ENG6_ACK +#define MMVM_INVALIDATE_ENG6_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 +#define MMVM_INVALIDATE_ENG6_ACK__SEMAPHORE__SHIFT 0x10 +#define MMVM_INVALIDATE_ENG6_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL +#define MMVM_INVALIDATE_ENG6_ACK__SEMAPHORE_MASK 0x00010000L +//MMVM_INVALIDATE_ENG6_ADDR_RANGE_LO32 +#define MMVM_INVALIDATE_ENG6_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 +#define MMVM_INVALIDATE_ENG6_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 +#define MMVM_INVALIDATE_ENG6_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L +#define MMVM_INVALIDATE_ENG6_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL +//MMVM_INVALIDATE_ENG6_ADDR_RANGE_HI32 +#define MMVM_INVALIDATE_ENG6_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 +#define MMVM_INVALIDATE_ENG6_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL +//MMVM_INVALIDATE_ENG7_SEM +#define MMVM_INVALIDATE_ENG7_SEM__SEMAPHORE__SHIFT 0x0 +#define MMVM_INVALIDATE_ENG7_SEM__SEMAPHORE_MASK 0x00000001L +//MMVM_INVALIDATE_ENG7_REQ +#define MMVM_INVALIDATE_ENG7_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 +#define MMVM_INVALIDATE_ENG7_REQ__FLUSH_TYPE__SHIFT 0x10 +#define MMVM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PTES__SHIFT 0x13 +#define MMVM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PDE0__SHIFT 0x14 +#define MMVM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PDE1__SHIFT 0x15 +#define MMVM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PDE2__SHIFT 0x16 +#define MMVM_INVALIDATE_ENG7_REQ__INVALIDATE_L1_PTES__SHIFT 0x17 +#define MMVM_INVALIDATE_ENG7_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x18 +#define MMVM_INVALIDATE_ENG7_REQ__LOG_REQUEST__SHIFT 0x19 +#define MMVM_INVALIDATE_ENG7_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT 0x1a +#define MMVM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PDE3__SHIFT 0x1b +#define MMVM_INVALIDATE_ENG7_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL +#define MMVM_INVALIDATE_ENG7_REQ__FLUSH_TYPE_MASK 0x00070000L +#define MMVM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PTES_MASK 0x00080000L +#define MMVM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PDE0_MASK 0x00100000L +#define MMVM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PDE1_MASK 0x00200000L +#define MMVM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PDE2_MASK 0x00400000L +#define MMVM_INVALIDATE_ENG7_REQ__INVALIDATE_L1_PTES_MASK 0x00800000L +#define MMVM_INVALIDATE_ENG7_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x01000000L +#define MMVM_INVALIDATE_ENG7_REQ__LOG_REQUEST_MASK 0x02000000L +#define MMVM_INVALIDATE_ENG7_REQ__INVALIDATE_4K_PAGES_ONLY_MASK 0x04000000L +#define MMVM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PDE3_MASK 0x08000000L +//MMVM_INVALIDATE_ENG7_ACK +#define MMVM_INVALIDATE_ENG7_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 +#define MMVM_INVALIDATE_ENG7_ACK__SEMAPHORE__SHIFT 0x10 +#define MMVM_INVALIDATE_ENG7_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL +#define MMVM_INVALIDATE_ENG7_ACK__SEMAPHORE_MASK 0x00010000L +//MMVM_INVALIDATE_ENG7_ADDR_RANGE_LO32 +#define MMVM_INVALIDATE_ENG7_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 +#define MMVM_INVALIDATE_ENG7_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 +#define MMVM_INVALIDATE_ENG7_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L +#define MMVM_INVALIDATE_ENG7_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL +//MMVM_INVALIDATE_ENG7_ADDR_RANGE_HI32 +#define MMVM_INVALIDATE_ENG7_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 +#define MMVM_INVALIDATE_ENG7_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL +//MMVM_INVALIDATE_ENG8_SEM +#define MMVM_INVALIDATE_ENG8_SEM__SEMAPHORE__SHIFT 0x0 +#define MMVM_INVALIDATE_ENG8_SEM__SEMAPHORE_MASK 0x00000001L +//MMVM_INVALIDATE_ENG8_REQ +#define MMVM_INVALIDATE_ENG8_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 +#define MMVM_INVALIDATE_ENG8_REQ__FLUSH_TYPE__SHIFT 0x10 +#define MMVM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PTES__SHIFT 0x13 +#define MMVM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PDE0__SHIFT 0x14 +#define MMVM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PDE1__SHIFT 0x15 +#define MMVM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PDE2__SHIFT 0x16 +#define MMVM_INVALIDATE_ENG8_REQ__INVALIDATE_L1_PTES__SHIFT 0x17 +#define MMVM_INVALIDATE_ENG8_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x18 +#define MMVM_INVALIDATE_ENG8_REQ__LOG_REQUEST__SHIFT 0x19 +#define MMVM_INVALIDATE_ENG8_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT 0x1a +#define MMVM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PDE3__SHIFT 0x1b +#define MMVM_INVALIDATE_ENG8_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL +#define MMVM_INVALIDATE_ENG8_REQ__FLUSH_TYPE_MASK 0x00070000L +#define MMVM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PTES_MASK 0x00080000L +#define MMVM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PDE0_MASK 0x00100000L +#define MMVM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PDE1_MASK 0x00200000L +#define MMVM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PDE2_MASK 0x00400000L +#define MMVM_INVALIDATE_ENG8_REQ__INVALIDATE_L1_PTES_MASK 0x00800000L +#define MMVM_INVALIDATE_ENG8_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x01000000L +#define MMVM_INVALIDATE_ENG8_REQ__LOG_REQUEST_MASK 0x02000000L +#define MMVM_INVALIDATE_ENG8_REQ__INVALIDATE_4K_PAGES_ONLY_MASK 0x04000000L +#define MMVM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PDE3_MASK 0x08000000L +//MMVM_INVALIDATE_ENG8_ACK +#define MMVM_INVALIDATE_ENG8_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 +#define MMVM_INVALIDATE_ENG8_ACK__SEMAPHORE__SHIFT 0x10 +#define MMVM_INVALIDATE_ENG8_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL +#define MMVM_INVALIDATE_ENG8_ACK__SEMAPHORE_MASK 0x00010000L +//MMVM_INVALIDATE_ENG8_ADDR_RANGE_LO32 +#define MMVM_INVALIDATE_ENG8_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 +#define MMVM_INVALIDATE_ENG8_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 +#define MMVM_INVALIDATE_ENG8_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L +#define MMVM_INVALIDATE_ENG8_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL +//MMVM_INVALIDATE_ENG8_ADDR_RANGE_HI32 +#define MMVM_INVALIDATE_ENG8_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 +#define MMVM_INVALIDATE_ENG8_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL +//MMVM_INVALIDATE_ENG9_SEM +#define MMVM_INVALIDATE_ENG9_SEM__SEMAPHORE__SHIFT 0x0 +#define MMVM_INVALIDATE_ENG9_SEM__SEMAPHORE_MASK 0x00000001L +//MMVM_INVALIDATE_ENG9_REQ +#define MMVM_INVALIDATE_ENG9_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 +#define MMVM_INVALIDATE_ENG9_REQ__FLUSH_TYPE__SHIFT 0x10 +#define MMVM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PTES__SHIFT 0x13 +#define MMVM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PDE0__SHIFT 0x14 +#define MMVM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PDE1__SHIFT 0x15 +#define MMVM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PDE2__SHIFT 0x16 +#define MMVM_INVALIDATE_ENG9_REQ__INVALIDATE_L1_PTES__SHIFT 0x17 +#define MMVM_INVALIDATE_ENG9_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x18 +#define MMVM_INVALIDATE_ENG9_REQ__LOG_REQUEST__SHIFT 0x19 +#define MMVM_INVALIDATE_ENG9_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT 0x1a +#define MMVM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PDE3__SHIFT 0x1b +#define MMVM_INVALIDATE_ENG9_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL +#define MMVM_INVALIDATE_ENG9_REQ__FLUSH_TYPE_MASK 0x00070000L +#define MMVM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PTES_MASK 0x00080000L +#define MMVM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PDE0_MASK 0x00100000L +#define MMVM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PDE1_MASK 0x00200000L +#define MMVM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PDE2_MASK 0x00400000L +#define MMVM_INVALIDATE_ENG9_REQ__INVALIDATE_L1_PTES_MASK 0x00800000L +#define MMVM_INVALIDATE_ENG9_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x01000000L +#define MMVM_INVALIDATE_ENG9_REQ__LOG_REQUEST_MASK 0x02000000L +#define MMVM_INVALIDATE_ENG9_REQ__INVALIDATE_4K_PAGES_ONLY_MASK 0x04000000L +#define MMVM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PDE3_MASK 0x08000000L +//MMVM_INVALIDATE_ENG9_ACK +#define MMVM_INVALIDATE_ENG9_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 +#define MMVM_INVALIDATE_ENG9_ACK__SEMAPHORE__SHIFT 0x10 +#define MMVM_INVALIDATE_ENG9_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL +#define MMVM_INVALIDATE_ENG9_ACK__SEMAPHORE_MASK 0x00010000L +//MMVM_INVALIDATE_ENG9_ADDR_RANGE_LO32 +#define MMVM_INVALIDATE_ENG9_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 +#define MMVM_INVALIDATE_ENG9_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 +#define MMVM_INVALIDATE_ENG9_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L +#define MMVM_INVALIDATE_ENG9_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL +//MMVM_INVALIDATE_ENG9_ADDR_RANGE_HI32 +#define MMVM_INVALIDATE_ENG9_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 +#define MMVM_INVALIDATE_ENG9_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL +//MMVM_INVALIDATE_ENG10_SEM +#define MMVM_INVALIDATE_ENG10_SEM__SEMAPHORE__SHIFT 0x0 +#define MMVM_INVALIDATE_ENG10_SEM__SEMAPHORE_MASK 0x00000001L +//MMVM_INVALIDATE_ENG10_REQ +#define MMVM_INVALIDATE_ENG10_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 +#define MMVM_INVALIDATE_ENG10_REQ__FLUSH_TYPE__SHIFT 0x10 +#define MMVM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PTES__SHIFT 0x13 +#define MMVM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PDE0__SHIFT 0x14 +#define MMVM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PDE1__SHIFT 0x15 +#define MMVM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PDE2__SHIFT 0x16 +#define MMVM_INVALIDATE_ENG10_REQ__INVALIDATE_L1_PTES__SHIFT 0x17 +#define MMVM_INVALIDATE_ENG10_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x18 +#define MMVM_INVALIDATE_ENG10_REQ__LOG_REQUEST__SHIFT 0x19 +#define MMVM_INVALIDATE_ENG10_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT 0x1a +#define MMVM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PDE3__SHIFT 0x1b +#define MMVM_INVALIDATE_ENG10_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL +#define MMVM_INVALIDATE_ENG10_REQ__FLUSH_TYPE_MASK 0x00070000L +#define MMVM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PTES_MASK 0x00080000L +#define MMVM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PDE0_MASK 0x00100000L +#define MMVM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PDE1_MASK 0x00200000L +#define MMVM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PDE2_MASK 0x00400000L +#define MMVM_INVALIDATE_ENG10_REQ__INVALIDATE_L1_PTES_MASK 0x00800000L +#define MMVM_INVALIDATE_ENG10_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x01000000L +#define MMVM_INVALIDATE_ENG10_REQ__LOG_REQUEST_MASK 0x02000000L +#define MMVM_INVALIDATE_ENG10_REQ__INVALIDATE_4K_PAGES_ONLY_MASK 0x04000000L +#define MMVM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PDE3_MASK 0x08000000L +//MMVM_INVALIDATE_ENG10_ACK +#define MMVM_INVALIDATE_ENG10_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 +#define MMVM_INVALIDATE_ENG10_ACK__SEMAPHORE__SHIFT 0x10 +#define MMVM_INVALIDATE_ENG10_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL +#define MMVM_INVALIDATE_ENG10_ACK__SEMAPHORE_MASK 0x00010000L +//MMVM_INVALIDATE_ENG10_ADDR_RANGE_LO32 +#define MMVM_INVALIDATE_ENG10_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 +#define MMVM_INVALIDATE_ENG10_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 +#define MMVM_INVALIDATE_ENG10_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L +#define MMVM_INVALIDATE_ENG10_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL +//MMVM_INVALIDATE_ENG10_ADDR_RANGE_HI32 +#define MMVM_INVALIDATE_ENG10_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 +#define MMVM_INVALIDATE_ENG10_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL +//MMVM_INVALIDATE_ENG11_SEM +#define MMVM_INVALIDATE_ENG11_SEM__SEMAPHORE__SHIFT 0x0 +#define MMVM_INVALIDATE_ENG11_SEM__SEMAPHORE_MASK 0x00000001L +//MMVM_INVALIDATE_ENG11_REQ +#define MMVM_INVALIDATE_ENG11_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 +#define MMVM_INVALIDATE_ENG11_REQ__FLUSH_TYPE__SHIFT 0x10 +#define MMVM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PTES__SHIFT 0x13 +#define MMVM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PDE0__SHIFT 0x14 +#define MMVM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PDE1__SHIFT 0x15 +#define MMVM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PDE2__SHIFT 0x16 +#define MMVM_INVALIDATE_ENG11_REQ__INVALIDATE_L1_PTES__SHIFT 0x17 +#define MMVM_INVALIDATE_ENG11_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x18 +#define MMVM_INVALIDATE_ENG11_REQ__LOG_REQUEST__SHIFT 0x19 +#define MMVM_INVALIDATE_ENG11_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT 0x1a +#define MMVM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PDE3__SHIFT 0x1b +#define MMVM_INVALIDATE_ENG11_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL +#define MMVM_INVALIDATE_ENG11_REQ__FLUSH_TYPE_MASK 0x00070000L +#define MMVM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PTES_MASK 0x00080000L +#define MMVM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PDE0_MASK 0x00100000L +#define MMVM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PDE1_MASK 0x00200000L +#define MMVM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PDE2_MASK 0x00400000L +#define MMVM_INVALIDATE_ENG11_REQ__INVALIDATE_L1_PTES_MASK 0x00800000L +#define MMVM_INVALIDATE_ENG11_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x01000000L +#define MMVM_INVALIDATE_ENG11_REQ__LOG_REQUEST_MASK 0x02000000L +#define MMVM_INVALIDATE_ENG11_REQ__INVALIDATE_4K_PAGES_ONLY_MASK 0x04000000L +#define MMVM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PDE3_MASK 0x08000000L +//MMVM_INVALIDATE_ENG11_ACK +#define MMVM_INVALIDATE_ENG11_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 +#define MMVM_INVALIDATE_ENG11_ACK__SEMAPHORE__SHIFT 0x10 +#define MMVM_INVALIDATE_ENG11_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL +#define MMVM_INVALIDATE_ENG11_ACK__SEMAPHORE_MASK 0x00010000L +//MMVM_INVALIDATE_ENG11_ADDR_RANGE_LO32 +#define MMVM_INVALIDATE_ENG11_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 +#define MMVM_INVALIDATE_ENG11_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 +#define MMVM_INVALIDATE_ENG11_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L +#define MMVM_INVALIDATE_ENG11_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL +//MMVM_INVALIDATE_ENG11_ADDR_RANGE_HI32 +#define MMVM_INVALIDATE_ENG11_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 +#define MMVM_INVALIDATE_ENG11_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL +//MMVM_INVALIDATE_ENG12_SEM +#define MMVM_INVALIDATE_ENG12_SEM__SEMAPHORE__SHIFT 0x0 +#define MMVM_INVALIDATE_ENG12_SEM__SEMAPHORE_MASK 0x00000001L +//MMVM_INVALIDATE_ENG12_REQ +#define MMVM_INVALIDATE_ENG12_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 +#define MMVM_INVALIDATE_ENG12_REQ__FLUSH_TYPE__SHIFT 0x10 +#define MMVM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PTES__SHIFT 0x13 +#define MMVM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PDE0__SHIFT 0x14 +#define MMVM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PDE1__SHIFT 0x15 +#define MMVM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PDE2__SHIFT 0x16 +#define MMVM_INVALIDATE_ENG12_REQ__INVALIDATE_L1_PTES__SHIFT 0x17 +#define MMVM_INVALIDATE_ENG12_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x18 +#define MMVM_INVALIDATE_ENG12_REQ__LOG_REQUEST__SHIFT 0x19 +#define MMVM_INVALIDATE_ENG12_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT 0x1a +#define MMVM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PDE3__SHIFT 0x1b +#define MMVM_INVALIDATE_ENG12_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL +#define MMVM_INVALIDATE_ENG12_REQ__FLUSH_TYPE_MASK 0x00070000L +#define MMVM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PTES_MASK 0x00080000L +#define MMVM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PDE0_MASK 0x00100000L +#define MMVM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PDE1_MASK 0x00200000L +#define MMVM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PDE2_MASK 0x00400000L +#define MMVM_INVALIDATE_ENG12_REQ__INVALIDATE_L1_PTES_MASK 0x00800000L +#define MMVM_INVALIDATE_ENG12_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x01000000L +#define MMVM_INVALIDATE_ENG12_REQ__LOG_REQUEST_MASK 0x02000000L +#define MMVM_INVALIDATE_ENG12_REQ__INVALIDATE_4K_PAGES_ONLY_MASK 0x04000000L +#define MMVM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PDE3_MASK 0x08000000L +//MMVM_INVALIDATE_ENG12_ACK +#define MMVM_INVALIDATE_ENG12_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 +#define MMVM_INVALIDATE_ENG12_ACK__SEMAPHORE__SHIFT 0x10 +#define MMVM_INVALIDATE_ENG12_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL +#define MMVM_INVALIDATE_ENG12_ACK__SEMAPHORE_MASK 0x00010000L +//MMVM_INVALIDATE_ENG12_ADDR_RANGE_LO32 +#define MMVM_INVALIDATE_ENG12_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 +#define MMVM_INVALIDATE_ENG12_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 +#define MMVM_INVALIDATE_ENG12_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L +#define MMVM_INVALIDATE_ENG12_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL +//MMVM_INVALIDATE_ENG12_ADDR_RANGE_HI32 +#define MMVM_INVALIDATE_ENG12_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 +#define MMVM_INVALIDATE_ENG12_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL +//MMVM_INVALIDATE_ENG13_SEM +#define MMVM_INVALIDATE_ENG13_SEM__SEMAPHORE__SHIFT 0x0 +#define MMVM_INVALIDATE_ENG13_SEM__SEMAPHORE_MASK 0x00000001L +//MMVM_INVALIDATE_ENG13_REQ +#define MMVM_INVALIDATE_ENG13_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 +#define MMVM_INVALIDATE_ENG13_REQ__FLUSH_TYPE__SHIFT 0x10 +#define MMVM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PTES__SHIFT 0x13 +#define MMVM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PDE0__SHIFT 0x14 +#define MMVM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PDE1__SHIFT 0x15 +#define MMVM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PDE2__SHIFT 0x16 +#define MMVM_INVALIDATE_ENG13_REQ__INVALIDATE_L1_PTES__SHIFT 0x17 +#define MMVM_INVALIDATE_ENG13_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x18 +#define MMVM_INVALIDATE_ENG13_REQ__LOG_REQUEST__SHIFT 0x19 +#define MMVM_INVALIDATE_ENG13_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT 0x1a +#define MMVM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PDE3__SHIFT 0x1b +#define MMVM_INVALIDATE_ENG13_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL +#define MMVM_INVALIDATE_ENG13_REQ__FLUSH_TYPE_MASK 0x00070000L +#define MMVM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PTES_MASK 0x00080000L +#define MMVM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PDE0_MASK 0x00100000L +#define MMVM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PDE1_MASK 0x00200000L +#define MMVM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PDE2_MASK 0x00400000L +#define MMVM_INVALIDATE_ENG13_REQ__INVALIDATE_L1_PTES_MASK 0x00800000L +#define MMVM_INVALIDATE_ENG13_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x01000000L +#define MMVM_INVALIDATE_ENG13_REQ__LOG_REQUEST_MASK 0x02000000L +#define MMVM_INVALIDATE_ENG13_REQ__INVALIDATE_4K_PAGES_ONLY_MASK 0x04000000L +#define MMVM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PDE3_MASK 0x08000000L +//MMVM_INVALIDATE_ENG13_ACK +#define MMVM_INVALIDATE_ENG13_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 +#define MMVM_INVALIDATE_ENG13_ACK__SEMAPHORE__SHIFT 0x10 +#define MMVM_INVALIDATE_ENG13_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL +#define MMVM_INVALIDATE_ENG13_ACK__SEMAPHORE_MASK 0x00010000L +//MMVM_INVALIDATE_ENG13_ADDR_RANGE_LO32 +#define MMVM_INVALIDATE_ENG13_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 +#define MMVM_INVALIDATE_ENG13_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 +#define MMVM_INVALIDATE_ENG13_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L +#define MMVM_INVALIDATE_ENG13_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL +//MMVM_INVALIDATE_ENG13_ADDR_RANGE_HI32 +#define MMVM_INVALIDATE_ENG13_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 +#define MMVM_INVALIDATE_ENG13_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL +//MMVM_INVALIDATE_ENG14_SEM +#define MMVM_INVALIDATE_ENG14_SEM__SEMAPHORE__SHIFT 0x0 +#define MMVM_INVALIDATE_ENG14_SEM__SEMAPHORE_MASK 0x00000001L +//MMVM_INVALIDATE_ENG14_REQ +#define MMVM_INVALIDATE_ENG14_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 +#define MMVM_INVALIDATE_ENG14_REQ__FLUSH_TYPE__SHIFT 0x10 +#define MMVM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PTES__SHIFT 0x13 +#define MMVM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PDE0__SHIFT 0x14 +#define MMVM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PDE1__SHIFT 0x15 +#define MMVM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PDE2__SHIFT 0x16 +#define MMVM_INVALIDATE_ENG14_REQ__INVALIDATE_L1_PTES__SHIFT 0x17 +#define MMVM_INVALIDATE_ENG14_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x18 +#define MMVM_INVALIDATE_ENG14_REQ__LOG_REQUEST__SHIFT 0x19 +#define MMVM_INVALIDATE_ENG14_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT 0x1a +#define MMVM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PDE3__SHIFT 0x1b +#define MMVM_INVALIDATE_ENG14_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL +#define MMVM_INVALIDATE_ENG14_REQ__FLUSH_TYPE_MASK 0x00070000L +#define MMVM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PTES_MASK 0x00080000L +#define MMVM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PDE0_MASK 0x00100000L +#define MMVM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PDE1_MASK 0x00200000L +#define MMVM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PDE2_MASK 0x00400000L +#define MMVM_INVALIDATE_ENG14_REQ__INVALIDATE_L1_PTES_MASK 0x00800000L +#define MMVM_INVALIDATE_ENG14_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x01000000L +#define MMVM_INVALIDATE_ENG14_REQ__LOG_REQUEST_MASK 0x02000000L +#define MMVM_INVALIDATE_ENG14_REQ__INVALIDATE_4K_PAGES_ONLY_MASK 0x04000000L +#define MMVM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PDE3_MASK 0x08000000L +//MMVM_INVALIDATE_ENG14_ACK +#define MMVM_INVALIDATE_ENG14_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 +#define MMVM_INVALIDATE_ENG14_ACK__SEMAPHORE__SHIFT 0x10 +#define MMVM_INVALIDATE_ENG14_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL +#define MMVM_INVALIDATE_ENG14_ACK__SEMAPHORE_MASK 0x00010000L +//MMVM_INVALIDATE_ENG14_ADDR_RANGE_LO32 +#define MMVM_INVALIDATE_ENG14_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 +#define MMVM_INVALIDATE_ENG14_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 +#define MMVM_INVALIDATE_ENG14_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L +#define MMVM_INVALIDATE_ENG14_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL +//MMVM_INVALIDATE_ENG14_ADDR_RANGE_HI32 +#define MMVM_INVALIDATE_ENG14_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 +#define MMVM_INVALIDATE_ENG14_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL +//MMVM_INVALIDATE_ENG15_SEM +#define MMVM_INVALIDATE_ENG15_SEM__SEMAPHORE__SHIFT 0x0 +#define MMVM_INVALIDATE_ENG15_SEM__SEMAPHORE_MASK 0x00000001L +//MMVM_INVALIDATE_ENG15_REQ +#define MMVM_INVALIDATE_ENG15_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 +#define MMVM_INVALIDATE_ENG15_REQ__FLUSH_TYPE__SHIFT 0x10 +#define MMVM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PTES__SHIFT 0x13 +#define MMVM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PDE0__SHIFT 0x14 +#define MMVM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PDE1__SHIFT 0x15 +#define MMVM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PDE2__SHIFT 0x16 +#define MMVM_INVALIDATE_ENG15_REQ__INVALIDATE_L1_PTES__SHIFT 0x17 +#define MMVM_INVALIDATE_ENG15_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x18 +#define MMVM_INVALIDATE_ENG15_REQ__LOG_REQUEST__SHIFT 0x19 +#define MMVM_INVALIDATE_ENG15_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT 0x1a +#define MMVM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PDE3__SHIFT 0x1b +#define MMVM_INVALIDATE_ENG15_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL +#define MMVM_INVALIDATE_ENG15_REQ__FLUSH_TYPE_MASK 0x00070000L +#define MMVM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PTES_MASK 0x00080000L +#define MMVM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PDE0_MASK 0x00100000L +#define MMVM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PDE1_MASK 0x00200000L +#define MMVM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PDE2_MASK 0x00400000L +#define MMVM_INVALIDATE_ENG15_REQ__INVALIDATE_L1_PTES_MASK 0x00800000L +#define MMVM_INVALIDATE_ENG15_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x01000000L +#define MMVM_INVALIDATE_ENG15_REQ__LOG_REQUEST_MASK 0x02000000L +#define MMVM_INVALIDATE_ENG15_REQ__INVALIDATE_4K_PAGES_ONLY_MASK 0x04000000L +#define MMVM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PDE3_MASK 0x08000000L +//MMVM_INVALIDATE_ENG15_ACK +#define MMVM_INVALIDATE_ENG15_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 +#define MMVM_INVALIDATE_ENG15_ACK__SEMAPHORE__SHIFT 0x10 +#define MMVM_INVALIDATE_ENG15_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL +#define MMVM_INVALIDATE_ENG15_ACK__SEMAPHORE_MASK 0x00010000L +//MMVM_INVALIDATE_ENG15_ADDR_RANGE_LO32 +#define MMVM_INVALIDATE_ENG15_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 +#define MMVM_INVALIDATE_ENG15_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 +#define MMVM_INVALIDATE_ENG15_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L +#define MMVM_INVALIDATE_ENG15_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL +//MMVM_INVALIDATE_ENG15_ADDR_RANGE_HI32 +#define MMVM_INVALIDATE_ENG15_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 +#define MMVM_INVALIDATE_ENG15_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL +//MMVM_INVALIDATE_ENG16_SEM +#define MMVM_INVALIDATE_ENG16_SEM__SEMAPHORE__SHIFT 0x0 +#define MMVM_INVALIDATE_ENG16_SEM__SEMAPHORE_MASK 0x00000001L +//MMVM_INVALIDATE_ENG16_REQ +#define MMVM_INVALIDATE_ENG16_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 +#define MMVM_INVALIDATE_ENG16_REQ__FLUSH_TYPE__SHIFT 0x10 +#define MMVM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PTES__SHIFT 0x13 +#define MMVM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PDE0__SHIFT 0x14 +#define MMVM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PDE1__SHIFT 0x15 +#define MMVM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PDE2__SHIFT 0x16 +#define MMVM_INVALIDATE_ENG16_REQ__INVALIDATE_L1_PTES__SHIFT 0x17 +#define MMVM_INVALIDATE_ENG16_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x18 +#define MMVM_INVALIDATE_ENG16_REQ__LOG_REQUEST__SHIFT 0x19 +#define MMVM_INVALIDATE_ENG16_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT 0x1a +#define MMVM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PDE3__SHIFT 0x1b +#define MMVM_INVALIDATE_ENG16_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL +#define MMVM_INVALIDATE_ENG16_REQ__FLUSH_TYPE_MASK 0x00070000L +#define MMVM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PTES_MASK 0x00080000L +#define MMVM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PDE0_MASK 0x00100000L +#define MMVM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PDE1_MASK 0x00200000L +#define MMVM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PDE2_MASK 0x00400000L +#define MMVM_INVALIDATE_ENG16_REQ__INVALIDATE_L1_PTES_MASK 0x00800000L +#define MMVM_INVALIDATE_ENG16_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x01000000L +#define MMVM_INVALIDATE_ENG16_REQ__LOG_REQUEST_MASK 0x02000000L +#define MMVM_INVALIDATE_ENG16_REQ__INVALIDATE_4K_PAGES_ONLY_MASK 0x04000000L +#define MMVM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PDE3_MASK 0x08000000L +//MMVM_INVALIDATE_ENG16_ACK +#define MMVM_INVALIDATE_ENG16_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 +#define MMVM_INVALIDATE_ENG16_ACK__SEMAPHORE__SHIFT 0x10 +#define MMVM_INVALIDATE_ENG16_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL +#define MMVM_INVALIDATE_ENG16_ACK__SEMAPHORE_MASK 0x00010000L +//MMVM_INVALIDATE_ENG16_ADDR_RANGE_LO32 +#define MMVM_INVALIDATE_ENG16_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 +#define MMVM_INVALIDATE_ENG16_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 +#define MMVM_INVALIDATE_ENG16_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L +#define MMVM_INVALIDATE_ENG16_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL +//MMVM_INVALIDATE_ENG16_ADDR_RANGE_HI32 +#define MMVM_INVALIDATE_ENG16_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 +#define MMVM_INVALIDATE_ENG16_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL +//MMVM_INVALIDATE_ENG17_SEM +#define MMVM_INVALIDATE_ENG17_SEM__SEMAPHORE__SHIFT 0x0 +#define MMVM_INVALIDATE_ENG17_SEM__SEMAPHORE_MASK 0x00000001L +//MMVM_INVALIDATE_ENG17_REQ +#define MMVM_INVALIDATE_ENG17_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 +#define MMVM_INVALIDATE_ENG17_REQ__FLUSH_TYPE__SHIFT 0x10 +#define MMVM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PTES__SHIFT 0x13 +#define MMVM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PDE0__SHIFT 0x14 +#define MMVM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PDE1__SHIFT 0x15 +#define MMVM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PDE2__SHIFT 0x16 +#define MMVM_INVALIDATE_ENG17_REQ__INVALIDATE_L1_PTES__SHIFT 0x17 +#define MMVM_INVALIDATE_ENG17_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x18 +#define MMVM_INVALIDATE_ENG17_REQ__LOG_REQUEST__SHIFT 0x19 +#define MMVM_INVALIDATE_ENG17_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT 0x1a +#define MMVM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PDE3__SHIFT 0x1b +#define MMVM_INVALIDATE_ENG17_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL +#define MMVM_INVALIDATE_ENG17_REQ__FLUSH_TYPE_MASK 0x00070000L +#define MMVM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PTES_MASK 0x00080000L +#define MMVM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PDE0_MASK 0x00100000L +#define MMVM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PDE1_MASK 0x00200000L +#define MMVM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PDE2_MASK 0x00400000L +#define MMVM_INVALIDATE_ENG17_REQ__INVALIDATE_L1_PTES_MASK 0x00800000L +#define MMVM_INVALIDATE_ENG17_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x01000000L +#define MMVM_INVALIDATE_ENG17_REQ__LOG_REQUEST_MASK 0x02000000L +#define MMVM_INVALIDATE_ENG17_REQ__INVALIDATE_4K_PAGES_ONLY_MASK 0x04000000L +#define MMVM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PDE3_MASK 0x08000000L +//MMVM_INVALIDATE_ENG17_ACK +#define MMVM_INVALIDATE_ENG17_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 +#define MMVM_INVALIDATE_ENG17_ACK__SEMAPHORE__SHIFT 0x10 +#define MMVM_INVALIDATE_ENG17_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL +#define MMVM_INVALIDATE_ENG17_ACK__SEMAPHORE_MASK 0x00010000L +//MMVM_INVALIDATE_ENG17_ADDR_RANGE_LO32 +#define MMVM_INVALIDATE_ENG17_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 +#define MMVM_INVALIDATE_ENG17_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 +#define MMVM_INVALIDATE_ENG17_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L +#define MMVM_INVALIDATE_ENG17_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL +//MMVM_INVALIDATE_ENG17_ADDR_RANGE_HI32 +#define MMVM_INVALIDATE_ENG17_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 +#define MMVM_INVALIDATE_ENG17_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL + + +// addressBlock: mmhub_mmutcl2_mmvmsharedhvdec +//MMVM_PCIE_ATS_CNTL +#define MMVM_PCIE_ATS_CNTL__STU__SHIFT 0x10 +#define MMVM_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT 0x1f +#define MMVM_PCIE_ATS_CNTL__STU_MASK 0x001F0000L +#define MMVM_PCIE_ATS_CNTL__ATC_ENABLE_MASK 0x80000000L +//MMMC_VM_NB_MMIOBASE +#define MMMC_VM_NB_MMIOBASE__MMIOBASE__SHIFT 0x0 +#define MMMC_VM_NB_MMIOBASE__MMIOBASE_MASK 0xFFFFFFFFL +//MMMC_VM_NB_MMIOLIMIT +#define MMMC_VM_NB_MMIOLIMIT__MMIOLIMIT__SHIFT 0x0 +#define MMMC_VM_NB_MMIOLIMIT__MMIOLIMIT_MASK 0xFFFFFFFFL +//MMMC_VM_NB_PCI_CTRL +#define MMMC_VM_NB_PCI_CTRL__MMIOENABLE__SHIFT 0x17 +#define MMMC_VM_NB_PCI_CTRL__MMIOENABLE_MASK 0x00800000L +//MMMC_VM_NB_PCI_ARB +#define MMMC_VM_NB_PCI_ARB__VGA_HOLE__SHIFT 0x3 +#define MMMC_VM_NB_PCI_ARB__VGA_HOLE_MASK 0x00000008L +//MMMC_VM_NB_TOP_OF_DRAM_SLOT1 +#define MMMC_VM_NB_TOP_OF_DRAM_SLOT1__TOP_OF_DRAM__SHIFT 0x17 +#define MMMC_VM_NB_TOP_OF_DRAM_SLOT1__TOP_OF_DRAM_MASK 0xFF800000L +//MMMC_VM_NB_LOWER_TOP_OF_DRAM2 +#define MMMC_VM_NB_LOWER_TOP_OF_DRAM2__ENABLE__SHIFT 0x0 +#define MMMC_VM_NB_LOWER_TOP_OF_DRAM2__LOWER_TOM2__SHIFT 0x17 +#define MMMC_VM_NB_LOWER_TOP_OF_DRAM2__ENABLE_MASK 0x00000001L +#define MMMC_VM_NB_LOWER_TOP_OF_DRAM2__LOWER_TOM2_MASK 0xFF800000L +//MMMC_VM_NB_UPPER_TOP_OF_DRAM2 +#define MMMC_VM_NB_UPPER_TOP_OF_DRAM2__UPPER_TOM2__SHIFT 0x0 +#define MMMC_VM_NB_UPPER_TOP_OF_DRAM2__UPPER_TOM2_MASK 0x0000FFFFL +//MMMC_VM_STEERING +#define MMMC_VM_STEERING__DEFAULT_STEERING__SHIFT 0x0 +#define MMMC_VM_STEERING__DEFAULT_STEERING_MASK 0x00000003L +//MMMC_SHARED_VIRT_RESET_REQ +#define MMMC_SHARED_VIRT_RESET_REQ__VF__SHIFT 0x0 +#define MMMC_SHARED_VIRT_RESET_REQ__PF__SHIFT 0x1f +#define MMMC_SHARED_VIRT_RESET_REQ__VF_MASK 0x7FFFFFFFL +#define MMMC_SHARED_VIRT_RESET_REQ__PF_MASK 0x80000000L +//MMMC_VM_CACHEABLE_DRAM_ADDRESS_START +#define MMMC_VM_CACHEABLE_DRAM_ADDRESS_START__ADDRESS__SHIFT 0x0 +#define MMMC_VM_CACHEABLE_DRAM_ADDRESS_START__ADDRESS_MASK 0x00FFFFFFL +//MMMC_VM_CACHEABLE_DRAM_ADDRESS_END +#define MMMC_VM_CACHEABLE_DRAM_ADDRESS_END__ADDRESS__SHIFT 0x0 +#define MMMC_VM_CACHEABLE_DRAM_ADDRESS_END__ADDRESS_MASK 0x00FFFFFFL +//MMMC_VM_LOCAL_SYSMEM_ADDRESS_START +#define MMMC_VM_LOCAL_SYSMEM_ADDRESS_START__ADDRESS__SHIFT 0x0 +#define MMMC_VM_LOCAL_SYSMEM_ADDRESS_START__ADDRESS_MASK 0x00FFFFFFL +//MMMC_VM_LOCAL_SYSMEM_ADDRESS_END +#define MMMC_VM_LOCAL_SYSMEM_ADDRESS_END__ADDRESS__SHIFT 0x0 +#define MMMC_VM_LOCAL_SYSMEM_ADDRESS_END__ADDRESS_MASK 0x00FFFFFFL +//MMMC_VM_APT_CNTL +#define MMMC_VM_APT_CNTL__FORCE_MTYPE_UC__SHIFT 0x0 +#define MMMC_VM_APT_CNTL__DIRECT_SYSTEM_EN__SHIFT 0x1 +#define MMMC_VM_APT_CNTL__FRAG_APT_INTXN_MODE__SHIFT 0x2 +#define MMMC_VM_APT_CNTL__CHECK_IS_LOCAL__SHIFT 0x4 +#define MMMC_VM_APT_CNTL__CAP_FRAG_SIZE_2M__SHIFT 0x5 +#define MMMC_VM_APT_CNTL__LOCAL_SYSMEM_APERTURE_CNTL__SHIFT 0x6 +#define MMMC_VM_APT_CNTL__LPDDR_APERTURE_CNTL__SHIFT 0x8 +#define MMMC_VM_APT_CNTL__FORCE_MTYPE_UC_MASK 0x00000001L +#define MMMC_VM_APT_CNTL__DIRECT_SYSTEM_EN_MASK 0x00000002L +#define MMMC_VM_APT_CNTL__FRAG_APT_INTXN_MODE_MASK 0x0000000CL +#define MMMC_VM_APT_CNTL__CHECK_IS_LOCAL_MASK 0x00000010L +#define MMMC_VM_APT_CNTL__CAP_FRAG_SIZE_2M_MASK 0x00000020L +#define MMMC_VM_APT_CNTL__LOCAL_SYSMEM_APERTURE_CNTL_MASK 0x000000C0L +#define MMMC_VM_APT_CNTL__LPDDR_APERTURE_CNTL_MASK 0x00000300L +//MMUTCL2_HARVEST_BYPASS_GROUPS +#define MMUTCL2_HARVEST_BYPASS_GROUPS__BYPASS_GROUPS__SHIFT 0x0 +#define MMUTCL2_HARVEST_BYPASS_GROUPS__BYPASS_GROUPS_MASK 0xFFFFFFFFL + + +// addressBlock: mmhub_mmutcl2_mmatcl2hvdec +//MM_ATC_L2_CNTL +#define MM_ATC_L2_CNTL__NUMBER_OF_TRANSLATION_READ_REQUESTS__SHIFT 0x0 +#define MM_ATC_L2_CNTL__NUMBER_OF_TRANSLATION_WRITE_REQUESTS__SHIFT 0x2 +#define MM_ATC_L2_CNTL__NUMBER_OF_TRANSLATION_READS_DEPENDS_ON_ADDR_MOD__SHIFT 0x4 +#define MM_ATC_L2_CNTL__NUMBER_OF_TRANSLATION_WRITES_DEPENDS_ON_ADDR_MOD__SHIFT 0x5 +#define MM_ATC_L2_CNTL__NUMBER_OF_HOST_TRANSLATION_READ_REQUESTS__SHIFT 0x6 +#define MM_ATC_L2_CNTL__NUMBER_OF_HOST_TRANSLATION_WRITE_REQUESTS__SHIFT 0x8 +#define MM_ATC_L2_CNTL__NUMBER_OF_HOST_TRANSLATION_READS_DEPENDS_ON_ADDR_MOD__SHIFT 0xa +#define MM_ATC_L2_CNTL__NUMBER_OF_HOST_TRANSLATION_WRITES_DEPENDS_ON_ADDR_MOD__SHIFT 0xb +#define MM_ATC_L2_CNTL__CACHE_INVALIDATE_MODE__SHIFT 0xc +#define MM_ATC_L2_CNTL__FRAG_APT_INTXN_MODE__SHIFT 0xf +#define MM_ATC_L2_CNTL__CLI_GPA_REQ_FRAG_SIZE__SHIFT 0x11 +#define MM_ATC_L2_CNTL__NUMBER_OF_TRANSLATION_READ_REQUESTS_MASK 0x00000003L +#define MM_ATC_L2_CNTL__NUMBER_OF_TRANSLATION_WRITE_REQUESTS_MASK 0x0000000CL +#define MM_ATC_L2_CNTL__NUMBER_OF_TRANSLATION_READS_DEPENDS_ON_ADDR_MOD_MASK 0x00000010L +#define MM_ATC_L2_CNTL__NUMBER_OF_TRANSLATION_WRITES_DEPENDS_ON_ADDR_MOD_MASK 0x00000020L +#define MM_ATC_L2_CNTL__NUMBER_OF_HOST_TRANSLATION_READ_REQUESTS_MASK 0x000000C0L +#define MM_ATC_L2_CNTL__NUMBER_OF_HOST_TRANSLATION_WRITE_REQUESTS_MASK 0x00000300L +#define MM_ATC_L2_CNTL__NUMBER_OF_HOST_TRANSLATION_READS_DEPENDS_ON_ADDR_MOD_MASK 0x00000400L +#define MM_ATC_L2_CNTL__NUMBER_OF_HOST_TRANSLATION_WRITES_DEPENDS_ON_ADDR_MOD_MASK 0x00000800L +#define MM_ATC_L2_CNTL__CACHE_INVALIDATE_MODE_MASK 0x00007000L +#define MM_ATC_L2_CNTL__FRAG_APT_INTXN_MODE_MASK 0x00018000L +#define MM_ATC_L2_CNTL__CLI_GPA_REQ_FRAG_SIZE_MASK 0x007E0000L +//MM_ATC_L2_CNTL2 +#define MM_ATC_L2_CNTL2__BANK_SELECT__SHIFT 0x0 +#define MM_ATC_L2_CNTL2__NUM_BANKS_LOG2__SHIFT 0x6 +#define MM_ATC_L2_CNTL2__L2_CACHE_UPDATE_MODE__SHIFT 0x9 +#define MM_ATC_L2_CNTL2__ENABLE_L2_CACHE_LRU_UPDATE_BY_WRITE__SHIFT 0xb +#define MM_ATC_L2_CNTL2__L2_CACHE_SWAP_TAG_INDEX_LSBS__SHIFT 0xc +#define MM_ATC_L2_CNTL2__BANK_SELECT_MASK 0x0000003FL +#define MM_ATC_L2_CNTL2__NUM_BANKS_LOG2_MASK 0x000001C0L +#define MM_ATC_L2_CNTL2__L2_CACHE_UPDATE_MODE_MASK 0x00000600L +#define MM_ATC_L2_CNTL2__ENABLE_L2_CACHE_LRU_UPDATE_BY_WRITE_MASK 0x00000800L +#define MM_ATC_L2_CNTL2__L2_CACHE_SWAP_TAG_INDEX_LSBS_MASK 0x00007000L +//MM_ATC_L2_CACHE_DATA0 +#define MM_ATC_L2_CACHE_DATA0__DATA_REGISTER_VALID__SHIFT 0x0 +#define MM_ATC_L2_CACHE_DATA0__CACHE_ENTRY_VALID__SHIFT 0x1 +#define MM_ATC_L2_CACHE_DATA0__CACHED_ATTRIBUTES__SHIFT 0x2 +#define MM_ATC_L2_CACHE_DATA0__DATA_REGISTER_VALID_MASK 0x00000001L +#define MM_ATC_L2_CACHE_DATA0__CACHE_ENTRY_VALID_MASK 0x00000002L +#define MM_ATC_L2_CACHE_DATA0__CACHED_ATTRIBUTES_MASK 0x0003FFFCL +//MM_ATC_L2_CACHE_DATA1 +#define MM_ATC_L2_CACHE_DATA1__VIRTUAL_PAGE_ADDRESS_LOW__SHIFT 0x0 +#define MM_ATC_L2_CACHE_DATA1__VIRTUAL_PAGE_ADDRESS_LOW_MASK 0xFFFFFFFFL +//MM_ATC_L2_CACHE_DATA2 +#define MM_ATC_L2_CACHE_DATA2__PHYSICAL_PAGE_ADDRESS__SHIFT 0x0 +#define MM_ATC_L2_CACHE_DATA2__PHYSICAL_PAGE_ADDRESS_MASK 0xFFFFFFFFL +//MM_ATC_L2_CNTL3 +#define MM_ATC_L2_CNTL3__L2_SMALLK_CACHE_FRAGMENT_SIZE__SHIFT 0x0 +#define MM_ATC_L2_CNTL3__L2_BIGK_CACHE_FRAGMENT_SIZE__SHIFT 0x6 +#define MM_ATC_L2_CNTL3__DELAY_SEND_INVALIDATION_REQUEST__SHIFT 0xc +#define MM_ATC_L2_CNTL3__ATS_REQUEST_CREDIT_MINUS1__SHIFT 0xf +#define MM_ATC_L2_CNTL3__COMPCLKREQ_OFF_HYSTERESIS__SHIFT 0x15 +#define MM_ATC_L2_CNTL3__REPEATER_FGCG_OFF__SHIFT 0x18 +#define MM_ATC_L2_CNTL3__L2_SMALLK_CACHE_FRAGMENT_SIZE_MASK 0x0000003FL +#define MM_ATC_L2_CNTL3__L2_BIGK_CACHE_FRAGMENT_SIZE_MASK 0x00000FC0L +#define MM_ATC_L2_CNTL3__DELAY_SEND_INVALIDATION_REQUEST_MASK 0x00007000L +#define MM_ATC_L2_CNTL3__ATS_REQUEST_CREDIT_MINUS1_MASK 0x001F8000L +#define MM_ATC_L2_CNTL3__COMPCLKREQ_OFF_HYSTERESIS_MASK 0x00E00000L +#define MM_ATC_L2_CNTL3__REPEATER_FGCG_OFF_MASK 0x01000000L +//MM_ATC_L2_CNTL4 +#define MM_ATC_L2_CNTL4__L2_RT_SMALLK_CACHE_FRAGMENT_SIZE__SHIFT 0x1 +#define MM_ATC_L2_CNTL4__L2_RT_BIGK_CACHE_FRAGMENT_SIZE__SHIFT 0x7 +#define MM_ATC_L2_CNTL4__L2_RT_SMALLK_CACHE_FRAGMENT_SIZE_MASK 0x0000007EL +#define MM_ATC_L2_CNTL4__L2_RT_BIGK_CACHE_FRAGMENT_SIZE_MASK 0x00001F80L +//MM_ATC_L2_CNTL5 +#define MM_ATC_L2_CNTL5__MM_NONRT_IFIFO_ACTIVE_TRANSACTION_LIMIT__SHIFT 0x0 +#define MM_ATC_L2_CNTL5__MM_SOFTRT_IFIFO_ACTIVE_TRANSACTION_LIMIT__SHIFT 0xa +#define MM_ATC_L2_CNTL5__MM_NONRT_IFIFO_ACTIVE_TRANSACTION_LIMIT_MASK 0x000003FFL +#define MM_ATC_L2_CNTL5__MM_SOFTRT_IFIFO_ACTIVE_TRANSACTION_LIMIT_MASK 0x000FFC00L +//MM_ATC_L2_MM_GROUP_RT_CLASSES +#define MM_ATC_L2_MM_GROUP_RT_CLASSES__GROUP_RT_CLASS__SHIFT 0x0 +#define MM_ATC_L2_MM_GROUP_RT_CLASSES__GROUP_RT_CLASS_MASK 0xFFFFFFFFL +//MM_ATC_L2_STATUS +#define MM_ATC_L2_STATUS__BUSY__SHIFT 0x0 +#define MM_ATC_L2_STATUS__NO_OUTSTANDING_AT_REQUESTS__SHIFT 0x1 +#define MM_ATC_L2_STATUS__BUSY_MASK 0x00000001L +#define MM_ATC_L2_STATUS__NO_OUTSTANDING_AT_REQUESTS_MASK 0x00000002L +//MM_ATC_L2_MISC_CG +#define MM_ATC_L2_MISC_CG__OFFDLY__SHIFT 0x6 +#define MM_ATC_L2_MISC_CG__ENABLE__SHIFT 0x12 +#define MM_ATC_L2_MISC_CG__MEM_LS_ENABLE__SHIFT 0x13 +#define MM_ATC_L2_MISC_CG__OFFDLY_MASK 0x00000FC0L +#define MM_ATC_L2_MISC_CG__ENABLE_MASK 0x00040000L +#define MM_ATC_L2_MISC_CG__MEM_LS_ENABLE_MASK 0x00080000L +//MM_ATC_L2_CGTT_CLK_CTRL +#define MM_ATC_L2_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 +#define MM_ATC_L2_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x5 +#define MM_ATC_L2_CGTT_CLK_CTRL__LS_ASSERT_HYSTERESIS__SHIFT 0xd +#define MM_ATC_L2_CGTT_CLK_CTRL__MIN_MGLS__SHIFT 0x1a +#define MM_ATC_L2_CGTT_CLK_CTRL__CGLS_DISABLE__SHIFT 0x1d +#define MM_ATC_L2_CGTT_CLK_CTRL__LS_DISABLE__SHIFT 0x1e +#define MM_ATC_L2_CGTT_CLK_CTRL__BUSY_OVERRIDE__SHIFT 0x1f +#define MM_ATC_L2_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000001FL +#define MM_ATC_L2_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00001FE0L +#define MM_ATC_L2_CGTT_CLK_CTRL__LS_ASSERT_HYSTERESIS_MASK 0x03FFE000L +#define MM_ATC_L2_CGTT_CLK_CTRL__MIN_MGLS_MASK 0x1C000000L +#define MM_ATC_L2_CGTT_CLK_CTRL__CGLS_DISABLE_MASK 0x20000000L +#define MM_ATC_L2_CGTT_CLK_CTRL__LS_DISABLE_MASK 0x40000000L +#define MM_ATC_L2_CGTT_CLK_CTRL__BUSY_OVERRIDE_MASK 0x80000000L +//MM_ATC_L2_SDPPORT_CTRL +#define MM_ATC_L2_SDPPORT_CTRL__SDPVDCI_RDRSPCKEN__SHIFT 0x0 +#define MM_ATC_L2_SDPPORT_CTRL__SDPVDCI_RDRSPCKENRCV__SHIFT 0x1 +#define MM_ATC_L2_SDPPORT_CTRL__SDPVDCI_RDRSPDATACKEN__SHIFT 0x2 +#define MM_ATC_L2_SDPPORT_CTRL__SDPVDCI_RDRSPDATACKENRCV__SHIFT 0x3 +#define MM_ATC_L2_SDPPORT_CTRL__SDPVDCI_WRRSPCKEN__SHIFT 0x4 +#define MM_ATC_L2_SDPPORT_CTRL__SDPVDCI_WRRSPCKENRCV__SHIFT 0x5 +#define MM_ATC_L2_SDPPORT_CTRL__SDPVDCI_REQCKEN__SHIFT 0x6 +#define MM_ATC_L2_SDPPORT_CTRL__SDPVDCI_REQCKENRCV__SHIFT 0x7 +#define MM_ATC_L2_SDPPORT_CTRL__SDPVDCI_ORIGDATACKEN__SHIFT 0x8 +#define MM_ATC_L2_SDPPORT_CTRL__SDPVDCI_ORIGDATACKENRCV__SHIFT 0x9 +#define MM_ATC_L2_SDPPORT_CTRL__SDPVDCI_RDRSPCKEN_MASK 0x00000001L +#define MM_ATC_L2_SDPPORT_CTRL__SDPVDCI_RDRSPCKENRCV_MASK 0x00000002L +#define MM_ATC_L2_SDPPORT_CTRL__SDPVDCI_RDRSPDATACKEN_MASK 0x00000004L +#define MM_ATC_L2_SDPPORT_CTRL__SDPVDCI_RDRSPDATACKENRCV_MASK 0x00000008L +#define MM_ATC_L2_SDPPORT_CTRL__SDPVDCI_WRRSPCKEN_MASK 0x00000010L +#define MM_ATC_L2_SDPPORT_CTRL__SDPVDCI_WRRSPCKENRCV_MASK 0x00000020L +#define MM_ATC_L2_SDPPORT_CTRL__SDPVDCI_REQCKEN_MASK 0x00000040L +#define MM_ATC_L2_SDPPORT_CTRL__SDPVDCI_REQCKENRCV_MASK 0x00000080L +#define MM_ATC_L2_SDPPORT_CTRL__SDPVDCI_ORIGDATACKEN_MASK 0x00000100L +#define MM_ATC_L2_SDPPORT_CTRL__SDPVDCI_ORIGDATACKENRCV_MASK 0x00000200L + + +// addressBlock: mmhub_mmutcl2_mmvml2pspdec +//MMUTCL2_TRANSLATION_BYPASS_BY_VMID +#define MMUTCL2_TRANSLATION_BYPASS_BY_VMID__TRANS_BYPASS_VMIDS__SHIFT 0x0 +#define MMUTCL2_TRANSLATION_BYPASS_BY_VMID__GPA_MODE_VMIDS__SHIFT 0x10 +#define MMUTCL2_TRANSLATION_BYPASS_BY_VMID__TRANS_BYPASS_VMIDS_MASK 0x0000FFFFL +#define MMUTCL2_TRANSLATION_BYPASS_BY_VMID__GPA_MODE_VMIDS_MASK 0xFFFF0000L +//MMVM_IOMMU_GPU_HOST_TRANSLATION_ENABLE +#define MMVM_IOMMU_GPU_HOST_TRANSLATION_ENABLE__GPU_HOST_TRANSLATION_ENABLE__SHIFT 0x0 +#define MMVM_IOMMU_GPU_HOST_TRANSLATION_ENABLE__GPU_HOST_TRANSLATION_ENABLE_MASK 0x00000001L +//MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_CNTL +#define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_CNTL__ENABLE__SHIFT 0x0 +#define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_CNTL__ENABLE_MASK 0x00000001L +//MMVM_IOMMU_CONTROL_REGISTER +#define MMVM_IOMMU_CONTROL_REGISTER__IOMMUEN__SHIFT 0x0 +#define MMVM_IOMMU_CONTROL_REGISTER__IOMMUEN_MASK 0x00000001L +//MMVM_IOMMU_PERFORMANCE_OPTIMIZATION_CONTROL_REGISTER +#define MMVM_IOMMU_PERFORMANCE_OPTIMIZATION_CONTROL_REGISTER__PERFOPTEN__SHIFT 0xd +#define MMVM_IOMMU_PERFORMANCE_OPTIMIZATION_CONTROL_REGISTER__PERFOPTEN_MASK 0x00002000L +//MMUTC_TRANSLATION_FAULT_CNTL0 +#define MMUTC_TRANSLATION_FAULT_CNTL0__DEFAULT_PHYSICAL_PAGE_ADDRESS_LSB__SHIFT 0x0 +#define MMUTC_TRANSLATION_FAULT_CNTL0__DEFAULT_PHYSICAL_PAGE_ADDRESS_LSB_MASK 0xFFFFFFFFL +//MMUTC_TRANSLATION_FAULT_CNTL1 +#define MMUTC_TRANSLATION_FAULT_CNTL1__DEFAULT_PHYSICAL_PAGE_ADDRESS_MSB__SHIFT 0x0 +#define MMUTC_TRANSLATION_FAULT_CNTL1__DEFAULT_IO__SHIFT 0x4 +#define MMUTC_TRANSLATION_FAULT_CNTL1__DEFAULT_SPA__SHIFT 0x5 +#define MMUTC_TRANSLATION_FAULT_CNTL1__DEFAULT_SNOOP__SHIFT 0x6 +#define MMUTC_TRANSLATION_FAULT_CNTL1__DEFAULT_HDM__SHIFT 0x7 +#define MMUTC_TRANSLATION_FAULT_CNTL1__DEFAULT_PHYSICAL_PAGE_ADDRESS_MSB_MASK 0x0000000FL +#define MMUTC_TRANSLATION_FAULT_CNTL1__DEFAULT_IO_MASK 0x00000010L +#define MMUTC_TRANSLATION_FAULT_CNTL1__DEFAULT_SPA_MASK 0x00000020L +#define MMUTC_TRANSLATION_FAULT_CNTL1__DEFAULT_SNOOP_MASK 0x00000040L +#define MMUTC_TRANSLATION_FAULT_CNTL1__DEFAULT_HDM_MASK 0x00000080L +//MMUTCL2_FFBM_ENABLE_CNTL +#define MMUTCL2_FFBM_ENABLE_CNTL__ENABLE_FFBM__SHIFT 0x0 +#define MMUTCL2_FFBM_ENABLE_CNTL__ENABLE_FFBM_MASK 0x00000001L +//MMUTCL2_VSCH_POWER_STATUS +#define MMUTCL2_VSCH_POWER_STATUS__POWERED_DOWN__SHIFT 0x0 +#define MMUTCL2_VSCH_POWER_STATUS__POWERED_DOWN_MASK 0x00000001L + + +// addressBlock: mmhub_mmutcl2_mmvmsharedpspdec +//MMMC_VM_FB_SIZE_OFFSET_VF0 +#define MMMC_VM_FB_SIZE_OFFSET_VF0__VF_FB_SIZE__SHIFT 0x0 +#define MMMC_VM_FB_SIZE_OFFSET_VF0__VF_FB_OFFSET__SHIFT 0x10 +#define MMMC_VM_FB_SIZE_OFFSET_VF0__VF_FB_SIZE_MASK 0x0000FFFFL +#define MMMC_VM_FB_SIZE_OFFSET_VF0__VF_FB_OFFSET_MASK 0xFFFF0000L +//MMMC_VM_FB_SIZE_OFFSET_VF1 +#define MMMC_VM_FB_SIZE_OFFSET_VF1__VF_FB_SIZE__SHIFT 0x0 +#define MMMC_VM_FB_SIZE_OFFSET_VF1__VF_FB_OFFSET__SHIFT 0x10 +#define MMMC_VM_FB_SIZE_OFFSET_VF1__VF_FB_SIZE_MASK 0x0000FFFFL +#define MMMC_VM_FB_SIZE_OFFSET_VF1__VF_FB_OFFSET_MASK 0xFFFF0000L +//MMMC_VM_FB_SIZE_OFFSET_VF2 +#define MMMC_VM_FB_SIZE_OFFSET_VF2__VF_FB_SIZE__SHIFT 0x0 +#define MMMC_VM_FB_SIZE_OFFSET_VF2__VF_FB_OFFSET__SHIFT 0x10 +#define MMMC_VM_FB_SIZE_OFFSET_VF2__VF_FB_SIZE_MASK 0x0000FFFFL +#define MMMC_VM_FB_SIZE_OFFSET_VF2__VF_FB_OFFSET_MASK 0xFFFF0000L +//MMMC_VM_FB_SIZE_OFFSET_VF3 +#define MMMC_VM_FB_SIZE_OFFSET_VF3__VF_FB_SIZE__SHIFT 0x0 +#define MMMC_VM_FB_SIZE_OFFSET_VF3__VF_FB_OFFSET__SHIFT 0x10 +#define MMMC_VM_FB_SIZE_OFFSET_VF3__VF_FB_SIZE_MASK 0x0000FFFFL +#define MMMC_VM_FB_SIZE_OFFSET_VF3__VF_FB_OFFSET_MASK 0xFFFF0000L +//MMMC_VM_FB_SIZE_OFFSET_VF4 +#define MMMC_VM_FB_SIZE_OFFSET_VF4__VF_FB_SIZE__SHIFT 0x0 +#define MMMC_VM_FB_SIZE_OFFSET_VF4__VF_FB_OFFSET__SHIFT 0x10 +#define MMMC_VM_FB_SIZE_OFFSET_VF4__VF_FB_SIZE_MASK 0x0000FFFFL +#define MMMC_VM_FB_SIZE_OFFSET_VF4__VF_FB_OFFSET_MASK 0xFFFF0000L +//MMMC_VM_FB_SIZE_OFFSET_VF5 +#define MMMC_VM_FB_SIZE_OFFSET_VF5__VF_FB_SIZE__SHIFT 0x0 +#define MMMC_VM_FB_SIZE_OFFSET_VF5__VF_FB_OFFSET__SHIFT 0x10 +#define MMMC_VM_FB_SIZE_OFFSET_VF5__VF_FB_SIZE_MASK 0x0000FFFFL +#define MMMC_VM_FB_SIZE_OFFSET_VF5__VF_FB_OFFSET_MASK 0xFFFF0000L +//MMMC_VM_FB_SIZE_OFFSET_VF6 +#define MMMC_VM_FB_SIZE_OFFSET_VF6__VF_FB_SIZE__SHIFT 0x0 +#define MMMC_VM_FB_SIZE_OFFSET_VF6__VF_FB_OFFSET__SHIFT 0x10 +#define MMMC_VM_FB_SIZE_OFFSET_VF6__VF_FB_SIZE_MASK 0x0000FFFFL +#define MMMC_VM_FB_SIZE_OFFSET_VF6__VF_FB_OFFSET_MASK 0xFFFF0000L +//MMMC_VM_FB_SIZE_OFFSET_VF7 +#define MMMC_VM_FB_SIZE_OFFSET_VF7__VF_FB_SIZE__SHIFT 0x0 +#define MMMC_VM_FB_SIZE_OFFSET_VF7__VF_FB_OFFSET__SHIFT 0x10 +#define MMMC_VM_FB_SIZE_OFFSET_VF7__VF_FB_SIZE_MASK 0x0000FFFFL +#define MMMC_VM_FB_SIZE_OFFSET_VF7__VF_FB_OFFSET_MASK 0xFFFF0000L +//MMMC_VM_FB_SIZE_OFFSET_VF8 +#define MMMC_VM_FB_SIZE_OFFSET_VF8__VF_FB_SIZE__SHIFT 0x0 +#define MMMC_VM_FB_SIZE_OFFSET_VF8__VF_FB_OFFSET__SHIFT 0x10 +#define MMMC_VM_FB_SIZE_OFFSET_VF8__VF_FB_SIZE_MASK 0x0000FFFFL +#define MMMC_VM_FB_SIZE_OFFSET_VF8__VF_FB_OFFSET_MASK 0xFFFF0000L +//MMMC_VM_FB_SIZE_OFFSET_VF9 +#define MMMC_VM_FB_SIZE_OFFSET_VF9__VF_FB_SIZE__SHIFT 0x0 +#define MMMC_VM_FB_SIZE_OFFSET_VF9__VF_FB_OFFSET__SHIFT 0x10 +#define MMMC_VM_FB_SIZE_OFFSET_VF9__VF_FB_SIZE_MASK 0x0000FFFFL +#define MMMC_VM_FB_SIZE_OFFSET_VF9__VF_FB_OFFSET_MASK 0xFFFF0000L +//MMMC_VM_FB_SIZE_OFFSET_VF10 +#define MMMC_VM_FB_SIZE_OFFSET_VF10__VF_FB_SIZE__SHIFT 0x0 +#define MMMC_VM_FB_SIZE_OFFSET_VF10__VF_FB_OFFSET__SHIFT 0x10 +#define MMMC_VM_FB_SIZE_OFFSET_VF10__VF_FB_SIZE_MASK 0x0000FFFFL +#define MMMC_VM_FB_SIZE_OFFSET_VF10__VF_FB_OFFSET_MASK 0xFFFF0000L +//MMMC_VM_FB_SIZE_OFFSET_VF11 +#define MMMC_VM_FB_SIZE_OFFSET_VF11__VF_FB_SIZE__SHIFT 0x0 +#define MMMC_VM_FB_SIZE_OFFSET_VF11__VF_FB_OFFSET__SHIFT 0x10 +#define MMMC_VM_FB_SIZE_OFFSET_VF11__VF_FB_SIZE_MASK 0x0000FFFFL +#define MMMC_VM_FB_SIZE_OFFSET_VF11__VF_FB_OFFSET_MASK 0xFFFF0000L +//MMMC_VM_FB_SIZE_OFFSET_VF12 +#define MMMC_VM_FB_SIZE_OFFSET_VF12__VF_FB_SIZE__SHIFT 0x0 +#define MMMC_VM_FB_SIZE_OFFSET_VF12__VF_FB_OFFSET__SHIFT 0x10 +#define MMMC_VM_FB_SIZE_OFFSET_VF12__VF_FB_SIZE_MASK 0x0000FFFFL +#define MMMC_VM_FB_SIZE_OFFSET_VF12__VF_FB_OFFSET_MASK 0xFFFF0000L +//MMMC_VM_FB_SIZE_OFFSET_VF13 +#define MMMC_VM_FB_SIZE_OFFSET_VF13__VF_FB_SIZE__SHIFT 0x0 +#define MMMC_VM_FB_SIZE_OFFSET_VF13__VF_FB_OFFSET__SHIFT 0x10 +#define MMMC_VM_FB_SIZE_OFFSET_VF13__VF_FB_SIZE_MASK 0x0000FFFFL +#define MMMC_VM_FB_SIZE_OFFSET_VF13__VF_FB_OFFSET_MASK 0xFFFF0000L +//MMMC_VM_FB_SIZE_OFFSET_VF14 +#define MMMC_VM_FB_SIZE_OFFSET_VF14__VF_FB_SIZE__SHIFT 0x0 +#define MMMC_VM_FB_SIZE_OFFSET_VF14__VF_FB_OFFSET__SHIFT 0x10 +#define MMMC_VM_FB_SIZE_OFFSET_VF14__VF_FB_SIZE_MASK 0x0000FFFFL +#define MMMC_VM_FB_SIZE_OFFSET_VF14__VF_FB_OFFSET_MASK 0xFFFF0000L +//MMMC_VM_FB_SIZE_OFFSET_VF15 +#define MMMC_VM_FB_SIZE_OFFSET_VF15__VF_FB_SIZE__SHIFT 0x0 +#define MMMC_VM_FB_SIZE_OFFSET_VF15__VF_FB_OFFSET__SHIFT 0x10 +#define MMMC_VM_FB_SIZE_OFFSET_VF15__VF_FB_SIZE_MASK 0x0000FFFFL +#define MMMC_VM_FB_SIZE_OFFSET_VF15__VF_FB_OFFSET_MASK 0xFFFF0000L +//MMMC_VM_FB_SIZE_OFFSET_VF16 +#define MMMC_VM_FB_SIZE_OFFSET_VF16__VF_FB_SIZE__SHIFT 0x0 +#define MMMC_VM_FB_SIZE_OFFSET_VF16__VF_FB_OFFSET__SHIFT 0x10 +#define MMMC_VM_FB_SIZE_OFFSET_VF16__VF_FB_SIZE_MASK 0x0000FFFFL +#define MMMC_VM_FB_SIZE_OFFSET_VF16__VF_FB_OFFSET_MASK 0xFFFF0000L +//MMMC_VM_FB_SIZE_OFFSET_VF17 +#define MMMC_VM_FB_SIZE_OFFSET_VF17__VF_FB_SIZE__SHIFT 0x0 +#define MMMC_VM_FB_SIZE_OFFSET_VF17__VF_FB_OFFSET__SHIFT 0x10 +#define MMMC_VM_FB_SIZE_OFFSET_VF17__VF_FB_SIZE_MASK 0x0000FFFFL +#define MMMC_VM_FB_SIZE_OFFSET_VF17__VF_FB_OFFSET_MASK 0xFFFF0000L +//MMMC_VM_FB_SIZE_OFFSET_VF18 +#define MMMC_VM_FB_SIZE_OFFSET_VF18__VF_FB_SIZE__SHIFT 0x0 +#define MMMC_VM_FB_SIZE_OFFSET_VF18__VF_FB_OFFSET__SHIFT 0x10 +#define MMMC_VM_FB_SIZE_OFFSET_VF18__VF_FB_SIZE_MASK 0x0000FFFFL +#define MMMC_VM_FB_SIZE_OFFSET_VF18__VF_FB_OFFSET_MASK 0xFFFF0000L +//MMMC_VM_FB_SIZE_OFFSET_VF19 +#define MMMC_VM_FB_SIZE_OFFSET_VF19__VF_FB_SIZE__SHIFT 0x0 +#define MMMC_VM_FB_SIZE_OFFSET_VF19__VF_FB_OFFSET__SHIFT 0x10 +#define MMMC_VM_FB_SIZE_OFFSET_VF19__VF_FB_SIZE_MASK 0x0000FFFFL +#define MMMC_VM_FB_SIZE_OFFSET_VF19__VF_FB_OFFSET_MASK 0xFFFF0000L +//MMMC_VM_FB_SIZE_OFFSET_VF20 +#define MMMC_VM_FB_SIZE_OFFSET_VF20__VF_FB_SIZE__SHIFT 0x0 +#define MMMC_VM_FB_SIZE_OFFSET_VF20__VF_FB_OFFSET__SHIFT 0x10 +#define MMMC_VM_FB_SIZE_OFFSET_VF20__VF_FB_SIZE_MASK 0x0000FFFFL +#define MMMC_VM_FB_SIZE_OFFSET_VF20__VF_FB_OFFSET_MASK 0xFFFF0000L +//MMMC_VM_FB_SIZE_OFFSET_VF21 +#define MMMC_VM_FB_SIZE_OFFSET_VF21__VF_FB_SIZE__SHIFT 0x0 +#define MMMC_VM_FB_SIZE_OFFSET_VF21__VF_FB_OFFSET__SHIFT 0x10 +#define MMMC_VM_FB_SIZE_OFFSET_VF21__VF_FB_SIZE_MASK 0x0000FFFFL +#define MMMC_VM_FB_SIZE_OFFSET_VF21__VF_FB_OFFSET_MASK 0xFFFF0000L +//MMMC_VM_FB_SIZE_OFFSET_VF22 +#define MMMC_VM_FB_SIZE_OFFSET_VF22__VF_FB_SIZE__SHIFT 0x0 +#define MMMC_VM_FB_SIZE_OFFSET_VF22__VF_FB_OFFSET__SHIFT 0x10 +#define MMMC_VM_FB_SIZE_OFFSET_VF22__VF_FB_SIZE_MASK 0x0000FFFFL +#define MMMC_VM_FB_SIZE_OFFSET_VF22__VF_FB_OFFSET_MASK 0xFFFF0000L +//MMMC_VM_FB_SIZE_OFFSET_VF23 +#define MMMC_VM_FB_SIZE_OFFSET_VF23__VF_FB_SIZE__SHIFT 0x0 +#define MMMC_VM_FB_SIZE_OFFSET_VF23__VF_FB_OFFSET__SHIFT 0x10 +#define MMMC_VM_FB_SIZE_OFFSET_VF23__VF_FB_SIZE_MASK 0x0000FFFFL +#define MMMC_VM_FB_SIZE_OFFSET_VF23__VF_FB_OFFSET_MASK 0xFFFF0000L +//MMMC_VM_FB_SIZE_OFFSET_VF24 +#define MMMC_VM_FB_SIZE_OFFSET_VF24__VF_FB_SIZE__SHIFT 0x0 +#define MMMC_VM_FB_SIZE_OFFSET_VF24__VF_FB_OFFSET__SHIFT 0x10 +#define MMMC_VM_FB_SIZE_OFFSET_VF24__VF_FB_SIZE_MASK 0x0000FFFFL +#define MMMC_VM_FB_SIZE_OFFSET_VF24__VF_FB_OFFSET_MASK 0xFFFF0000L +//MMMC_VM_FB_SIZE_OFFSET_VF25 +#define MMMC_VM_FB_SIZE_OFFSET_VF25__VF_FB_SIZE__SHIFT 0x0 +#define MMMC_VM_FB_SIZE_OFFSET_VF25__VF_FB_OFFSET__SHIFT 0x10 +#define MMMC_VM_FB_SIZE_OFFSET_VF25__VF_FB_SIZE_MASK 0x0000FFFFL +#define MMMC_VM_FB_SIZE_OFFSET_VF25__VF_FB_OFFSET_MASK 0xFFFF0000L +//MMMC_VM_FB_SIZE_OFFSET_VF26 +#define MMMC_VM_FB_SIZE_OFFSET_VF26__VF_FB_SIZE__SHIFT 0x0 +#define MMMC_VM_FB_SIZE_OFFSET_VF26__VF_FB_OFFSET__SHIFT 0x10 +#define MMMC_VM_FB_SIZE_OFFSET_VF26__VF_FB_SIZE_MASK 0x0000FFFFL +#define MMMC_VM_FB_SIZE_OFFSET_VF26__VF_FB_OFFSET_MASK 0xFFFF0000L +//MMMC_VM_FB_SIZE_OFFSET_VF27 +#define MMMC_VM_FB_SIZE_OFFSET_VF27__VF_FB_SIZE__SHIFT 0x0 +#define MMMC_VM_FB_SIZE_OFFSET_VF27__VF_FB_OFFSET__SHIFT 0x10 +#define MMMC_VM_FB_SIZE_OFFSET_VF27__VF_FB_SIZE_MASK 0x0000FFFFL +#define MMMC_VM_FB_SIZE_OFFSET_VF27__VF_FB_OFFSET_MASK 0xFFFF0000L +//MMMC_VM_FB_SIZE_OFFSET_VF28 +#define MMMC_VM_FB_SIZE_OFFSET_VF28__VF_FB_SIZE__SHIFT 0x0 +#define MMMC_VM_FB_SIZE_OFFSET_VF28__VF_FB_OFFSET__SHIFT 0x10 +#define MMMC_VM_FB_SIZE_OFFSET_VF28__VF_FB_SIZE_MASK 0x0000FFFFL +#define MMMC_VM_FB_SIZE_OFFSET_VF28__VF_FB_OFFSET_MASK 0xFFFF0000L +//MMMC_VM_FB_SIZE_OFFSET_VF29 +#define MMMC_VM_FB_SIZE_OFFSET_VF29__VF_FB_SIZE__SHIFT 0x0 +#define MMMC_VM_FB_SIZE_OFFSET_VF29__VF_FB_OFFSET__SHIFT 0x10 +#define MMMC_VM_FB_SIZE_OFFSET_VF29__VF_FB_SIZE_MASK 0x0000FFFFL +#define MMMC_VM_FB_SIZE_OFFSET_VF29__VF_FB_OFFSET_MASK 0xFFFF0000L +//MMMC_VM_FB_SIZE_OFFSET_VF30 +#define MMMC_VM_FB_SIZE_OFFSET_VF30__VF_FB_SIZE__SHIFT 0x0 +#define MMMC_VM_FB_SIZE_OFFSET_VF30__VF_FB_OFFSET__SHIFT 0x10 +#define MMMC_VM_FB_SIZE_OFFSET_VF30__VF_FB_SIZE_MASK 0x0000FFFFL +#define MMMC_VM_FB_SIZE_OFFSET_VF30__VF_FB_OFFSET_MASK 0xFFFF0000L //MMMC_VM_FB_OFFSET #define MMMC_VM_FB_OFFSET__FB_OFFSET__SHIFT 0x0 #define MMMC_VM_FB_OFFSET__FB_OFFSET_MASK 0x00FFFFFFL +//MMMC_VM_LOCAL_FB_ADDRESS_START +#define MMMC_VM_LOCAL_FB_ADDRESS_START__ADDRESS__SHIFT 0x0 +#define MMMC_VM_LOCAL_FB_ADDRESS_START__ADDRESS_MASK 0x00FFFFFFL +//MMMC_VM_LOCAL_FB_ADDRESS_END +#define MMMC_VM_LOCAL_FB_ADDRESS_END__ADDRESS__SHIFT 0x0 +#define MMMC_VM_LOCAL_FB_ADDRESS_END__ADDRESS_MASK 0x00FFFFFFL +//MMMC_VM_LOCAL_FB_ADDRESS_LOCK_CNTL +#define MMMC_VM_LOCAL_FB_ADDRESS_LOCK_CNTL__LOCK__SHIFT 0x0 +#define MMMC_VM_LOCAL_FB_ADDRESS_LOCK_CNTL__LOCK_MASK 0x00000001L + + +// addressBlock: mmhub_mmutcl2_mmutcl2ffbmpspdec +//MMUTCL2_FFBM_CONFIG +#define MMUTCL2_FFBM_CONFIG__TLB_PAGE_SIZE__SHIFT 0x0 +#define MMUTCL2_FFBM_CONFIG__DBITIGNOREPERMISSIONS__SHIFT 0x8 +#define MMUTCL2_FFBM_CONFIG__TLB_PAGE_SIZE_MASK 0x0000003FL +#define MMUTCL2_FFBM_CONFIG__DBITIGNOREPERMISSIONS_MASK 0x00000100L +//MMUTCL2_FFBM_ACCESS_CNTL +#define MMUTCL2_FFBM_ACCESS_CNTL__TLB_ACCESS_REQUEST__SHIFT 0x0 +#define MMUTCL2_FFBM_ACCESS_CNTL__TLB_ACCESS_GRANT__SHIFT 0x1 +#define MMUTCL2_FFBM_ACCESS_CNTL__TLB_ACCESS_REQUEST_MASK 0x00000001L +#define MMUTCL2_FFBM_ACCESS_CNTL__TLB_ACCESS_GRANT_MASK 0x00000002L +//MMUTCL2_FFBM_INVALIDATE_RESPONSE +#define MMUTCL2_FFBM_INVALIDATE_RESPONSE__NON_FLUSHTYPE_INVALIDATE_ACK__SHIFT 0x0 +#define MMUTCL2_FFBM_INVALIDATE_RESPONSE__FLUSHTYPE_INVALIDATE_ACK__SHIFT 0x1 +#define MMUTCL2_FFBM_INVALIDATE_RESPONSE__PF_INVALIDATE_ACK__SHIFT 0x2 +#define MMUTCL2_FFBM_INVALIDATE_RESPONSE__NON_FLUSHTYPE_INVALIDATE_ACK_MASK 0x00000001L +#define MMUTCL2_FFBM_INVALIDATE_RESPONSE__FLUSHTYPE_INVALIDATE_ACK_MASK 0x00000002L +#define MMUTCL2_FFBM_INVALIDATE_RESPONSE__PF_INVALIDATE_ACK_MASK 0x00000004L + #endif