drm/i915/wm: Allow SAGV with multiple pipes on pre-icl

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There was never any documented reason for limiting SAGV to
single active pipe configuration on pre-icl. Allow SAGV
with multiple active pipes.

At least my CFL NUC seems happy with this when using
multiple displays. The machine actually has working
SAGV because the memory clock can be observed changing
via SA_PERF_STATUS/mchbar:0x5918.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patch.msgid.link/20260324134843.2364-10-ville.syrjala@linux.intel.com
Reviewed-by: Vinod Govindapillai <vinod.govindapillai@intel.com>

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Ville Syrjälä 2026-03-24 15:48:43 +02:00

parent 29865dd7f3

commit 77ce3160ee

1 changed files with 0 additions and 40 deletions

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drivers/gpu/drm/i915/display/intel_bw.c

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