RISC-V: KVM: Implement guest external interrupt line management

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The RISC-V host will have one guest external interrupt line for each
VS-level IMSICs associated with a HART. The guest external interrupt
lines are per-HART resources and hypervisor can use HGEIE, HGEIP, and
HIE CSRs to manage these guest external interrupt lines.

Signed-off-by: Anup Patel <apatel@ventanamicro.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Reviewed-by: Atish Patra <atishp@rivosinc.com>
Signed-off-by: Anup Patel <anup@brainfault.org>

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Anup Patel 2023-06-15 13:03:44 +05:30 • committed by Anup Patel

parent 95c99104cb

commit 77cf33c171

4 changed files with 258 additions and 1 deletions

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10

arch/riscv/include/asm/kvm_aia.h

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244

arch/riscv/kvm/aia.c

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3

arch/riscv/kvm/main.c

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2

arch/riscv/kvm/vcpu.c

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