clk: imx8mp: Define gates for pll1/2 fixed dividers

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Inspried from
commit e8688fe8df ("clk: imx8mn: Define gates for pll1/2 fixed dividers")

On imx8mp there are 9 fixed-factor dividers for SYS_PLL1 and SYS_PLL2
each with their own gate. Only one of these gates (the one "dividing" by
one) is currently defined and it's incorrectly set as the parent of all
the fixed-factor dividers.

Add the other 8 gates to the clock tree between sys_pll1/2_bypass and
the fixed dividers.

Reviewed-by: Dong Aisheng <aisheng.dong@nxp.com>
Reviewed-by: Leonard Crestez <leonard.crestez@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>

...

This commit is contained in:

Peng Fan 2020-05-07 13:56:13 +08:00 • committed by Shawn Guo

parent dc6e21da34

commit 77f5d2d973

2 changed files with 54 additions and 19 deletions

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54

drivers/clk/imx/clk-imx8mp.c

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19

include/dt-bindings/clock/imx8mp-clock.h

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