MIPS: Sync icache for whole exception vector

Browse source

Rather than performing cache flushing for a fixed 0x400 bytes, use the
actual size of the vector in order to ensure we cover all emitted code
on systems that make use of vectored interrupts.

Signed-off-by: Paul Burton <paul.burton@mips.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Serge Semin <fancer.lancer@gmail.com>
Tested-by: Serge Semin <fancer.lancer@gmail.com>
Cc: linux-mips@vger.kernel.org

...

This commit is contained in:

Paul Burton 2019-04-30 22:53:31 +00:00

parent 172dcd935c

commit 783454e2bc

No known key found for this signature in database

GPG key ID: 3EA79FACB57500DD

1 changed files with 1 additions and 1 deletions

Show all changes Ignore whitespace when comparing lines Ignore changes in amount of whitespace Ignore changes in whitespace at EOL

Download patch file Download diff file Expand all files Collapse all files

2

arch/mips/kernel/traps.c

View file