drm/amd/display: Optimize cursor position updates

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[why]
Updating the cursor enablement register can be a slow operation and accumulates
when high polling rate cursors cause frequent updates asynchronously to the
cursor position.

[how]
Since the cursor enable bit is cached there is no need to update the
enablement register if there is no change to it.  This removes the
read-modify-write from the cursor position programming path in HUBP and
DPP, leaving only the register writes.

Reviewed-by: Josip Pavic <josip.pavic@amd.com>
Signed-off-by: Aric Cyr <Aric.Cyr@amd.com>
Signed-off-by: Roman Li <roman.li@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

...

This commit is contained in:

Aric Cyr 2024-12-10 18:38:15 -05:00 • committed by Alex Deucher

parent de5d7a8802

commit 787e7be0c9

4 changed files with 19 additions and 12 deletions

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7

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.c

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6

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_cm.c

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8

drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

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10

drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c

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