drm/i915/icl: add definitions for the ICL PLL registers

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There's a lot of code for the PLL enabling, so let's first only
introduce the register definitions in order to make patch reviewing a
little easier.

v2: Coding style (Jani).
v3: Preparation for upstreaming.
v4: Fix MG_CLKTOP2_CORECLKCTL1 address and random typos (James).

Cc: James Ausmus <james.ausmus@intel.com>
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Reviewed-by: James Ausmus <james.ausmus@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20180328215803.13835-3-paulo.r.zanoni@intel.com

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Paulo Zanoni 2018-03-28 14:57:57 -07:00

parent 37cde11ba7

commit 78b60ce7b9

1 changed files with 149 additions and 0 deletions

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drivers/gpu/drm/i915/i915_reg.h

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