clk: renesas: r9a07g043: Add clock and reset entries for CRU

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Add CRU clock and reset entries to CPG driver.

CRU_SYSCLK and CRU_VCLK clocks need to be turned ON/OFF in particular
sequence for the CRU block hence add these clocks to
r9a07g043_no_pm_mod_clks[] array and pass it as part of CPG data for
RZ/G2UL SoCs.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/20240123114415.290918-1-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>

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Biju Das 2024-01-23 11:44:15 +00:00 • committed by Geert Uytterhoeven

parent 292d3079ab

commit 78ed252953

1 changed files with 31 additions and 0 deletions

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drivers/clk/renesas/r9a07g043-cpg.c

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