usb: dwc3: core: configure TX/RX threshold for DWC3_IP

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[ Upstream commit e72fc8d6a1 ]

In Synopsys's dwc3 data book:
To avoid underrun and overrun during the burst, in a high-latency bus
system (like USB), threshold and burst size control is provided through
GTXTHRCFG and GRXTHRCFG registers.

In Realtek DHC SoC, DWC3 USB 3.0 uses AHB system bus. When dwc3 is
connected with USB 2.5G Ethernet, there will be overrun problem.
Therefore, setting TX/RX thresholds can avoid this issue.

Signed-off-by: Stanley Chang <stanley_chang@realtek.com>
Acked-by: Thinh Nguyen <Thinh.Nguyen@synopsys.com>
Link: https://lore.kernel.org/r/20230912041904.30721-1-stanley_chang@realtek.com
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Signed-off-by: Sasha Levin <sashal@kernel.org>

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Stanley Chang 2023-09-12 12:19:02 +08:00 • committed by Greg Kroah-Hartman

parent 7cebc86481

commit 7932afa9bb

2 changed files with 137 additions and 36 deletions

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160

drivers/usb/dwc3/core.c

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13

drivers/usb/dwc3/core.h

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