clk: sunxi: unify sun6i AHB1 clock with proper PLL6 pre-divider

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This patch unifies the sun6i AHB1 clock, originally supported
with separate mux and divider clks. It also adds support for
the pre-divider on the PLL6 input, thus allowing the clock to
be muxed to PLL6 with proper clock rate calculation.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>

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Chen-Yu Tsai 2014-11-26 15:16:52 +08:00 • committed by Maxime Ripard

parent 75bd2ec1a6

commit 7954dfaee3

2 changed files with 209 additions and 1 deletions

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2

Documentation/devicetree/bindings/clock/sunxi.txt

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208

drivers/clk/sunxi/clk-sunxi.c

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