clk: tegra: Add the DFLL as a possible parent of the cclk_g clock

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The DFLL clocksource was missing from the list of possible parents for
the fast CPU cluster. Add it to the list.

Signed-off-by: Tuomas Tynkkynen <ttynkkynen@nvidia.com>
Signed-off-by: Mikko Perttunen <mikko.perttunen@kapsi.fi>
Acked-by: Michael Turquette <mturquette@linaro.org>
Signed-off-by: Thierry Reding <treding@nvidia.com>

...

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Tuomas Tynkkynen 2015-05-13 17:58:43 +03:00 • committed by Thierry Reding

parent c38864a703

commit 79cf95c763

1 changed files with 3 additions and 1 deletions

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drivers/clk/tegra/clk-tegra-super-gen4.c

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