RDMA/hns: Fix wrong PBL offset when VA is not aligned to PAGE_SIZE

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ROCE uses "VA % buf_page_size" to caclulate the offset in the PBL's first
page, the actual PA corresponding to the MR's VA is equal to MR's PA plus
this offset. The first PA in PBL has already been aligned to PAGE_SIZE
after calling ib_umem_get(), but the MR's VA may not. If the buf_page_size
is smaller than the PAGE_SIZE, this will lead the HW to access the wrong
memory because the offset is smaller than expected.

Fixes: 9b2cf76c9f ("RDMA/hns: Optimize PBL buffer allocation process")
Link: https://lore.kernel.org/r/1594726935-45666-1-git-send-email-liweihang@huawei.com
Signed-off-by: Xi Wang <wangxi11@huawei.com>
Signed-off-by: Weihang Li <liweihang@huawei.com>
Signed-off-by: Jason Gunthorpe <jgg@nvidia.com>

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Xi Wang 2020-07-14 19:42:15 +08:00 • committed by Jason Gunthorpe

parent 7b9bd73ed1

commit 79d5208386

1 changed files with 1 additions and 1 deletions

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drivers/infiniband/hw/hns/hns_roce_mr.c

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