ARM i.MX6: Fix ethernet PLL clocks

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In current code the ethernet PLL is not handled correctly. The PLL runs at 500MHz
and has different outputs. Only the enet reference clock is implemented. This
patch changes the PLL so that it outputs 500MHz and adds the additional outputs
as dividers. This now matches the datasheet which says:

> This PLL synthesizes a low jitter clock from 24 MHz reference clock.
> The PLL outputs a 500 MHz clock. The reference clocks generated by this PLL are:
>  • Ref_PCIe = 125 MHz
>  • Ref_SATA = 100 MHz
>  • Ref_ethernet, which is configurable based on the PLL_ENET[1:0] register field.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Acked-by: Shawn Guo <shawn.guo@linaro.org>

...

This commit is contained in:

Sascha Hauer 2012-11-21 14:42:31 +01:00

parent 13861701a8

commit 7a04092c73

3 changed files with 25 additions and 63 deletions

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5

Documentation/devicetree/bindings/clock/imx6q-clock.txt

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20

arch/arm/mach-imx/clk-imx6q.c

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63

arch/arm/mach-imx/clk-pllv3.c

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