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Aside from preparation changes in the SPI NAND core, the changes carried

Browse source 
here focus on the shared spi-mem layer which is enhanced in order to
 bring two new features:
 
 - The possibility to fill a primary and a secondary operation template
   in the direct mapping structure in order to support continuous reads
   in SPI NAND, which may require two different read operations.
 
 - SPI controllers may indicate possible CS instabilities over long
   transfers by setting a boolean. This capability is related to the
   previous one, the need for it has arised while testing SPI NAND
   continuous reads with the Cadence QSPI controller which cannot, under
   certain conditions, keep the CS asserted for the length of
   an eraseblock-large transfer.
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Merge tag 'mtd/spi-mem-cont-read-for-7.2' into nand/next

Aside from preparation changes in the SPI NAND core, the changes carried
here focus on the shared spi-mem layer which is enhanced in order to
bring two new features:

- The possibility to fill a primary and a secondary operation template
  in the direct mapping structure in order to support continuous reads
  in SPI NAND, which may require two different read operations.

- SPI controllers may indicate possible CS instabilities over long
  transfers by setting a boolean. This capability is related to the
  previous one, the need for it has arised while testing SPI NAND
  continuous reads with the Cadence QSPI controller which cannot, under
  certain conditions, keep the CS asserted for the length of
  an eraseblock-large transfer.
This commit is contained in:
Miquel Raynal 2026-05-04 15:14:36 +02:00
commit 7a0d420e42
14 changed files with 115 additions and 103 deletions
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