drm/amd/display: Program OTG vtotal min/max selectors unconditionally

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OTG_V_TOTAL_MIN/MAX_SEL bits are required to be programmed to 1 if
writes to OTG timing registers need to be honoured. This is usually
needed only when freesync is active. However, SubVP + DRR requires that
we're able to change timing even without freesync being active (but
supported). By unconditionally writing this bit to 1, we remove an
unnecessary dependency so that DMCUB can change OTG timing whenever it wants.

Signed-off-by: Aurabindo Pillai <aurabindo.pillai@amd.com>
Reviewed-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

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Aurabindo Pillai 2023-03-21 11:31:22 -04:00 • committed by Alex Deucher

parent 5e9252d841

commit 7a1187eab0

1 changed files with 2 additions and 9 deletions

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drivers/gpu/drm/amd/display/dc/dcn32/dcn32_optc.c

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