drm/i915: Make most pre-skl primary plane registers unlocked

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Drop the locks around most primary plane register writes.
The lock isn't needed since each plane's register are neatly
contained on their own cachelines.

The one exception we have to make is DSPADDR/DSPSURF which is
(ab)used to also trigger FBC nukes on pre-snb (since the
hardware doesn't seem to have any dedicated mechanism to
trigger nukes). So we need to keep the lock around it to
protect against the rmw performed by the fbc code.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20220210062403.18690-5-ville.syrjala@linux.intel.com
Reviewed-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>

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This commit is contained in:

Ville Syrjälä 2022-02-10 08:24:02 +02:00

parent 0225a90981

commit 7ad9993b23

1 changed files with 9 additions and 15 deletions

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drivers/gpu/drm/i915/display/i9xx_plane.c

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