KVM: arm64: Normalize cache configuration

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Before this change, the cache configuration of the physical CPU was
exposed to vcpus. This is problematic because the cache configuration a
vcpu sees varies when it migrates between vcpus with different cache
configurations.

Fabricate cache configuration from the sanitized value, which holds the
CTR_EL0 value the userspace sees regardless of which physical CPU it
resides on.

CLIDR_EL1 and CCSIDR_EL1 are now writable from the userspace so that
the VMM can restore the values saved with the old kernel.

Suggested-by: Marc Zyngier <maz@kernel.org>
Signed-off-by: Akihiko Odaki <akihiko.odaki@daynix.com>
Link: https://lore.kernel.org/r/20230112023852.42012-8-akihiko.odaki@daynix.com
[ Oliver: Squash Marc's fix for CCSIDR_EL1.LineSize when set from userspace ]
Signed-off-by: Oliver Upton <oliver.upton@linux.dev>

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This commit is contained in:

Akihiko Odaki 2023-01-12 11:38:52 +09:00 • committed by Oliver Upton

parent bf48040cd9

commit 7af0c2534f

4 changed files with 176 additions and 96 deletions

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3

arch/arm64/include/asm/cache.h

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4

arch/arm64/include/asm/kvm_host.h

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1

arch/arm64/kvm/reset.c

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266

arch/arm64/kvm/sys_regs.c

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