From 12f332d2dd3187472f595b678246adb10d886bd0 Mon Sep 17 00:00:00 2001 From: Hari Prasath Date: Wed, 8 Dec 2021 12:05:53 +0530 Subject: [PATCH 1/6] ARM: dts: at91: update alternate function of signal PD20 The alternate function of PD20 is 4 as per the datasheet of sama7g5 and not 5 as defined earlier. Signed-off-by: Hari Prasath Fixes: 7540629e2fc7 ("ARM: dts: at91: add sama7g5 SoC DT and sama7g5-ek") Cc: # v5.15+ Signed-off-by: Nicolas Ferre Link: https://lore.kernel.org/r/20211208063553.19807-1-Hari.PrasathGE@microchip.com --- arch/arm/boot/dts/sama7g5-pinfunc.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/sama7g5-pinfunc.h b/arch/arm/boot/dts/sama7g5-pinfunc.h index 22fe9e522a97..4eb30445d205 100644 --- a/arch/arm/boot/dts/sama7g5-pinfunc.h +++ b/arch/arm/boot/dts/sama7g5-pinfunc.h @@ -765,7 +765,7 @@ #define PIN_PD20__PCK0 PINMUX_PIN(PIN_PD20, 1, 3) #define PIN_PD20__FLEXCOM2_IO3 PINMUX_PIN(PIN_PD20, 2, 2) #define PIN_PD20__PWMH3 PINMUX_PIN(PIN_PD20, 3, 4) -#define PIN_PD20__CANTX4 PINMUX_PIN(PIN_PD20, 5, 2) +#define PIN_PD20__CANTX4 PINMUX_PIN(PIN_PD20, 4, 2) #define PIN_PD20__FLEXCOM5_IO0 PINMUX_PIN(PIN_PD20, 6, 5) #define PIN_PD21 117 #define PIN_PD21__GPIO PINMUX_PIN(PIN_PD21, 0, 0) From 6d4518a086b2cce1f7935eb5a88a7f03e241f640 Mon Sep 17 00:00:00 2001 From: Mihai Sain Date: Tue, 26 Oct 2021 16:20:34 +0300 Subject: [PATCH 2/6] ARM: dts: at91: sama5d2_xplained: remove PA11__SDMMC0_VDDSEL from pinctrl I/O voltage for eMMC is always 3.3V because PA11__SDMMC0_VDDSEL is tied with 10K resistor to GND. U13 switch S1 is always selected as voltage rail of 3.3V for VCCQ power pin from MPU controller and eMMC flash. Removing PA11 from pinctrl because it remains unused. Signed-off-by: Mihai Sain Reviewed-by: Eugen Hristev Signed-off-by: Eugen Hristev Signed-off-by: Nicolas Ferre Link: https://lore.kernel.org/r/20211026132034.678655-1-eugen.hristev@microchip.com --- arch/arm/boot/dts/at91-sama5d2_xplained.dts | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/arch/arm/boot/dts/at91-sama5d2_xplained.dts b/arch/arm/boot/dts/at91-sama5d2_xplained.dts index b1e854f658de..9bf2ec0ba3e2 100644 --- a/arch/arm/boot/dts/at91-sama5d2_xplained.dts +++ b/arch/arm/boot/dts/at91-sama5d2_xplained.dts @@ -66,7 +66,7 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_sdmmc0_default>; non-removable; - mmc-ddr-1_8v; + mmc-ddr-3_3v; status = "okay"; }; @@ -619,10 +619,9 @@ bias-disable; }; - ck_cd_rstn_vddsel { + ck_cd_rstn { pinmux = , , - , ; bias-disable; }; From b3111fe15df5e420f5251bad612fcf6915392c92 Mon Sep 17 00:00:00 2001 From: Oleksij Rempel Date: Thu, 11 Nov 2021 09:10:45 +0100 Subject: [PATCH 3/6] ARM: dts: at91: add Microchip EVB-KSZ9477 board Add KSZ9477 managed switch evaluation kit with SAMA5D36 MPU: https://www.microchip.com/en-us/development-tool/evb-ksz9477 Signed-off-by: Oleksij Rempel Signed-off-by: Nicolas Ferre Link: https://lore.kernel.org/r/20211111081045.711323-1-o.rempel@pengutronix.de --- arch/arm/boot/dts/Makefile | 1 + .../arm/boot/dts/at91-sama5d3_ksz9477_evb.dts | 209 ++++++++++++++++++ 2 files changed, 210 insertions(+) create mode 100644 arch/arm/boot/dts/at91-sama5d3_ksz9477_evb.dts diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index 0de64f237cd8..f79585f6e80b 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -61,6 +61,7 @@ dtb-$(CONFIG_SOC_SAM_V7) += \ at91-sama5d2_icp.dtb \ at91-sama5d2_ptc_ek.dtb \ at91-sama5d2_xplained.dtb \ + at91-sama5d3_ksz9477_evb.dtb \ at91-sama5d3_xplained.dtb \ at91-dvk_som60.dtb \ at91-gatwick.dtb \ diff --git a/arch/arm/boot/dts/at91-sama5d3_ksz9477_evb.dts b/arch/arm/boot/dts/at91-sama5d3_ksz9477_evb.dts new file mode 100644 index 000000000000..443e8b022897 --- /dev/null +++ b/arch/arm/boot/dts/at91-sama5d3_ksz9477_evb.dts @@ -0,0 +1,209 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright (c) 2021 Oleksij Rempel , Pengutronix + */ +/dts-v1/; +#include "sama5d36.dtsi" + +/ { + model = "EVB-KSZ9477"; + compatible = "microchip,sama5d3-ksz9477-evb", "atmel,sama5d36", + "atmel,sama5d3", "atmel,sama5"; + + chosen { + stdout-path = &dbgu; + }; + + reg_3v3: regulator-3v3 { + compatible = "regulator-fixed"; + regulator-name = "3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + reg_vcc_mmc0: regulator-mmc0 { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_mcc0_vcc>; + regulator-name = "mmc0-vcc"; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <3300000>; + gpio = <&pioE 2 GPIO_ACTIVE_LOW>; + }; +}; + +&dbgu { + status = "okay"; +}; + +&ebi { + pinctrl-0 = <&pinctrl_ebi_nand_addr>; + pinctrl-names = "default"; + status = "okay"; +}; + +&i2c0 { + pinctrl-0 = <&pinctrl_i2c0_pu>; + status = "okay"; +}; + +&macb0 { + phy-mode = "rgmii"; + status = "okay"; + + fixed-link { + speed = <1000>; + full-duplex; + }; +}; + +&main_xtal { + clock-frequency = <12000000>; +}; + +&mmc0 { + pinctrl-0 = <&pinctrl_mmc0_clk_cmd_dat0 &pinctrl_mmc0_dat1_3 + &pinctrl_mmc0_dat4_7 &pinctrl_mmc0_cd>; + status = "okay"; + + slot@0 { + reg = <0>; + bus-width = <8>; + cd-gpios = <&pioE 0 GPIO_ACTIVE_LOW>; + disable-wp; + vmmc-supply = <®_vcc_mmc0>; + vqmmc-supply = <®_3v3>; + }; +}; + +&nand_controller { + status = "okay"; + + nand@3 { + reg = <0x3 0x0 0x2>; + atmel,rb = <0>; + nand-bus-width = <8>; + nand-ecc-mode = "hw"; + nand-ecc-strength = <4>; + nand-ecc-step-size = <512>; + nand-on-flash-bbt; + label = "atmel_nand"; + }; +}; + +&slow_xtal { + clock-frequency = <32768>; +}; + +&spi0 { + cs-gpios = <&pioD 13 GPIO_ACTIVE_LOW>, <0>, <0>, + <&pioD 16 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + +&spi1 { + pinctrl-0 = <&pinctrl_spi_ksz>; + cs-gpios = <&pioC 25 GPIO_ACTIVE_LOW>; + status = "okay"; + + switch@0 { + compatible = "microchip,ksz9477"; + reg = <0>; + spi-max-frequency = <1000000>; + spi-cpha; + spi-cpol; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + label = "lan1"; + }; + + port@1 { + reg = <1>; + label = "lan2"; + }; + + port@2 { + reg = <2>; + label = "lan3"; + }; + + port@3 { + reg = <3>; + label = "lan4"; + }; + + port@4 { + reg = <4>; + label = "lan5"; + }; + + port@5 { + reg = <5>; + label = "cpu"; + ethernet = <&macb0>; + phy-mode = "rgmii-txid"; + + fixed-link { + speed = <1000>; + full-duplex; + }; + }; + }; + }; +}; + +&usb0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usba_vbus>; + atmel,vbus-gpio = <&pioE 9 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; + +&pinctrl { + board { + pinctrl_i2c0_pu: i2c0-pu { + atmel,pins = + , + ; + }; + + pinctrl_mmc0_cd: mmc0-cd { + atmel,pins = ; + }; + + pinctrl_mcc0_vcc: mmc0-vcc { + atmel,pins = ; + }; + + pinctrl_spi_ksz: spi-ksz { + atmel,pins = + < + /* SPI1_MISO */ + AT91_PIOC 22 AT91_PERIPH_A AT91_PINCTRL_PULL_UP + /* SPI1_MOSI */ + AT91_PIOC 23 AT91_PERIPH_A AT91_PINCTRL_NONE + /* SPI1_SPCK */ + AT91_PIOC 24 AT91_PERIPH_A AT91_PINCTRL_NONE + + /* SPI CS */ + AT91_PIOC 25 AT91_PERIPH_GPIO AT91_PINCTRL_NONE + /* switch IRQ */ + AT91_PIOB 28 AT91_PERIPH_GPIO AT91_PINCTRL_DEGLITCH + /* switch PME_N, SoC IN */ + AT91_PIOC 30 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP + /* switch RST */ + AT91_PIOC 31 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP_DEGLITCH + >; + }; + + pinctrl_usba_vbus: usba-vbus { + atmel,pins = + ; + }; + }; +}; From cf4060f1bb643495742f3630ab98a7b44fc5c0fd Mon Sep 17 00:00:00 2001 From: Tudor Ambarus Date: Thu, 9 Dec 2021 12:25:42 +0200 Subject: [PATCH 4/6] ARM: dts: at91: sama5d2: Name the qspi clock Naming clocks is a good practice. The atmel-quadspi driver supports an unnamed clock for the peripheral clock in order to be backward compatible with old DTs, but it is recommended to name the clocks on new DTs. The driver's bindings file requires the clock-names property, so name the clock. Signed-off-by: Tudor Ambarus Signed-off-by: Nicolas Ferre Link: https://lore.kernel.org/r/20211209102542.254153-1-tudor.ambarus@microchip.com --- arch/arm/boot/dts/sama5d2.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm/boot/dts/sama5d2.dtsi b/arch/arm/boot/dts/sama5d2.dtsi index 801969c113d6..09c741e8ecb8 100644 --- a/arch/arm/boot/dts/sama5d2.dtsi +++ b/arch/arm/boot/dts/sama5d2.dtsi @@ -288,6 +288,7 @@ reg-names = "qspi_base", "qspi_mmap"; interrupts = <52 IRQ_TYPE_LEVEL_HIGH 7>; clocks = <&pmc PMC_TYPE_PERIPHERAL 52>; + clock-names = "pclk"; #address-cells = <1>; #size-cells = <0>; status = "disabled"; @@ -299,6 +300,7 @@ reg-names = "qspi_base", "qspi_mmap"; interrupts = <53 IRQ_TYPE_LEVEL_HIGH 7>; clocks = <&pmc PMC_TYPE_PERIPHERAL 53>; + clock-names = "pclk"; #address-cells = <1>; #size-cells = <0>; status = "disabled"; From 0081a525ceef14e950172def4af14c3f652fb4a2 Mon Sep 17 00:00:00 2001 From: Tudor Ambarus Date: Thu, 9 Dec 2021 14:36:42 +0200 Subject: [PATCH 5/6] ARM: dts: at91: sama7g5: Add QSPI nodes sama7g5 embedds 2 instances of QSPI controller: 1/ OSPI0 Supporting Up to 200 MHz DDR. Octal, TwinQuad, Hyperflash and OctaFlash Protocols Supported. 2/ QSPI1 Supporting Up to 90 MHz DDR/133 MHz SDR. Signed-off-by: Tudor Ambarus Signed-off-by: Nicolas Ferre Link: https://lore.kernel.org/r/20211209123643.341892-1-tudor.ambarus@microchip.com --- arch/arm/boot/dts/sama7g5.dtsi | 30 ++++++++++++++++++++++++++++++ 1 file changed, 30 insertions(+) diff --git a/arch/arm/boot/dts/sama7g5.dtsi b/arch/arm/boot/dts/sama7g5.dtsi index 7039311bf678..eddcfbf4d223 100644 --- a/arch/arm/boot/dts/sama7g5.dtsi +++ b/arch/arm/boot/dts/sama7g5.dtsi @@ -181,6 +181,36 @@ clock-names = "t0_clk", "t1_clk", "t2_clk", "slow_clk"; }; + qspi0: spi@e080c000 { + compatible = "microchip,sama7g5-ospi"; + reg = <0xe080c000 0x400>, <0x20000000 0x10000000>; + reg-names = "qspi_base", "qspi_mmap"; + interrupts = ; + dmas = <&dma0 AT91_XDMAC_DT_PERID(41)>, + <&dma0 AT91_XDMAC_DT_PERID(40)>; + dma-names = "tx", "rx"; + clocks = <&pmc PMC_TYPE_PERIPHERAL 78>, <&pmc PMC_TYPE_GCK 78>; + clock-names = "pclk", "gclk"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + qspi1: spi@e0810000 { + compatible = "microchip,sama7g5-qspi"; + reg = <0xe0810000 0x400>, <0x30000000 0x10000000>; + reg-names = "qspi_base", "qspi_mmap"; + interrupts = ; + dmas = <&dma0 AT91_XDMAC_DT_PERID(43)>, + <&dma0 AT91_XDMAC_DT_PERID(42)>; + dma-names = "tx", "rx"; + clocks = <&pmc PMC_TYPE_PERIPHERAL 79>, <&pmc PMC_TYPE_GCK 79>; + clock-names = "pclk", "gclk"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + adc: adc@e1000000 { compatible = "microchip,sama7g5-adc"; reg = <0xe1000000 0x200>; From 078c2a0e8e60bb3fe78cf50b5da1620a4e13e0cd Mon Sep 17 00:00:00 2001 From: Tudor Ambarus Date: Thu, 9 Dec 2021 14:36:43 +0200 Subject: [PATCH 6/6] ARM: dts: at91: sama7g5ek: Add QSPI0 node QSPI0 comunicates with a MX66LM1G45G SPI NOR flash. Enable the controller and describe the flash. Signed-off-by: Tudor Ambarus Signed-off-by: Nicolas Ferre Link: https://lore.kernel.org/r/20211209123643.341892-2-tudor.ambarus@microchip.com --- arch/arm/boot/dts/at91-sama7g5ek.dts | 73 ++++++++++++++++++++++++++++ 1 file changed, 73 insertions(+) diff --git a/arch/arm/boot/dts/at91-sama7g5ek.dts b/arch/arm/boot/dts/at91-sama7g5ek.dts index 0e1975c6812e..ccf9e224da78 100644 --- a/arch/arm/boot/dts/at91-sama7g5ek.dts +++ b/arch/arm/boot/dts/at91-sama7g5ek.dts @@ -13,6 +13,7 @@ #include "sama7g5.dtsi" #include #include +#include / { model = "Microchip SAMA7G5-EK"; @@ -134,6 +135,59 @@ cpu-supply = <&vddcpu>; }; +&qspi0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_qspi>; + status = "okay"; + + flash@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <133000000>; + spi-tx-bus-width = <8>; + spi-rx-bus-width = <8>; + m25p,fast-read; + + at91bootstrap@0 { + label = "ospi: at91bootstrap"; + reg = <0x0 0x40000>; + }; + + bootloader@40000 { + label = "ospi: bootloader"; + reg = <0x40000 0xc0000>; + }; + + bootloaderenvred@100000 { + label = "ospi: bootloader env redundant"; + reg = <0x100000 0x40000>; + }; + + bootloaderenv@140000 { + label = "ospi: bootloader env"; + reg = <0x140000 0x40000>; + }; + + dtb@180000 { + label = "ospi: device tree"; + reg = <0x180000 0x80000>; + }; + + kernel@200000 { + label = "ospi: kernel"; + reg = <0x200000 0x600000>; + }; + + rootfs@800000 { + label = "ospi: rootfs"; + reg = <0x800000 0x7800000>; + }; + + }; +}; + &dma0 { status = "okay"; }; @@ -555,6 +609,25 @@ bias-disable; }; + pinctrl_qspi: qspi { + pinmux = , + , + , + , + , + , + , + , + , + , + , + , + ; + bias-disable; + slew-rate = <0>; + atmel,drive-strength = ; + }; + pinctrl_sdmmc0_default: sdmmc0_default { cmd_data { pinmux = ,