ASoC: fsl_utils: Add function to handle PLL clock source

i.MX8MQ/MN/MM/MP platforms typically have 2 AUDIO PLLs being
configured to handle 8kHz and 11kHz series audio rates.
Add common function in fsl_utils to handle these two PLL
clock source, which are needed by CPU DAI drivers

Signed-off-by: Shengjiu Wang <shengjiu.wang@nxp.com>
Link: https://lore.kernel.org/r/1656667961-1799-2-git-send-email-shengjiu.wang@nxp.com
Signed-off-by: Mark Brown <broonie@kernel.org>
This commit is contained in:
Shengjiu Wang 2022-07-01 17:32:36 +08:00 • committed by Mark Brown
commit 7bad812554
No known key found for this signature in database
GPG key ID: 24D68B725D5487D0
2 changed files with 76 additions and 0 deletions