dmaengine: xilinx_dma: Freeup active list based on descriptor completion bit

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AXIDMA IP in SG mode sets completion bit to 1 when the transfer is
completed. Read this bit to move descriptor from active list to the
done list. This feature is needed when interrupt delay timeout and
IRQThreshold is enabled i.e Dly_IrqEn is triggered w/o completing
interrupt threshold.

Signed-off-by: Radhey Shyam Pandey <radhey.shyam.pandey@amd.com>
Link: https://lore.kernel.org/r/1691387509-2113129-6-git-send-email-radhey.shyam.pandey@amd.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>

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Radhey Shyam Pandey 2023-08-07 11:21:44 +05:30 • committed by Vinod Koul

parent 491e9d4096

commit 7bcdaa6581

1 changed files with 9 additions and 0 deletions

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drivers/dma/xilinx/xilinx_dma.c

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