drm/bridge: analogix_dp: some rockchip chips need to flip REF_CLK bit setting

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As vendor document indicate, when REF_CLK bit set 0, then DP
phy's REF_CLK should switch to 24M source clock.

But due to IC PHY layout mistaken, some chips need to flip this
bit(like RK3288), and unfortunately they didn't indicate in the
DP version register. That's why we have to make this little hack.

Signed-off-by: Yakir Yang <ykk@rock-chips.com>
Reviewed-by: Tomasz Figa <tomasz.figa@chromium.com>
Tested-by: Javier Martinez Canillas <javier@osg.samsung.com>
Reviewed-by: Sean Paul <seanpaul@chromium.org>

...

This commit is contained in:

Yakir Yang 2016-06-29 17:15:18 +08:00

parent cb5571fcf8

commit 7bdc072086

3 changed files with 14 additions and 4 deletions

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5

include/drm/bridge/analogix_dp.h

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