arm64/cpufeature: Add remaining feature bits in ID_AA64ISAR0 register

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Enable TLB features bit in ID_AA64ISAR0 register as per ARM DDI 0487F.a
specification.

Cc: Catalin Marinas <catalin.marinas@arm.com>
Cc: Will Deacon <will@kernel.org>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Suzuki K Poulose <suzuki.poulose@arm.com>
Cc: linux-arm-kernel@lists.infradead.org
Cc: linux-kernel@vger.kernel.org

Suggested-by: Will Deacon <will@kernel.org>
Signed-off-by: Anshuman Khandual <anshuman.khandual@arm.com>
Reviewed-by: Suzuki K Poulose <suzuki.poulose@arm.com>
Link: https://lore.kernel.org/r/1589881254-10082-10-git-send-email-anshuman.khandual@arm.com
Signed-off-by: Will Deacon <will@kernel.org>

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This commit is contained in:

Anshuman Khandual 2020-05-19 15:10:46 +05:30 • committed by Will Deacon

parent fcd6535322

commit 7cd51a5a84

2 changed files with 2 additions and 0 deletions

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arch/arm64/include/asm/sysreg.h

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arch/arm64/kernel/cpufeature.c

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