drm/i915: Clear VLV_IIR after PIPESTAT

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On VLV/CHV VLV_IIR is not double double buffered, and it doesn't detect
edges from PIPESTAT & co. like it does on gen4. Instead it just
directly latches the level from PIPESTAT & co. That means we must clear
VLV_IIR after PIPESTAT & co. or else we'll get a spurious bit in VLV_IIR
every single time.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1460571598-24452-4-git-send-email-ville.syrjala@linux.intel.com
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>

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Ville Syrjälä 2016-04-13 21:19:49 +03:00

parent 34c7b8a7b8

commit 7ce4d1f273

1 changed files with 21 additions and 15 deletions

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drivers/gpu/drm/i915/i915_irq.c

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