clk: renesas: r8a77990: Correct parent clock of DU

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According to the R-Car Gen3 Hardware Manual Rev 1.00, the parent clock
of the DU module clocks on R-Car E3 is S1D1.

Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
Fixes: 3570a2af47 ("clk: renesas: cpg-mssr: Add support for R-Car E3")
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Acked-by: Stephen Boyd <sboyd@kernel.org>
Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>

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Takeshi Kihara 2018-10-12 16:48:34 +09:00 • committed by Geert Uytterhoeven

parent 396bc9d40d

commit 7cf3a216a2

1 changed files with 2 additions and 2 deletions

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drivers/clk/renesas/r8a77990-cpg-mssr.c

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