drm/omap: work-around for errata i886

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DRA7 errata i886 (FPDLink PLL Unlocks With Certain SoC PLL M/N Values)
says that FPDLink is sensitive to jitter on the vout clock, and that low
PLL M and N values result in more jitter than high M and N values.

This patch implements a workaround for the problem by changing the PLL
setup to search for clocks starting from high M and N values, instead of
low values. This should not cause any functional change, and only
reduces the jitter.

Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>

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Tomi Valkeinen 2016-01-05 11:43:13 +02:00

parent 320d8c3d38

commit 7d267f068a

1 changed files with 9 additions and 8 deletions

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drivers/gpu/drm/omapdrm/dss/pll.c

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