cxl/acpi: Add downstream port data to cxl_port instances

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In preparation for infrastructure that enumerates and configures the CXL
decode mechanism of an upstream port to its downstream ports, add a
representation of a CXL downstream port.

On ACPI systems the top-most logical downstream ports in the hierarchy
are the host bridges (ACPI0016 devices) that decode the memory windows
described by the CXL Early Discovery Table Fixed Memory Window
Structures (CEDT.CFMWS).

Reviewed-by: Alison Schofield <alison.schofield@intel.com>
Link: https://lore.kernel.org/r/162325450624.2293126.3533006409920271718.stgit@dwillia2-desk3.amr.corp.intel.com
Signed-off-by: Dan Williams <dan.j.williams@intel.com>

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This commit is contained in:

Dan Williams 2021-06-09 09:01:46 -07:00

parent 3feaa2d358

commit 7d4b5ca2e2

4 changed files with 180 additions and 4 deletions

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13

Documentation/ABI/testing/sysfs-bus-cxl

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43

drivers/cxl/acpi.c

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107

drivers/cxl/core.c

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21

drivers/cxl/cxl.h

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