sh_eth: Ensure proper ordering of descriptor active bit write/read

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When submitting a DMA descriptor, the active bit must be written last.
When reading a completed DMA descriptor, the active bit must be read
first.

Add memory barriers to ensure that this ordering is maintained.

Signed-off-by: Ben Hutchings <ben.hutchings@codethink.co.uk>
Signed-off-by: David S. Miller <davem@davemloft.net>

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Ben Hutchings 2015-03-03 00:52:00 +00:00 • committed by David S. Miller

parent eee617a1c3

commit 7d7355f58b

1 changed files with 6 additions and 0 deletions

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drivers/net/ethernet/renesas/sh_eth.c

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