drm/amd/display: Send DPM0 clock values to DMU

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[why & how]
Z8 Retention requires clocks to be put into bypass for the PLL
to be powered down.

Notify DMU of the DPM0 clock values, which is likely always going
to be running of a bypass clock.

Reviewed-by: Leo Chen <leo.chen@amd.com>
Signed-off-by: Ovidiu Bunea <ovidiu.bunea@amd.com>
Signed-off-by: James Lin <pinglei.lin@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

...

This commit is contained in:

Ovidiu Bunea 2026-07-30 23:50:04 -04:00 • committed by Alex Deucher

parent 322a0695ac

commit 7dd3e8cc11

4 changed files with 21 additions and 0 deletions

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12

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_clk_mgr.c

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5

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_clk_mgr.h

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1

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42b/dcn42b_clk_mgr.c

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3

drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h

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