KVM: riscv: Add a G-stage PTE cmpxchg helper

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Permission-only G-stage PTE updates can run in parallel once they are
moved to the read side of mmu_lock. Plain set_pte() is not enough for
that case because another CPU may update the same PTE first.

x86 handles the same class of SPTE races with cmpxchg-based updates in
its fast page fault and TDP MMU paths. Add a small RISC-V helper for
atomic G-stage PTE updates. The helper reports contention to the caller
and flushes the target range only when the PTE value actually changes.

Signed-off-by: Jinyu Tang <tjytimi@163.com>
Reviewed-by: Anup Patel <anup@brainfault.org>
Link: https://lore.kernel.org/r/20260517153427.94889-4-tjytimi@163.com
Signed-off-by: Anup Patel <anup@brainfault.org>

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Jinyu Tang 2026-05-17 23:34:25 +08:00 • committed by Anup Patel

parent cc98f006c6

commit 7dd416fdd3

2 changed files with 18 additions and 0 deletions

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4

arch/riscv/include/asm/kvm_gstage.h

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14

arch/riscv/kvm/gstage.c

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