clk: samsung: Add CLK_SET_RATE_PARENT to some AUDSS CLK CON clocks

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This allows clk rate propagation up to the clock tree so EPLL
can be reprogrammed indirectly when setting rate of the Audio
Subsystem clocks.
The advantage is that sound machine driver can operate only
on the leaf clocks rather than explicitly re-configuring
the root clock (EPLL).

Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>

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Sylwester Nawrocki 2017-07-17 14:39:21 +02:00

parent 41097f25e9

commit 7df45a532c

1 changed files with 4 additions and 4 deletions

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drivers/clk/samsung/clk-exynos-audss.c

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