clk: renesas: r9a09g057: Add reset entry for SYS

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Add the missing reset entry for the `SYS` module in the clock driver. The
corresponding core clock entry for `SYS` is already present.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/20250102181839.352599-6-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>

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Lad Prabhakar 2025-01-02 18:18:38 +00:00 • committed by Geert Uytterhoeven

parent 7088d2d7e9

commit 7e3557b4dd

1 changed files with 1 additions and 0 deletions

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drivers/clk/renesas/r9a09g057-cpg.c

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