drm/msm/a8xx: Fix ubwc config related to swizzling

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To disable l2/l3 swizzling in A8x, set the respective bits in both
GRAS_NC_MODE_CNTL and RB_CCU_NC_MODE_CNTL registers. This is required
for Glymur where it is recommended to keep l2/l3 swizzling disabled.

Fixes: 288a932008 ("drm/msm/adreno: Introduce A8x GPU Support")
Signed-off-by: Akhil P Oommen <akhilpo@oss.qualcomm.com>
Message-ID: <20260305-a8xx-ubwc-fix-v1-1-d99b6da4c5a9@oss.qualcomm.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Signed-off-by: Rob Clark <robin.clark@oss.qualcomm.com>

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Akhil P Oommen 2026-03-05 23:51:16 +05:30 • committed by Rob Clark

parent e4eb6e4dd6

commit 7e459c4126

1 changed files with 12 additions and 2 deletions

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drivers/gpu/drm/msm/adreno/a8xx_gpu.c

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