clk: renesas: r9a06g032: Fix UART clkgrp bitsel

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[ Upstream commit 2dee50ab9e ]

There are two UART clock groups, each having a mux to select its
upstream clock source. The register/bit definitions for accessing these
two muxes appear to have been reversed since introduction. Correct them
so as to match the hardware manual.

Fixes: 4c3d88526e ("clk: renesas: Renesas R9A06G032 clock driver")

Signed-off-by: Ralph Siemsen <ralph.siemsen@linaro.org>
Reviewed-by: Phil Edworthy <phil.edworthy@renesas.com>
Link: https://lore.kernel.org/r/20220518182527.1693156-1-ralph.siemsen@linaro.org
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Sasha Levin <sashal@kernel.org>

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Ralph Siemsen 2022-05-18 14:25:27 -04:00 • committed by Greg Kroah-Hartman

parent ec254dac7a

commit 7e7963a5bd

1 changed files with 4 additions and 4 deletions

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drivers/clk/renesas/r9a06g032-clocks.c

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