ARM i.MX6q: Mark VPU and IPU AXI transfers as cacheable, increase IPU priority

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This is needed so that the IPU framebuffer scanout cannot be
starved by VPU or GPU activity.
Some boards like the SabreLite and SabreSD seem to set this in
the DCD already, but the documented register reset values do not
contain the necessary settings.

Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>

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Philipp Zabel 2014-02-24 14:51:50 +01:00 • committed by Shawn Guo

parent ef3adc187c

commit 7ea653efa9

1 changed files with 34 additions and 0 deletions

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arch/arm/mach-imx/mach-imx6q.c

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