clk: davinci: pll-dm646x: keep PLL2 SYSCLK1 always enabled

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PLL2 SYSCLK1 on DM646x is connected to DDR2 PHY and cannot
be disabled. Mark it so to prevent unused clock disable
infrastructure from disabling it.

Signed-off-by: Sekhar Nori <nsekhar@ti.com>
Reviewed-by: David Lechner <david@lechnology.com>
Signed-off-by: Michael Turquette <mturquette@baylibre.com>
Link: lkml.kernel.org/r/20180525181150.17873-5-david@lechnology.com

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Sekhar Nori 2018-05-25 13:11:45 -05:00 • committed by Michael Turquette

parent 715478bb63

commit 7f02f18e7f

1 changed files with 1 additions and 1 deletions

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drivers/clk/davinci/pll-dm646x.c

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