irqchip/gic-v3: Add quirks for HIP06/07 invalid GICD_TYPER erratum 161010803

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It looks like the HIP06/07 SoCs have extra bits in their GICD_TYPER
registers, which confuse the GICv3.1 code (these systems appear to
expose ESPIs while they actually don't).

Detect these systems as early as possible and wipe the fields that
should be RES0 in the register.

Tested-by: John Garry <john.garry@huawei.com>
Signed-off-by: Marc Zyngier <maz@kernel.org>

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This commit is contained in:

Marc Zyngier 2019-07-31 17:29:33 +01:00

parent 25edaed6c7

commit 7f2481b39b

2 changed files with 48 additions and 10 deletions

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2

Documentation/arm64/silicon-errata.rst

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56

drivers/irqchip/irq-gic-v3.c

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