clk: clocking-wizard: Fix the round rate handling for versal

Browse source

Fix the `clk_round_rate` implementation for Versal platforms by calling
the Versal-specific divider calculation helper. The existing code used
the generic divider routine, which results in incorrect round rate.

Fixes: 7681f64e64 ("clk: clocking-wizard: calculate dividers fractional parts")
Signed-off-by: Shubhrajyoti Datta <shubhrajyoti.datta@amd.com>
Link: https://lore.kernel.org/r/20250625054114.28273-1-shubhrajyoti.datta@amd.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>

...

This commit is contained in:

Shubhrajyoti Datta 2025-06-25 11:11:14 +05:30 • committed by Stephen Boyd

parent 264200cc3a

commit 7f5e9ca0a4

No known key found for this signature in database

GPG key ID: AD028897C6E49525

1 changed files with 1 additions and 1 deletions

Show all changes Ignore whitespace when comparing lines Ignore changes in amount of whitespace Ignore changes in whitespace at EOL

Download patch file Download diff file Expand all files Collapse all files

2

drivers/clk/xilinx/clk-xlnx-clock-wizard.c

View file