clk: rockchip: rk3568: Add PLL rate for 101MHz

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This patch adds PLL setting for not so common resolution as 1920x720-50.00,
which can be set using 2500 horizontal signals and 808 vertical.

Signed-off-by: Alibek Omarov <a1ba.omarov@gmail.com>
Reviewed-by: Sascha Hauer <s.hauer@pengutronix.de>
Link: https://lore.kernel.org/r/20230614134716.1055862-1-a1ba.omarov@gmail.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>

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Alibek Omarov 2023-06-14 16:47:16 +03:00 • committed by Heiko Stuebner

parent 06c2afb862

commit 7f890a885f

1 changed files with 1 additions and 0 deletions

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drivers/clk/rockchip/clk-rk3568.c

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