dt-bindings: clock: Add StarFive JH7110 system clock and reset generator

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Add bindings for the system clock and reset generator (SYSCRG) on the
JH7110 RISC-V SoC by StarFive Ltd.

Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Reviewed-by: Emil Renner Berthing <emil.renner.berthing@canonical.com>
Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>

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Emil Renner Berthing 2023-04-01 19:19:13 +08:00 • committed by Conor Dooley

parent eeac8ede17

commit 7fce1e39f0

3 changed files with 449 additions and 0 deletions

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104

Documentation/devicetree/bindings/clock/starfive,jh7110-syscrg.yaml

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203

include/dt-bindings/clock/starfive,jh7110-crg.h

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142

include/dt-bindings/reset/starfive,jh7110-crg.h

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