clk: canaan: Clear rate fields before reprogramming dividers

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The rate set_rate helpers perform a read-modify-write on the divider
and multiplier registers but only ever OR the new value in, without
first masking off the existing field. The first write after reset lands
on a zeroed field and looks correct, but any later reprogramming leaves
the old bits set: the field becomes the bitwise OR of the previous and
new encodings, corrupting the divider or multiplier.

Mask off each field before writing the new value so reprogramming a
clock to a different rate produces the intended register contents.

Fixes: a7b7c7c6c0 ("clk: canaan: Add clock driver for Canaan K230")
Signed-off-by: David Carlier <devnexen@gmail.com>
Reviewed-by: Brian Masney <bmasney@redhat.com>
Acked-by: Xukai Wang <kingxukai@zohomail.com>
Signed-off-by: Brian Masney <bmasney@redhat.com>

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David Carlier 2026-06-18 05:50:30 +01:00 • committed by Brian Masney

parent d4873b9181

commit 804bac4a26

1 changed files with 4 additions and 0 deletions

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drivers/clk/clk-k230.c

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