iommu/tegra: smmu: Compute PFN mask at runtime

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The SMMU on Tegra30 and Tegra114 supports addressing up to 4 GiB of
physical memory. On Tegra124 the addressable physical memory was
extended to 16 GiB. The page frame number stored in PTEs therefore
requires 20 or 22 bits, depending on SoC generation.

In order to cope with this, compute the proper value at runtime.

Reported-by: Joseph Lo <josephl@nvidia.com>
Cc: Hiroshi Doyu <hdoyu@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Joerg Roedel <jroedel@suse.de>

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Thierry Reding 2015-03-27 11:07:27 +01:00 • committed by Joerg Roedel

parent 836a8ac9fe

commit 804cb54cbb

1 changed files with 10 additions and 5 deletions

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drivers/iommu/tegra-smmu.c

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