drm/xe/irq: Ensure primary GuC won't clobber media GuC's interrupt mask

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Although primary and media GuC share a single interrupt enable bit, they
each have distinct bits in the mask register.  Although we always enable
interrupts for the primary GuC before the media GuC today (and never
disable either of them), this might not always be the case in the
future, so use a RMW when updating the mask register to ensure the other
GuC's mask doesn't get clobbered.

Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
Link: https://lore.kernel.org/r/20230601215244.678611-24-matthew.d.roper@intel.com
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>

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Matt Roper 2023-06-01 14:52:36 -07:00 • committed by Rodrigo Vivi

parent 8e758225e5

commit 80d6e5874a

1 changed files with 7 additions and 4 deletions

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drivers/gpu/drm/xe/xe_guc.c

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