drm/amd/display: Correct slice width calculation for YCbCr420

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[Why]
-OVT compliance testing for 5120x2880p300Hz YCbCr420 was failing due to
incorrect slice width being calculated

[How]
-Ensure slice width is divisible by 2 for 420 to comply with spec

Reviewed-by: Wenjing Liu <wenjing.liu@amd.com>
Signed-off-by: Relja Vojvodic <rvojvodi@amd.com>
Signed-off-by: Roman Li <roman.li@amd.com>
Tested-by: Dan Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

...

This commit is contained in:

Relja Vojvodic 2025-09-17 12:30:51 -04:00 • committed by Alex Deucher

parent 0975c4deb6

commit 81557c96c8

7 changed files with 8 additions and 1 deletions

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2

drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

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drivers/gpu/drm/amd/display/dc/dsc/dsc.h

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drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

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drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

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drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

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2

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

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1

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

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