clk: at91: allow 24 Mhz clock as input for PLL

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The PLL input range needs to be able to allow 24 Mhz crystal as input
Update the range accordingly in plla characteristics struct

Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com>
Link: https://lkml.kernel.org/r/1568183622-7858-1-git-send-email-eugen.hristev@microchip.com
Acked-by: Nicolas Ferre <nicolas.ferre@microchip.com>
Fixes: c561e41ce4d2 ("clk: at91: add sama5d2 PMC driver")
Signed-off-by: Stephen Boyd <sboyd@kernel.org>

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Eugen Hristev 2019-09-11 06:39:20 +00:00 • committed by Stephen Boyd

parent 69a6bcde7f

commit 81a6b601f9

1 changed files with 1 additions and 1 deletions

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drivers/clk/at91/sama5d2.c

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