arm64: dts: imx8mp-venice-gw702x: Increase HS400 USDHC clock speed

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The IMX8M reference manuals indicate in the USDHC Clock generator section
that the clock rate for DDR is 1/2 the input clock therefore HS400 rates
clocked at 200Mhz require a 400Mhz SDHC clock.

This showed about a 1.5x improvement in read performance for the eMMC's
used on the various imx8mp-venice boards.

Fixes: 0d5b288c21 ("arm64: dts: freescale: Add imx8mp-venice-gw7905-2x")
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>

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Tim Harvey 2025-07-07 13:16:57 -07:00 • committed by Shawn Guo

parent c5d9a362c7

commit 81b07d51cd

1 changed files with 2 additions and 0 deletions

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arch/arm64/boot/dts/freescale/imx8mp-venice-gw702x.dtsi

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