drm/amdkfd: correct sienna_cichlid SDMA RLC register offset error

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1.correct KFD SDMA RLC queue register offset error.
(all sdma rlc register offset is base on SDMA0.RLC0_RLC0_RB_CNTL)
2.HQD_N_REGS (19+6+7+12)
  12: the 2 more resgisters than navi1x (SDMAx_RLCy_MIDCMD_DATA{9,10})

the patch also can be fixed NULL pointer issue when read
/sys/kernel/debug/kfd/hqds on sienna_cichlid chip.

Signed-off-by: Kevin Wang <kevin1.wang@amd.com>
Reviewed-by: Likun Gao <Likun.Gao@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

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Kevin Wang 2021-05-19 11:03:11 +08:00 • committed by Alex Deucher

parent 7884245712

commit 8200b1cd85

1 changed files with 6 additions and 6 deletions

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drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10_3.c

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