clk: mediatek: add MUX_CLR_SET macro

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Some MediaTek SoCs (e.g. MT7988) define infra muxes that have neither
a clock gate nor an update register.

Add a MUX_CLR_SET convenience macro that takes only the mux register
offsets, bit shift, and width, hardcoding upd_ofs = 0 and
upd_shift = -1 so callers cannot accidentally pass bogus sentinel
values to wrongly-typed fields.

Signed-off-by: Daniel Golle <daniel@makrotopia.org>
Reviewed-by: Chen-Yu Tsai <wenst@chromium.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>

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Daniel Golle 2026-03-26 05:09:35 +00:00 • committed by Stephen Boyd

parent 254f49634e

commit 820ea6936b

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drivers/clk/mediatek/clk-mux.h

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