drm/amd/display: Do not set DRR on pipe Commit

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[WHY]
Writing to DRR registers such as OTG_V_TOTAL_MIN on the same frame as a
pipe commit can cause underflow.

Cc: stable@vger.kernel.org
Cc: Mario Limonciello <mario.limonciello@amd.com>
Reviewed-by: Jun Lei <Jun.Lei@amd.com>
Acked-by: Qingqing Zhuo <qingqing.zhuo@amd.com>
Signed-off-by: Wesley Chalmers <Wesley.Chalmers@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

...

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Wesley Chalmers 2022-11-03 22:29:31 -04:00 • committed by Alex Deucher

parent 2792f98cdb

commit 825b3772a2

1 changed files with 0 additions and 3 deletions

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drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.c

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